Drivers for Large LCD Panels 6bit RSDSTM Source Driver BU95101 No.10043EAT01 ●Description ROHMLCD drivers for large panels are display drivers optimized for large LCDs in a variety of applications, including desktop PCs, laptops, and TVs. The broad lineup is offered in low amplitude differential transmission interface type TM (RSDS ) featuring low EMI, 6bit gradation precision, and different output configurations (384 and up) for wide compatibility. ●Features 1) 384 output channels TM 2) 6bit 9pair RSDS inputs 3) Dot & n-line inversion available 4) Built-in 2ch repair amplifiers 5) γcorrection is possible 6) Built-in input data reversing function(INV) 7) Output voltage range : AVSS+0.1V ~ AVDD-0.1V 8) High speed data transfer : fCLK(MAX)=85MHz 9) Logic power supply voltage (DVDD) : 2.7 ~ 3.6V 10) Driver power supply voltage (AVDD) : 8.0 ~ 13.5V 11) Package : COF35 ●Applications TFT LCD Panels ●Line up matrix Number of outputs BU95101 BU95303 BU95306 BU95408 384 384 / 414 / 420 / 432 600 / 618 / 630 / 642 684 / 690 / 702 / 720 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/14 2010.10 - Rev.A Technical Note BU95101 ●Absolute maximum ratings Parameter Symbol Ratings Unit Logic power supply voltage DVDD -0.3 ~ +4.5 V Driver power supply voltage AVDD -0.3 ~ +14.0 V Logic input voltage VI1 -0.3 ~ DVDD+0.3 V Logic output voltage VO1 -0.3 ~ DVDD+0.3 V Driver input voltage VI2 -0.3 ~ AVDD+0.3 V Driver output voltage VO2 -0.3 ~ AVDD+0.3 V Storage temperature range Tstg -55 ~ +125 ℃ Symbol Ratings Unit Logic power supply voltage DVDD +2.7 ~ +3.6 V Driver power supply voltage AVDD +8.0 ~ +13.5 V V1 ~ V10 0.1 ~ AVDD-0.1 V Driver output voltage VO 0.1 ~ AVDD-0.1 V Output load capacitance CL 150 pF fCLK(MAX) 85 MHz Topr -20 ~ +75 ℃ ●Recommended operating range Parameter γ-correction reference voltage Maximum clock frequency Operating temperature range * AVSS=DVSS=0V www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/14 2010.10 - Rev.A Technical Note BU95101 ●Electrical characteristics (DC) (Unless otherwise noted, Ta=-20 ~ +75℃, DVDD=2.7 ~ 3.6V, AVDD=8.0 ~ 13.5V, DVSS=AVSS=0V) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Logic Part Logic supply current IDDL - 8 12 mA fclk=85MHz,Data=15h-2Ah Input “H” voltage V1H 0.7DVDD - DVDD V Input “L” voltage V1L 0 - 0.3DVDD V Input “H” current I1H1 - - +1 μA VIN=DVDD Input “L” current I1L1 -1 - - μA VIN=DVSS Output “H” voltage VOH DVDD-0.5 - - V IOH=-1.0mA Output “L” voltage VOL - - 0.5 V IOL=1.0mA IDDA - 5 10 mA noLoad, fclk=85MHz,Data=15h-2Ah RγUP 11.2 16.0 20.8 kΩ V1 ~ V5 RγLOW 11.2 16.0 20.8 kΩ V6 ~ V10 - ±20 ±30 mV Yout=0.1V ~ 1.2V,Yout=10.8V ~ 11.9V R/L,SFTR,INV,SFTL, POL,STB Dxx, SFTR, POL, INV, SFTL,CLK,STB,R/L SFTR,SFTL Driver part Driver supply current γ correction resistance Output voltage deviation VOD1*1 Output swing voltage Deviation VRMS Output voltage deviation 2 (between chips) VOD2 *2 *3 - ±10 ±20 mV Yout=1.2V ~ 10.8V - ±10 ±20 mV Yout=0.1V ~ 1.2V,Yout=10.8V ~ 11.9V - ±3 ±10 mV Yout=1.2V ~ 10.8V - - ±7.5 mV Repair input voltage V1NB 0.1 - AVDD-0.1 V Repair input “H” current I1BH -1 - +1 μA VIN=AVDD=13.5V Repair input “L” current I1BL -1 - +1 μA VIN=AVSS Driver output “H” current IREP1,2 IVOHY - -0.8 -0.4 mA Y1 ~ Y384, Vx=8 V, Yout=11V IVOHR - -2.0 -0.8 mA OREP1,2, Vx=8 V, Yout=11V IVOLY 0.4 0.8 - mA Y1 ~ Y384, Vx=4 V, Yout=1V IVOLR 0.8 2.0 - mA OREP1,2, RSDSTM input “H” voltage VIHRSDS 100 200 - mV RSDSTM input “L” voltage VILRSDS - -200 -100 mV RSDSTM common input voltage VCMRSDS 0.5 - 1.4 V Driver output“L” current Vx=4 V, Yout=1V TM RSDS Input part *1 *2 *3 *4 *5 VCMRSDS=+1.2V*4 CLKP/N,DXXP/N (X=0,1,2) VDIFF=200mV*5 VOD1=measured output voltage - averaged output voltage of all outputs VRMS=measured output swing voltage - averaged output swing voltage of all outputs VOD2=averaged output voltage - target value VCM RSDS = (VCLKP+VCLKN)/2 or (VDXXP+VDXXN)/2 VDIFF = VCLKP- VCLKN or VDXXP-VDXXN www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/14 2010.10 - Rev.A Technical Note BU95101 ●Electrical characteristics (AC) (Unless otherwise noted, Ta=-20 ~ +75℃, DVDD=2.7 ~ 3.6V, AVDD=8.0 ~ 13.5V, DVSS=AVSS=0V) Limits Parameter Symbol Unit Min. Typ. Max. Conditions Clock pulse width tw 1/85MHz - - ns Clock pulse "H" period th 4 - - ns Clock pulse "L" period tl 4 - - ns Data setup time tsu1 2 - - ns Data hold time thd1 0 - - ns Start pulse setup time tsu2 2 - - ns Start pulse hold time thd2 2 - - ns Start pulse width tWSFT 1 - 2 CLK period tdc - - 10 ns STB pulse width tWSTB 1 - - CLK period Final data timing tLDT 0 - - CLK period Time between STB↑and start pulse↑ tSTB-SFT 5 - - CLK period Time between STB↑and CLK↓ tSTB-CLK 4 - - ns tsp 14 - - ns - - 6 μs *1*3 - - 10 μs *2*3 Carry output delay time POL/STB setup time Output delay time *1 *2 *3 tdout CL=15pF The value is specified when the drive voltage value reaches the target output voltage level of 90%. he value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. Output load condition: R1=R2=R3=1kΩ, C1=C2=C3=50pF Output R1 R2 R3 (Test Probe) C1 C2 C3 Vcom=AVSS www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/14 2010.10 - Rev.A Technical Note BU95101 Y1 Y2 Y3 Y382 Y383 Y384 ●Block diagram ・・・・・・・・・・・・・・・・・ AVDD AVSS Output Buffer OREP1 IREP1 V1～V10 POL OREP2 IREP2 ・・・・・・・・・・・・・・・・・ 10 D/A Converter 6 6 6 6 6 6 ・・・・・・・・・・・・・・・・・ Level Shifter 6 6 6 6 6 6 ・・・・・・・・・・・・・・・・・ Data Latch STB 6 6 6 6 6 6 ・・・・・・・・・・・・・・・・・ Data Register D00P/N～D02P/N INV Latch D20P/N～D22P/N RSDS Rx D10P/N～D12P/N 240 bit Bi-directional Shift Register CLKP/N SFTR DVDD R/L DVSS SFTL Fig.1 Block diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/14 2010.10 - Rev.A Technical Note BU95101 ●Pin configuration IREP2 OREP2 SFTL D22P D22N D21P D21N D20P D20N D12P D12N D11P D11N D10P D10N DVDD R/L V10 V9 V8 V7 V6 AVDD AVSS V5 V4 V3 V2 V1 DVSS CLKP CLKN STB POL INV D02P D02N D01P D01N D00P D00N SFTR OREP1 IREP1 Y384 Y383 Y382 ・ ・ ・ ・ ・ ・ ・ BU95101 ・ Top View ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Y3 Y2 Y1 ↓ BUMP BUMP IC Fig.2 Pin configuration (Top View) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/14 2010.10 - Rev.A Technical Note BU95101 ●Pin descriptions Pin Name In/Out Active D00P/N ~ D02P/N D10P/N ~ D12P/N D20P/N ~ D22P/N In Differential RSDS input terminals of display data The 3-bit differential input pairs generate the internal 6-bit data through the comparison between DXXP and DXXN. CLKP/N In Differential The RSDS clock input pair generate the internal shift clock through the comparison between CLKP and CLKN. Out - Driver outputs for D/A converted 64 gray scale analog voltage. In - The shift direction of internal shift register is controlled by this pin as shown below. R/L=H : Right shift SFTR→Y1→Y384→SFTL R/L=L : Left shift SFTL→Y384→Y1→SFTR SFTR In/Out H SFTR=H：Right shift start pulse input terminal in cascade connection. SFTR=L：Carry output terminal in cascade connection. SFTL In/Out H SFTL=H：Carry output terminal in cascade connection. SFTL=L：Left shift start pulse input terminal in cascade connection. STB In INV In H Terminal to specify inverting or non-inverting of display data INV:H : Input data are inverted in the IC. INV:L : Input data are not inverted. V1 ~ V10 In - Input for the γ-correction reference voltage The following external reference voltages are input. Y1 ~ Y384 R/L Descriptions The data in the data register are transferred to the data latch at the rising edge of STB, then the gray scale voltages are output from the buffer at the falling edge of STB. POL In - At the rising edge of STB, the state of POL are transferred to the driver. POL=H : The reference voltage for odd number outputs are V1 to V5 and those for even number outputs are V6 to V10. POL=L : The reference voltage for odd number outputs are V6 to V10 and those for even number outputs are V1 to V5 IREP1,2 In - Repair amplifier input OREP1,2 Out - Repair amplifier output AVDD In - Power supply for driver block AVSS In - Ground for AVDD DVDD In - Power supply for digital block DVSS In - Ground for DVDD www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/14 2010.10 - Rev.A Technical Note BU95101 ●Relationship between Input Data and Output Terminals R/L=H (Right Shift) First Data Output Last → D00P ~ D02N D10P ~ D12N D20P ~ D22N … D00P ~ D02N D10P ~ D12N D20P ~ D22N Y1 Y2 Y3 … Y382 Y383 Y384 R/L=L (Left Shift) First Data Output Last → D00P ~ D02N D10P ~ D12N D20P ~ D22N … D00P ~ D02N D10P ~ D12N D20P ~ D22N Y382 Y383 Y384 … Y1 Y2 Y3 ●Relationship between R/L , SFTR , SFTL and Output Direction R/L pin controls the shift direction of the internal shift resistor as shown below. Terminal Right Shift Mode Left Shift Mode R/L “H” “L” SFTR Input Output SFTL Output Input Y1,Y2,Y3→Y382,Y383,Y384 Y384,Y383,Y382→Y3,Y2,Y1 Output direction ●Relationship between POL and Output Polarity POL Y1 *1 “H” “L” +*1 -*1 Y2 - + Y3 + - Y4 - + Y5 + - Y6 - + ・ ・ ・ ・ ・ ・ Y379 + - Y380 - + Y381 + - Y382 - + Y383 + - Y384 - + +: The reference voltage are V1 ~ V5 -: The reference voltage are V6 ~ V10 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/14 2010.10 - Rev.A Technical Note BU95101 ●Relationship between Input Data and Output Voltage The LCD driver output voltages are determined by the input data and 10γ-corrected power supply. 0.1V≦V10≦V9≦V8≦V7≦V6≦0.5AVDD 0.5 AVDD≦V5≦V4≦V3≦V2≦V1≦AVDD -0.1V Vout AVDD V1 V2 V3 V4 V5 VCOM V6 V7 V8 V9 V10 AVSS 00H 08H 10H 18H 20H 28H 30H 38H 3FH Input Data Fig.3 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Input data - γ correction curve 9/14 2010.10 - Rev.A Technical Note BU95101 ●γ correction Power Supply Circuit 10 external γ-corrected power supply is connected to ladder resistors inside IC. IC Internal Circuit V1 RS0 V2 RS1 V3 RS2 V4 RS3 V5 External γ-corrected power supply V6 RS4 V7 RS5 V8 RS6 V9 RS7 V10 Fig.4 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. γ correction power supply circuit 10/14 2010.10 - Rev.A Technical Note BU95101 ●RSDSTM data timing thd2 thd1 thd1 tsu2 tsu1 tsu1 CLKP/N SFTR D00P/N Y1 (0) Y1 (1) Y4 (0) Y4 (1) Y7 (0) Y7 (1) D01P/N Y1 (2) Y1 (3) Y4 (2) Y4 (3) Y7 (2) Y7 (3) D02P/N Y1 (4) Y1 (5) Y4 Y4 Y7 (4) (5) (4) Y7 (5) D10P/N Y2 (0) Y2 (1) Y5 (0) Y5 (1) Y8 (0) Y8 (1) D11P/N Y2 Y2 (3) Y5 (2) Y5 (3) Y8 (2) (2) Y8 (3) D12P/N (4) Y2 (5) Y5 (4) Y5 (5) Y2 Y8 (4) Y8 (5) D20P/N Y3 Y3 (1) Y6 (0) (0) Y6 (1) (0) D21P/N Y3 (2) Y3 (3) Y6 (2) Y6 (3) (2) Y9 (3) D22P/N Y3 (4) Y3 (5) Y6 (4) Y6 (5) Y9 (4) Y9 (5) Y9 Y9 Y9 (1) Fig.5 RSDS data timing www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/14 2010.10 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. www.rohm.com 12/14 Yout POL STB 1 2 th 0V(DVSS) INVALID tWSFT tsu2 thd2 (SFTR output) SFTL output (SFTL input) SFTR input DXXP -DXXN -CLKN CLKP tw VDIFE tl VCM EVEN ODD tsu1 thd1 tsu1 thd1 3 tdc EVEN 128 ODD tdc EVEN 129 ODD tsp tLDT Last Data Hi-Z tWSTB tSTB-SFT INVALID tSTB-CLK tSTB-CLK 1 2 3 BU95101 Technical Note ●Timing chart Fig.6 Timing chart 2010.10 - Rev.A Technical Note BU95101 ●Power Supply Sequence Maintain the following power supply order to prevent the device from being destroyed. Turn on power order : DVDD → Input signal → AVDD, V1 ~ V10 Turn off power order : AVDD, V1 ~ V10 → Input signal → DVDD Voltage AVDD V1～V10 DVDD Input signal DVSS, AVSS t ●Notes for use 1) When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special consideration to power coupling capacitance, power wiring, width of GNDwiring, and routing of connections. 2) For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of wiring. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/14 2010.10 - Rev.A Technical Note BU95101 ●Ordering part number B U Part No. 9 5 1 0 1 - Part No. S R Reel packing specification SR: A pattern side is an inner arrow. The output side is the right side. SL: A pattern side is an inner arrow. The output side is the left side. BR: A pattern side is an outside arrow. The output side is the right side. BL: A pattern side is an outside arrow. The output side is the left side. COF35 <Tape dimensions> www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. <Packing specifications> 14/14 2010.10 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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