CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H) F PACKAGE (TOP VIEW) 5 1 0 2 6 7 3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC MR CP CE TC 9 4 8 description The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low. The CD54HC4017 is characterized for operation over the full military temperature range of –55°C to 125°C. FUNCTION TABLE INPUTS CP CE MR OUTPUT STATE† L X L No change X H L No change X X H 0=H 1–9 = L ↑ L L Increments counter ↓ X L No change X ↑ L No change H ↓ L Increments counter † If n < 5, TC = H; otherwise, TC = L. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 logic diagram (positive logic) 3 0 4 7 10 1 2 3 4 1 5 5 6 6 7 9 8 11 9 12 D C MR R Q D Q C R Q D Q C R Q D Q C R Q D Q C 15 13 CE 14 CP 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q R Q TC Decoded Decimal Out 2 CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 V or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 V or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, each output pin, IO (VO > –0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . ±25 mA VCC or ground current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating (see Note 1) VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage Low-level input voltage VI VO Input voltage tt 2 6 UNIT V V 3.15 4.2 VCC = 4.5 V VCC = 6 V Output voltage VCC = 2 V VCC = 4.5 V Input transition (rise and fall) time MAX 1.5 VCC = 6 V VCC = 2 V VIL MIN 0 0.5 0 1.35 0 1.8 0 0 VCC VCC 0 1000 0 500 V V V ns VCC = 6 V 0 400 TA Operating free-air temperature –55 125 °C NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER CMOS loads TEST CONDITIONS VI = VIH or VIL, VCC IOH = –0.02 mA VOH TTL loads CMOS loads VI = VIH or VIL VI = VIH or VIL, IOH = –4 mA IOH = –5.2 mA IOL = 0.02 mA VOL TTL loads II ICC VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, IOL = 4 mA IOL = 5.2 mA IO = 0 Ci POST OFFICE BOX 655303 TA = 25°C MIN MAX MIN 2V 1.9 1.9 4.5 V 4.4 4.4 6V 5.9 5.9 4.5 V 3.98 3.7 6V 5.48 MAX UNIT V 5.2 2V 0.1 0.1 4.5 V 0.1 0.1 6V 0.1 0.1 4.5 V 0.26 0.4 V 6V 0.26 0.4 6V ±100 ±1000 nA 6V 8 160 µA 2 V to 6 V 10 10 pF • DALLAS, TEXAS 75265 3 CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) PARAMETER fclock VCC Maximum clock frequency CP tw Pulse duration MR tsu th trem 4 Setup time, CE to CP Hold time, CE to CP Removal time, MR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = 25°C MIN MAX MIN MAX 2V 6 4 4.5 V 30 20 6V 35 23 2V 80 120 4.5 V 16 24 6V 14 20 2V 80 120 4.5 V 16 24 6V 14 20 2V 75 110 4.5 V 15 22 6V 13 19 2V 0 0 4.5 V 0 0 6V 0 0 2V 5 5 4.5 V 5 5 6V 5 5 UNIT MHz ns ns ns ns CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 timing requirements CP MR CE 0 1 2 3 4 5 6 0 1 1 2 2 3 4 5 6 7 7 8 8 9 9 TC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 switching characteristics, CL = 50 pF, TA = 25°C (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd Any output VCC TC tpd Any output TC tpd Any output TC MIN MAX 4 4.5 V 20 20 6V 35 23 UNIT MAX MHz 2V 230 345 4.5 V 46 69 6V 39 59 2V 230 345 4.5 V 46 69 6V 39 59 2V 250 375 4.5 V 50 75 6V 43 64 2V 250 375 4.5 V 50 75 6V 43 64 2V 230 345 4.5 V 46 69 6V 39 59 2V 230 345 4.5 V 46 69 6V 39 59 MR tpd MIN 6 CE tpd TA = –55°C TO 125°C 2V CP tpd TA = 25°C ns ns ns ns ns ns operating characteristics PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 39 UNIT pF CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open PARAMETER From Output Under Test CL (see Note A) Test Point S1 1 kΩ ten S2 tdis tpd or tt LOAD CIRCUIT High-Level Pulse 50% VCC VCC Reference Input VCC 50% VCC 50% VCC 0V 0V Data Input tw Low-Level Pulse VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATIONS 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-ofPhase Output 90% tf 50% 10% 90% VCC 50% 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES Output Control VCC 50% VCC 50% VCC 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ 90% VOH VOL Output Waveform 2 (See Note B) ≈ VCC ≈ VCC 50% tPZH tPLH 50% 10% 90% tr 0V In-Phase Output 50% 10% 50% VCC VCC Input th tsu 10% VOL tPHZ 50% 90% VOH ≈0V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 PARAMETER MEASUREMENT INFORMATION tf tr CP VCC VS 0.5 VCC Input Level VS f max tPLH tPHL Input Level VS CE GND 1 GND tPHL tPLH VS TC VS 0–9 MR INPUT LEVEL Input Level VS Input Level VS CP GND tw GND tPLH tw tPHL tPHL VS TC VS 1–9 Input Level tPLH CE 0, TC VS VS GND tPLH CP Input Level VS 0–9 tPLH VS GND trem MR Input Level VS CE VS tsu CP GND Figure 2. Voltage Waveforms 8 POST OFFICE BOX 655303 GND tw tsu CE VS GND Input Level Input Level • DALLAS, TEXAS 75265 th VS Input Level GND PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) 8601101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8601101EA CD54HC4017F3A CD54HC4017F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8601101EA CD54HC4017F3A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 OTHER QUALIFIED VERSIONS OF CD54HC4017 : • Catalog: CD74HC4017 • Automotive: CD74HC4017-Q1 • Enhanced Product: CD74HC4017-EP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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