CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER • • • • • • • • • High-Performance 1:10 Clock Driver for General-Purpose Applications Pin-to-Pin Skew < 100 ps at VDD 3.3 V VDD Range = 2.3 V to 3.6 V Input Clock Up To 200 MHz (See Figure 7) Operating Temperature Range –40°C to 85°C Output Enable Glitch Suppression Distributes One Clock Input to Two Banks of Five Outputs Packaged in 24-Pin TSSOP Pin-to-Pin Compatible to the CDCVF2310, Except the R = 22-Ω Series Damping Resistors at Yn PW PACKAGE (TOP VIEW) GND VDD 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VDD 1G 2Y4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK VDD VDD 2Y0 2Y1 GND GND 2Y2 2Y3 VDD VDD 2G DESCRIPTION The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The CDCVF310 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 FUNCTIONAL BLOCK DIAGRAM 3 4 5 8 9 1G 2G 11 Logic Control 13 Logic Control 21 CLK 24 20 17 16 12 2 1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3 2Y4 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 FUNCTION TABLE INPUT (1) OUTPUT 1G 2G CLK 1Y[0:4] 2Y[0:4] L L ↓ L L H L ↓ CLK (1) L L H ↓ L CLK (1) H H ↓ CLK (1) CLK (1) After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION 1G 11 I Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the 1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high. 2G 13 I Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the 2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high. 1Y[0:4] 3, 4, 5, 8, 9 O Buffered output clocks 2Y[0:4] 21, 20, 17, 16, 12 O Buffered output clocks CLK 24 I Input reference frequency GND 1, 6, 7, 18, 19 VDD 2, 10, 14, 15, 22, 23 Ground DC power supply, 2.3 V – 3.6 V 3 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 DETAILED DESCRIPTION Output Enable Glitch Suppression Circuit The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the input clock) (see Figure 1). The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable operation. CLK Gn Yn tsu(en) th(en) a) Enable Mode CLK Gn Yn tsu(dis) th(dis) b) Disable Mode Figure 1. Enable and Disable Mode Relative to CLK↓ 4 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range, VDD Input voltage range, VI –0.5 V to 4.6 V (2) (3) –0.5 V to VDD + 0.5 V Output voltage range, VO (2) (3) –0.5 V to VDD + 0.5 V Input clamp current, IIK (VI < 0 or VI> VDD) ±50 mA Output clamp current, IOK (VO < 0 or VO > VDD) ±50 mA ±50 mA Continuous total output current, IO (VO = 0 to VDD) 88°C/W, high K Package thermal impedance, θJA (4): PW package 120°C/W, low K Storage temperature range Tstg (1) (2) (3) (4) –65°C to 150°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS (1) Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH NOM 2.3 2.5 3.3 Low-level output current, IOL 3.6 0.8 VDD = 2.3 V to 2.7 V 0.7 VDD = 3 V to 3.6 V 2 VDD = 2.3 V to 2.7 V VDD = 3 V to 3.6 V VDD -12 VDD = 2.3 V to 2.7 V -6 VDD = 3 V to 3.6 V 12 VDD = 2.3 V to 2.7 V 6 Operating free-air temperature, TA UNIT V V V 1.7 0 High-level output current, IOH MAX VDD = 3 V to 3.6 V Input voltage, VI (1) MIN -40 85 V mA mA °C Unused inputs must be held high or low to prevent them from floating. TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) PARAMETER fclk Clock frequency TEST CONDITIONS VDD = 2.3 V to 3.6 V, See Figure 7 MIN 0 TYP MAX UNIT 200 MHz 5 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP VIK Input voltage VDD = 3 V, II Input current VI = 0 V or VDD IDD (2) Static device current CLK = 0 V or VDD = 3.6 V, IO = 0 mA CI Input capacitance VDD = 2.3 V to 3.6 V, VI = 0 V or VDD 2.5 CO Output capacitance VDD = 2.3 V to 3.6 V, VI = 0 V or VDD 2.6 CPD Power dissipation (3) VDD = 2.3 V to 3.6 V, VI= 0 V or VDD (1) (2) (3) II = –18 mA MAX UNIT –1.2 V ±5 µA 80 µA pF pF 32 pF All typical values are with respect to nominal VDD. For dynamic IDD over Frequency see Figure 6. This is the formula for the power dissipation calculation. P_tot P_stat P_Dyn P_Load[W] P_stat V DD I DD [W] P_Dyn C_PD VDD VDD ƒ [W] P_Load C_Load VDD VDD ƒ n [W] n Number of switching output pins VDD = 3.3 V ±0.3 V PARAMETER TEST CONDITIONS VDD = min to max, VOH High-level output voltage VDD = 3 V VDD = min to max, VOL IOH IOL (1) Low-level output voltage High-level output current Low-level output current VDD = 3 V MIN IOH = –100 µA VDD - 0.2 IOH = –12 mA 2.1 IOH = –6 mA 2.4 TYP (1) MAX V IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 6 mA 0.3 VDD = 3 V, VO = 1 V VDD = 3.3 V, VO = 1.65 V VDD = 3.6 V, VO = 3.135 V VDD = 3 V, VO = 1.95 V VDD = 3.3 V, VO = 1.65 V VDD = 3.6 V, VO = 0.4 V UNIT V -37 -57 mA -38 37 57 mA 38 All typical values are with respect to nominal VDD. VDD = 2.5 V ±0.2 V PARAMETER VOH High-level output voltage VOL Low-level output voltage IOH High-level output current IOL (1) 6 Low-level output current TEST CONDITIONS MIN TYP (1) MAX VDD = min to max, IOH = –100 µA VDD = 2.3 V IOH = –6 mA VDD = min to max, IOL = 100 µA 0.2 VDD = 2.3 V IOL = 6 mA 0.4 VDD = 2.3 V, VO = 1 V VDD = 2.5 V, VO = 1.25 V VDD = 2.7 V, VO = 2.375 V VDD = 2.3 V, VO = 1.2 V VDD = 2.5 V, VO = 1.25 V VDD = 2.7 V, VO = 0.3 V All typical values are with respect to nominal VDD. VDD - 0.2 UNIT V 1.8 V -20 -36 mA -25 20 36 mA 25 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VDD = 3.3 V ±0.3 V (see Figure 2) tPLH CLK to Yn tPHL f = 0 MHz to 200 MHz (2) 1 2.8 1 2.8 (see Figure 4) 100 ns tsk(o) Output skew (Ym to Yn) 150 ps tsk(p) tsk(pp) Pulse skew (see Figure 5) 250 ps Part-to-part skew 350 tr Rise time VO = 0.4 V to 2 V ps 1.3 2.7 V/ns tf Fall time VO = 2 V to 0.4 V tsu(en) Enable setup time, G_high before CLK ↓ 1.3 0.1 2.7 V/ns ns tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns th(en) Enable hold time, G_high after CLK ↓ 0.4 ns th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns VDD = 2.5 V ±0.2 V (see Figure 2) tPLH CLK to Yn tPHL f = 0 MHz to 200 MHz (2) 1.3 4 1.3 4 tsk(o) Output skew (Ym to Yn) tsk(p) Pulse skew (see Figure 5) tsk(pp) Part-to-part skew 400 ps tr Rise time VO = 0.4 V to 1.7 V 0.5 1.6 V/ns tf Fall time VO = 1.7 V to 0.4 V 0.5 1.6 V/ns tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns th(en) Enable hold time, G_high after CLK ↓ 0.4 ns th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns (1) (2) (see Figure 4 ) 150 ns 230 ps 280 ps All typical values are with respect to nominal VDD. The tsk(o) specification is only valid for equal loading of all outputs. 7 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test 500 Ω CL = 25 pF on Yn A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: Clock Frequency ≤ 200 MHz, ZO = 50 Ω, tr < 1.2 ns, tf < 1.2 ns. Figure 2. Test Load Circuit VDD 50% VDD 0V CLK tPLH tPHL 1.7 V or 2 V Yn 0.4 V 0.4 V tr VOH 50% VDD VOL tf Figure 3. Voltage Waveforms Propagation Delay Times VDD CLK 0V VOH 50% VDD Any Y VOL VOH 50% VDD Any Y VOL tsk(o) tsk(o) Figure 4. Output Skew VDD 50% VDD CLK 0V tPLH tPHL VOH Yn 50% VDD VOL NOTE: tsk(p) = | tPLH − tPHL | Figure 5. Pulse Skew 8 CDCVF310 www.ti.com SCAS771A – AUGUST 2004 – REVISED AUGUST 2004 DYNAMIC SUPPLY CURRENT vs CLOCK FREQUENCY 50 VDD = 2.3 V to 3.6 V CL(Yn) = No Load CPD = 32 pF CO = 10 x 2.6 pF CI = 3 x 2.5 pF All Outputs Switching TA = -40C to 85C Dynamic Supply Current - mA 45 40 35 30 25 VDD = 3.3 V, No C_Load, TA = 25C VDD = 3.6 V, No C_Load, TA = -40C 20 15 VDD = 2.7 V, No C_Load, TA = -40C 10 VDD = 2.5 V, No C_Load, TA = 25C 5 0 0 20 40 60 80 100 120 140 160 180 200 fCLK - Clock Frequency - MHz Figure 6. C_LOAD(max) PER OUTPUT PIN Yn vs CLOCK FREQUENCY 40 VDD = 2.7 V, TA = -40C for High-K Material 35 C_Load - pF 30 25 20 VDD = 3.6 V, TA = -40C for High-K Material 15 VDD = 2.3 V to 3.6 V CL(Yn) max = According to Graph CPD = 32 pF CO = 10 x 2.6 pF CI = 3 x 2.5 pF All Outputs Switching TA = -40C to 85C 10 5 0 0 20 40 60 80 100 120 140 160 180 200 fCLK - Clock Frequency - MHz Figure 7. 9 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CDCVF310PW ACTIVE TSSOP PW 24 60 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CDCVF310PWR ACTIVE TSSOP PW 24 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM CDCVF310PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated