NSC COP411C

COP410C/COP411C/COP310C/COP311C
Single-Chip CMOS Microcontrollers
General Description
Features
The COP410C, COP411C, COP310C, and COP311C fully
static, single-chip CMOS microcontrollers are members of
the COPSTM family, fabricated using double-poly, silicongate CMOS technology. These controller-oriented processors are complete microcomputers containing all system
timing, internal logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include single supply operation, a variety of
output configuration options, with an instruction set, internal
architecture, and I/O scheme designed to facilitate keyboard input, display output, and BCD data manipulation. The
COP411C is identical to the COP410C but with 16 I/O lines
instead of 20. They are an appropriate choice for use in
numerous human interface control environments. Standard
test procedures and reliable high-density fabrication techniques provide the medium to large volume customers with
a customized controller-oriented processor at a low endproduct cost.
The COP310C/COP311C is the extended temperature
range version of the COP410C/COP411C.
The COP404C should be used for exact emulation.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Lowest power dissipation (40 mW typical)
Low cost
Power-saving HALT Mode with Continue function
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
20 I/O lines (COP410C)
Two-level subroutine stack
DC to 4 ms instruction time
Single supply operation (2.4V to 5.5V)
General purpose and TRI-STATEÉ outputs
Internal binary counter register with MICROWIRETM
compatible serial I/O
LSTTL/CMOS compatible in and out
Software/hardware compatible with other members of
the COP400 family
Extended temperature (b40§ C to a 85§ C) devices
available
The military temperature range devices (b55§ C to
a 125§ C) are specified on COP210C/211C data sheet.
Block Diagram
TL/DD/5015 – 1
FIGURE 1. COP410C
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/DD/5015
RRD-B30M105/Printed in U. S. A.
COP410C/COP411C/COP310C/COP311C Single-Chip CMOS Microcontrollers
April 1992
COP410C/COP411C
Absolute Maximum Ratings
Operating Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
6V
b 0.3V to VCC a 0.3V
Voltage at Any Pin
Total Allowable Source Current
Total Allowable Sink Current
Storage Temperature Range
0§ C to a 70§ C
b 65§ C to a 150§ C
Lead Temperature (Soldering, 10 sec.)
300§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
25 mA
25 mA
DC Electrical Characteristics 0§ C s TA s 70§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
Min
Max
2.4
5.5
V
0.1 VCC
V
Power Supply Ripple (Notes 5, 6)
Units
Supply Current (Note 1)
VCC e 2.4V, tc e 125 ms
VCC e 5.0V, tc e 16 ms
VCC e 5.0V, tc e 4 ms
(tc is instruction cycle time)
80
500
2000
mA
mA
mA
HALT Mode Current (Note 2)
VCC e 5.0V, FIN e 0 kHz
VCC e 2.4V, FIN e 0 kHz
30
10
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
a1
mA
7
pF
0.4
V
V
0.2
V
V
b 330
b 80
mA
mA
mA
mA
mA
mA
Input Voltage Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 VCC
0.7 VCC
Hi-Z Input Leakage
b1
Input Capacitance (Note 6)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Standard Outputs
VCC e 5.0V g 10%
IOH e b25 mA
IOL e 400 mA
IOH e b10 mA
IOL e 10 mA
Output Current Levels (Note 4)
(Except CKO)
Sink
Source (Standard
Option)
Source (Low
Current Option)
CKO Current Levels
(As Clock Out)
Sink
Source
2.7
d4
d8
d 16
d4
d8
d 16
VCC
VCC
VCC
VCC
VCC
VCC
e
e
e
e
e
e
4.5V, VOUT
2.4V, VOUT
4.5V, VOUT
2.4V, VOUT
4.5V, VOUT
2.4V, VOUT
VCCb0.2
e
e
e
e
e
e
VCC
VCC
0V
0V
0V
0V
VCC e 4.5V, CKI e VCC, VOUT e VCC
VCC e 4.5V, CKI e 0V, VOUT e 0V
Allowable Sink/Source
Current Per Pin (Note 4)
1.2
0.2
b 0.5
b 0.1
b 30
b6
0.3
0.6
1.2
b 0.3
b 0.6
b 1.2
mA
mA
mA
mA
mA
mA
5
2
mA
COP410C/COP411C
DC Electrical Characteristics
(Continued)
Parameter
Conditions
Min
Allowable Loading on CKO
(as HALT I/O pin)
Current Needed to
Override HALT3
To Continue
To Halt
VCC e 4.5V, VIN e 0.2 VCC
VCC e 4.5V, VIN e 0.7 VCC
TRI-STATE or Open Drain
Leakage Current
b2
Max
Units
100
pF
0.6
1.6
mA
mA
a2
mA
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k
resistors. See current drain equation on page 13.
Note 2: The Halt mode will stop CKI from oscillating in the RC and crystal configurations.
Note 3: When forcing HALT, current is only needed for a short time (approximately 200 ns) to flip the HALT flip-flop.
Note 4: SO output sink current must be limited to keep VOL less than 0.2 VCC when part is running in order to prevent entering test mode.
Note 5: Voltage change must be less than 0.5V in a 1 ms period.
Note 6: This parameter is only sampled and not 100% tested.
Note 7: Variation due to the device included.
COP410C/COP411C
AC Electrical Characteristics 0§ C s TA s 70§ C unless otherwise specified
Parameter
Min
Max
Units
Instruction Cycle Time (tc)
VCC t 4.5V
4.5V l VCC t 2.4V
4
16
DC
DC
ms
ms
Operating CKI d 4 mode
d 8 mode
Frequency
d 16 mode
d 4 mode
d 8 mode
d 16 mode
(
(
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
R e 30k g 5%, VCC e 5V
C e 82 pF g 5% ( d 4 Mode)
8
16
ms
Duty Cycle6
fI e 4 MHz
40
60
%
Rise Time6
fI e 4 MHz External Clock
60
ns
Fall Time6
fI e 4 MHz External Clock
40
ns
Instruction Cycle Time
RC Oscillator7
Inputs (See Figure 3 )
tSETUP
tHOLD
Output Propagation
Delay
tPD1, tPD0
tPD1, tPD0
Conditions
VCC t 4.5V
4.5V l VCC t 2.4V
G Inputs
SI Input
VCC t 4.5V
All Others
VCC t 4.5V
VCC t 2.4V
(
VOUT e 1.5V, CL e 100 pF, RL e 5k
VCC s 4.5V
VCC s 2.4V
3
tc/4 a 0.7
0.3
1.7
0.25
1.0
ms
ms
ms
ms
ms
1.0
4.0
ms
ms
COP310C/COP311C
Absolute Maximum Ratings
Operating Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
6V
b 0.3V to VCC a 0.3V
Voltage at Any Pin
Total Allowable Source Current
Total Allowable Sink Current
Storage Temperature Range
b 40§ C to a 85§ C
b 65§ C to a 150§ C
Lead Temperature (Soldering, 10 sec.)
300§ C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
25 mA
25 mA
DC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified
Parameter
Conditions
Operating Voltage
Min
Max
3.0
5.5V
V
0.1 VCC
V
Power Supply Ripple (Notes 5, 6)
Units
Supply Current (Note 1)
VCC e 3.0V, tc e 125 ms
VCC e 5.0V, tc e 16 ms
VCC e 5.0V, tc e 4 ms
(tc is instruction cycle time)
100
600
2500
mA
mA
mA
HALT Mode Current (Note 2)
VCC e 5.0V, FIN e 0 kHz
VCC e 3.0V, FIN e 0 kHz
50
20
mA
mA
0.1 VCC
V
V
0.2 VCC
V
V
a2
mA
7
pF
0.4
V
V
0.2
V
V
b 440
b 200
mA
mA
mA
mA
mA
mA
Input Voltage Levels
RESET, CKI
Logic High
Logic Low
All Other Inputs
Logic High
Logic Low
0.9 VCC
0.7 VCC
Hi-Z Input Leakage
b2
Input Capacitance (Note 6)
Output Voltage Levels
LSTTL Operation
Logic High
Logic Low
CMOS Operation
Logic High
Logic Low
Standard Outputs
VCC e 5.0V g 10%
IOH e b25 mA
IOL e 400 mA
IOH e b10 mA
IOL e 10 mA
Output Current Levels (Note 4)
(Except CKO)
Sink
Source (Standard
Option)
Source (Low
Current Option)
CKO Current Levels
(As Clock Out)
Sink
Source
2.7
d4
d8
d 16
d4
d8
d 16
VCC
VCC
VCC
VCC
VCC
VCC
e
e
e
e
e
e
4.5V, VOUT
3.0V, VOUT
4.5V, VOUT
3.0V, VOUT
4.5V, VOUT
3.0V, VOUT
VCCb0.2
e
e
e
e
e
e
VCC
VCC
0V
0V
0V
0V
VCC e 4.5V, CKI e VCC, VOUT e VCC
VCC e 4.5V, CKI e 0V, VOUT e 0V
Allowable Sink/Source
Current Per Pin (Note 4)
1.2
0.2
b 0.5
b 0.1
b 30
b8
0.3
0.6
1.2
b 0.3
b 0.6
b 1.2
mA
mA
mA
mA
mA
mA
5
4
mA
COP310C/COP311C
DC Electrical Characteristics
(Continued)
Parameter
Conditions
Min
Allowable Loading on CKO
(as HALT I/O pin)
Current Needed to
Override HALT3
To Continue
To Halt
VCC e 4.5V, VIN e 0.2 VCC
VCC e 4.5V, VIN e 0.7 VCC
TRI-STATE or Open Drain
Leakage Current
b4
Max
Units
100
pF
0.8
2.0
mA
mA
a4
mA
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k
resistors. See current drain equation on page 13.
Note 2: The Halt mode will stop CKI from oscillating in the RC and crystal configurations.
Note 3: When forcing HALT, current is only needed for a short time (approximately 200 ns) to flip the HALT flip-flop.
Note 4: SO output sink current must be limited to keep VOL less than 0.2 VCC when part is running in order to prevent entering test mode.
Note 5: Voltage change must be less than 0.5V in a 1 ms period.
Note 6: This parameter is only sampled and not 100% tested.
Note 7: Variation due to the device included.
COP310C/COP311C
AC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified
Parameter
Min
Max
Units
Instruction Cycle Time (tc)
VCC t 4.5V
4.5V l VCC t 3.0V
4
16
DC
DC
ms
ms
Operating CKI d 4 mode
d 8 mode
Frequency
d 16 mode
d 4 mode
d 8 mode
d 16 mode
(
(
DC
DC
DC
DC
DC
DC
1.0
2.0
4.0
250
500
1.0
MHz
MHz
MHz
kHz
kHz
MHz
R e 30k g 5%, VCC e 5V
C e 82 pF g 5% ( d 4 Mode)
8
16
ms
Duty Cycle6
fI e 4 MHz
40
60
%
Rise Time6
fI e 4 MHz External Clock
60
ns
Fall Time6
fI e 4 MHz External Clock
40
ns
Instruction Cycle Time
RC Oscillator7
Inputs (See Figure 3 )
tSETUP
tHOLD
Output Propagation
Delay
tPD1, tPD0
tPD1, tPD0
Conditions
VCC t 4.5V
4.5V l VCC t 3.0V
G Inputs
SI Input
VCC t 4.5V
All Others
VCC t 4.5V
VCC t 3.0V
(
VOUT e 1.5V, CL e 100 pF, RL e 5k
VCC s 4.5V
VCC s 3.0V
5
tc/4 a 0.7
0.3
1.7
0.25
1.0
ms
ms
ms
ms
ms
1.0
4.0
ms
ms
Connection Diagrams
S.O. Wide and DIP
S.O. Wide and DIP
TL/DD/5015–2
Top View
TL/DD/5015 – 3
Order Number COP311C-XXX/D or COP411C-XXX/D
See NS Hermetic Package Number D20A
(Prototype Package Only)
Top View
Order Number COP310C-XXX/D or COP410C-XXX/D
See NS Hermetic Package Number D24C
(Prototype Package Only)
Order Number COP311C-XXX/N or COP411C-XXX/N
See NS Molded Package Number N20A
Order Number COP310C-XXX/N or COP410C-XXX/N
See NS Molded Package Number N24A
Order Number COP311C-XXX/WM or
COP411C-XXX/WM
See NS Surface Mount Package Number M20B
Order Number COP310C-XXX/WM or
COP410C-XXX/WM
See NS Surface Mount Package Number M24B
FIGURE 2
Pin Descriptions
Pin
L7 – L0
G3 – G0
D 3 – D0
SI
SO
Description
8-bit bidirectional I/O port with TRI-STATE
4-bit bidirectional I/O port
(G2 – G0 for 20-pin package)
4-bit general purpose output port
(D1 – D0 for 20-pin package)
Serial input (or counter input)
Serial output (or general purpose output)
Pin
SK
CKI
CKO
RESET
VCC
GND
Description
Logic-controlled clock
(or general purpose output)
System oscillator input
Crystal oscillator output, or HALT mode
I/O port (24-pin package only)
System reset input
System power supply
System Ground
Timing Diagram
TL/DD/5015 – 4
FIGURE 3. Input/Output (Divide-by-8 Mode)
6
Functional Description
To ease reading of this description, only COP410C and/or
COP411C are referenced; however, all such references apply equally to COP310C and/or COP311C, respectively.
A block diagram of the COP410C is given in Figure 1. Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic ‘‘1’’; when a bit is reset, it
is a logic ‘‘0’’.
INTERNAL LOGIC
The internal logic of the COP410C/411C is designed to ensure fully static operation of the device.
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load four bits of the 8-bit Q latch
data and to perform data exchanges with the SIO register.
The 4-bit adder performs the arithmetic and logic functions
of the COP410C/411C, storing its results in A. It also outputs the carry information to a 1-bit carry register, most often employed to indicate arithmetic overflow. The C register,
in conjunction with the XAS instruction and the EN register,
also serves to control the SK output. C can be outputted
directly to SK or can enable SK to be a sync clock each
instruction cycle time. (See XAS instruction and EN register
description below.)
The G register contents are outputs to four general purpose
bidirectional I/O ports.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded from RAM and A, as well as 8-bit data from
ROM. Its contents are output to the L I/O ports when the L
drivers are enabled under program control. (See LEI instruction.)
The eight L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and RAM.
PROGRAM MEMORY
Program memory consists of a 512-byte ROM. As can be
seen by an examination of the COP410C/411C instruction
set, these words may be program instructions, program
data, or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, and LQID instructions, ROM must often be thought of as being organized into 8 pages of 64 words (bytes) each.
ROM ADDRESSING
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by two 9-bit subroutine save registers, SA and SB.
ROM instruction words are fetched, decoded, and executed
by the instruction decode, control and skip logic circuitry.
DATA MEMORY
Data Memory consists of a 128-bit RAM, organized as four
data registers of 8 c 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper two bits (Br) selects one of four data registers and lower three bits of the 4bit Bd select one of eight 4-bit digits in the selected data
register. While the 4-bit contents of the selected RAM digit
(M) are usually loaded into or from, or exchanged with, the A
register (accumulator), they may also be loaded into the Q
latches or loaded from the L ports. RAM addressing may
also be performed directly by the XAD 3, 15 instruction. The
Bd register also serves as a source register for 4-bit data
sent directly to the D outputs.
The most significant bit of Bd is not used to select a RAM
digit. Hence, each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4. The skip
condition for XIS and XDS instructions will be true if Bd
changes between 0 to 15, but not between 7 and 8 (see
Table III).
* Can be directly addressed by
LBI instruction (See Table 3)
TL/DD/5015 – 5
FIGURE 4. RAM Digit Address to Physical
RAM Digit Mapping
7
Functional Description (Continued)
The SIO register functions as a 4-bit serial-in/serial-out shift
register or as a binary counter, depending upon the contents of the EN register. (See EN register description below.) Its contents can be exchanged with A, allowing
it to input or output a continuous serial data stream. With
SIO functioning as a serial-in/serial-out shift register and SK
as a sync clock, the COP410C/411C is MICROWIRE compatible.
The D register provides four general purpose outputs and is
used as the destination register for the 4-bit contents of Bd.
The XAS instruction copies C into the SKL latch. In the
counter mode, SK is the output of SKL; in the shift register
mode, SK is a sync clock, inhibited when SKL is a logic ‘‘0’’.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3–EN0).
1. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or as a
4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With EN0 reset, SIO is a serial
shift register, shifting left each instruction cycle time. The
data present at SI is shifted into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each instruction cycle time. (See 4, below.) The
SK output becomes a logic-controlled clock.
2. EN 1 is not used, it has no effect on the COP410C/411C.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O ports. Resetting EN2 disables the L
drivers, placing the L I/O ports in a high impedance input
state.
4. EN3, in conjunction with EN0, affects the SO output. With
EN0 set (binary counter option selected), SO will output
the value loaded into EN3. With EN0 reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected, disables SO as the shift
register output; data continues to be shifted through SIO
and can be exchanged with A via an XAS instruction but
SO remains reset to ‘‘0’’.
INITIALIZATION
The internal reset logic will initialize the device upon powerup if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz, otherwise the external RC network shown in Figure 5 must be
connected to the RESET pin. The RESET pin is configured
as a Schmitt trigger input. If not used, it should be connected to VCC. Initialization will occur whenever a logic ‘‘0’’ is
applied to the RESET input, providing it stays low for at
least three instruction cycle times.
When VCC power is applied, the internal reset logic will keep
the chip in initialization mode for up to 2500 instruction cycles. If the CKI clock is running at a low frequency, this
could take a long time, therefore, the internal logic should
be disabled by a mask option with initialization controlled
solely by RESET pin.
Note: If CKI clock is less than 32 kHz, the internal reset logic (Option 25 e 1)
must be disabled and the external RC network must be present.
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA (clear A register).
TL/DD/5015 – 6
RC l 5 c Power Supply Rise Time
and RC l 100 c CKI Period
FIGURE 5. Power-Up Clear Circuit
COP411C
If the COP410C is bonded as a 20-pin package, it becomes
the COP411C, illustrated in Figure 2, COP410C/411C Connection Diagrams. Note that the COP411C does not contain
D2, D3, G3, or CKO. Use of this option, of course, precludes
use of D2, D3, G3, and CKO options. All other options are
available for the COP411C.
TABLE I. Enable Register Modes Ð Bits EN0 and EN3
EN0
EN3
0
0
Shift Register
SIO
0
1
Shift Register
1
1
0
1
Binary Counter
Binary Counter
SI
SO
Input to Shift
Register
Input to Shift
Register
Input to Counter
Input to Counter
0
8
Serial
out
0
1
SK
If SKL e 1, SK
If SKL e 0, SK
If SKL e 1, SK
If SKL e 0, SK
SK e SKL
SK e SKL
e
e
e
e
clock
0
clock
0
Functional Description (Continued)
flip-flop which is an indicator of the HALT status. An external signal can override this pin to start and stop the chip. By
forcing a high level to CKO, the chip will stop as soon as
CKI is high and the CKO output will go high to keep the chip
stopped. By forcing a low level to CKO, the chip will continue and CKO output will go low.
All features associated with the CKO I/O pin are available
with the 24-pin package only.
HALT MODE
The COP410C/411C is a fully static circuit; therefore, the
user may stop the system oscillator at any time to halt the
chip. The chip also may be halted by the HALT instruction or
by forcing CKO high when it is used as a HALT I/O port.
Once in the HALT mode, the internal circuitry does not receive any clock signal, and is therefore frozen in the exact
state it was in when halted. All information is retained until
continuing. The HALT mode is the minimum power dissipation state.
The HALT mode has slight differences depending upon the
type of oscillator used.
a. 1-pin oscillatorÐRC or external
The HALT mode may be entered into by either program
control (HALT instruction) or by forcing CKO to a logic
‘‘1’’ state.
The circuit may be awakened by one of two different
methods:
1) Continue function. By forcing CKO to a logic ‘‘0’’, the
system clock is re-enabled and the circuit continues to
operate from the point where it was stopped.
2) Restart. Forcing the RESET pin to a logic ‘‘0’’ will restart the chip regardless of HALT or CKO (see initialization).
b. 2-pin oscillatorÐcrystal
The HALT mode may be entered into by program control
(HALT instruction) which forces CKO to a logic ‘‘1’’ state.
The circuit can be awakened only by the RESET function.
OSCILLATOR OPTIONS
There are three options available that define the use of CKI
and CKO.
a. Crystal-Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time
equals the crystal frequency divided by 16 (optionally by 8
or 4).
b. External Oscillator. CKI is configured as LSTTL-compatible input accepting an external clock signal. The external
frequency is divided by 16 (optionally by 8 or 4) to give
the instruction cycle time. CKO is the HALT I/O port.
c. RC-Controlled Oscillator. CKI is configured as a single pin
RC-controlled Schmitt trigger oscillator. The instruction
cycle equals the oscillation frequency divided by 4. CKO
is the HALT I/O port.
The RC oscillator is not recommended in systems that require accurate timing or low current. The RC oscillator
draws more current than an external oscillator (typically an
additional 100 mA at 5V). However, when the part halts, it
stops with CKI high and the halt current is at the minimum.
TL/DD/5015 – 7
Halt I/O Port
CKO Pin Options
In a crystal-controlled oscillator system, CKO is used as an
output to the crystal network. CKO will be forced high during
the execution of a HALT instruction, thus inhibiting the crystal network. If a 1-pin oscillator system is chosen (RC or
external), CKO will be selected as HALT and is an I/O
TL/DD/5015 – 8
FIGURE 6. COP410C Oscillator
RC-Controlled
Oscillator
Crystal or Resonator
Crystal
Value
R1
32 kHz
455 kHz
2.096 MHz
4.0 MHz
220k
5k
2k
1k
Component Value
R2
C1 pF
C2 pF
20M
10M
1M
1M
30
80
30
30
5-36
40
6-36
6-36
9
R
C
Cycle
Time
15k
82 pF
4-9 ms
30k
82 pF
8-16 ms
47k
100 pF
16-32 ms
Note: 15k s R s 150k,
50 pf s C s 150 pF
VCC
t 4.5V
t 4.5V
2.4 to 4.5
COP410C/COP411C Instruction Set
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP410C/411C instruction set.
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
TABLE II. COP410C/411C Instruction Set Table Symbols
Symbol
Symbol
Definition
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
D
EN
G
L
M
d
r
PC
Q
SA
SB
SIO
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by B
Register
9-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register B
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0-15 binary (RAM Digit Select)
2-bit Operand Field, 0-3 binary (RAM Register
Select)
a
9-bit Operand Field, 0-511 binary (ROM Address)
y
4-bit Operand Field, 0-15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
a
b
x
Ý
e
A
Z
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one’s complement of A
Exclusive-OR
Range of values
TABLE III. COP410C/411C Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
À 0011 À 0000 À
A a C a RAM(B)
Carry x C
ADD
31
À 0011 À 0001 À
A a RAM(B)
5b
À 0101 À
Aay
CLRA
00
À 0000 À 0000 À
0
COMP
40
À 0100 À 0000 À
A
NOP
44
À 0100 À 0100 À
None
RC
32
À 0011 À 0010 À
‘‘0’’
SC
22
À 0010 À 0010 À
XOR
02
À 0000 À 0010 À
AISC
y
y
À
xA
Carry
Add with Carry, Skip on
Carry
None
Add RAM to A
Carry
Add immediate, Skip on
Carry (y i 0)
xA
None
Clear A
xA
None
One’s complement of A to A
None
No Operation
xC
None
Reset C
‘‘1’’
xC
None
Set C
A
RAM(B)
None
Exclusive-OR RAM with A
Z
xA
xA
10
xA
Instruction Set (Continued)
TABLE III. COP410C/411C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
FF
À 1111 À 1111 À
ROM (PC8, A,M)
PC7:0
x
None
Jump Indirect (Note 2)
JMP
a
6b
–
À 0110 À 000 À a8 À
a7:0
À
À
a
x PC
None
Jump
JP
a
–
a6:0
À1À
À
(pages 2,3 only)
or
a5:0
À 11 À
À
(all other pages)
a
x PC6:0
None
Jump within Page
(Note 1)
a
x PC5:0
None
Jump to Subroutine Page
(Note 2)
None
Jump to Subroutine
None
Return from Subroutine
Always Skip on Return
Return from Subroutine
then Skip
None
Halt processor
–
JSRP
a
–
À 10 À
a5:0
JSR
a
6b
–
À 0110 À 100 À a8 À
a7:0
À
À
RET
48
À 0100 À 1000 À
RETSK
49
À 0100 À 10011 À
HALT
33
38
À 0011 À 0011 À
À 0011 À 1000 À
À
x SA x SB
010 x PC8:6
a x PC5:0
PC a 1 x SA x SB
a x PC
SB x SA x PC
SB x SA x PC
PC a 1
MEMORY REFERENCE INSTRUCTIONS
CAMQ
33
3C
À 0011 À 0011 À
À 0011 À 1100 À
A x Q7:4
RAM(B) x Q3:0
None
Copy A, RAM to Q
CQMA
33
2C
À 0011 À 0011 À
À 0010 À 1100 À
Q7:4 x RAM(B)
Q3:0 x A
None
Copy Q to RAM, A
b5
À 00 À r À 0101 À
RAM(B) x A
Br Z r x Br
None
Load RAM into A
Exclusive-OR Br with r
BF
À 1011 À 1111 À
ROM(PC8,A,M)
SA x SB
None
Load Q Indirect
0
0
0
0
None
Reset RAM Bit
None
Set RAM Bit
None
Store Memory Immediate
and Increment Bd
None
Exchange RAM with A,
Exclusive-OR Br with r
None
Exchange A with RAM
(3,15)
LD
r
LQID
RMB
0
1
2
3
4C
45
42
43
À 0100 À 1100 À
À 0100 À 0101 À
À 0100 À 0010 À
À 0100 À 0011 À
SMB
0
1
2
3
4D
47
46
4B
À 0100 À 1101 À
À 0100 À 0111 À
À 0100 À 0110 À
À 0100 À 1011 À
STII
y
7b
À 0111 À
X
r
b6
À 00 À r À 0110 À
XAD
3,15
23
BF
À 0010 À 0011 À
À 1011 À 1111 À
y
À
xQ
x RAM(B)0
x RAM(B)1
x RAM(B)2
x RAM(B)3
1 x RAM(B)0
1 x RAM(B)1
1 x RAM(B)2
1 x RAM(B)3
y x RAM(B)
Bd a 1 x Bd
RAM(B) Ý A
Br Z r x Br
RAM(3,15) Ý A
11
Instruction Set (Continued)
TABLE III. COP410C/411C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
MEMORY REFERENCE INSTRUCTIONS (Continued)
XDS
r
b7
À 00 À r À 0111 À
RAM(B) Ý A
Bd – 1 x Bd
Br Z r x Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd
Exclusive-OR Br with r
XIS
r
b4
À 00 À r À 0100 À
RAM(B) Ý A
Bd a 1 x Bd
Br Z r x Br
Bd increments past 15
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
x Bd
None
Copy A to Bd
REGISTER REFERENCE INSTRUCTIONS
CAB
50
À 0101 À 0000 À
A
CBA
4E
À 0100 À 1110 À
Bd
xA
None
Copy Bd to A
xB
Skip until not a LBI
Load B Immediate with
r,d
None
Load EN Immediate
LBI
r,d
–
À 00 À r À (d - 1) À
(d e 0,9:15)
r,d
LEI
y
33
6b
À 0011 À 0011 À
À 0010 À y À
y
SKC
20
À 0010 À 0000 À
C e ‘‘1’’
Skip if C is True
SKE
21
À 0010 À 0001 À
A e RAM(B)
Skip if A Equals RAM
SKGZ
33
21
À 0011 À 0011 À
À 0010 À 0001 À
G3:0 e 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
À 0011 À 0011 À
À 0000 À 0001 À
À 0001 À 0001 À
À 0000 À 0011 À
À 0010 À 0011 À
0
1
2
3
01
11
03
13
À 0000 À 0001 À
À 0001 À 0001 À
À 0000 À 0011 À
À 0001 À 0011 À
x EN
TEST INSTRUCTIONS
SKGBZ
SKMBZ
1st byte
*
2nd byte
Skip if G Bit is Zero
G0
G1
G2
G3
e
e
e
e
0
0
0
0
RAM(B)0
RAM(B)1
RAM(B)2
RAM(B)3
e
e
e
e
0
0
0
0
Skip if RAM Bit is Zero
INPUT/OUTPUT INSTRUCTIONS
xA
ING
33
2A
À 0011 À 0011 À
À 0010 À 1010 À
G
INL
33
2E
À 0011 À 0011 À
À 0010 À 1110 À
L7:4
L3:0
OBD
33
3E
À 0011 À 0011 À
À 0011 À 1110 À
Bd
OMG
33
3A
À 0011 À 0011 À
À 0011 À 1010 À
RAM(B)
XAS
4F
À 0100 À 1111 À
A
x RAM(B)
xA
xD
xG
Ý SIO, C x SKL
None
Input G Ports to A
None
Input L Ports to RAM, A
None
Output Bd to D Outputs
None
Output RAM to G Ports
None
Exchange A with SIO
Note 1: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 2: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
12
Description of Selected
Instructions
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP410C/411C programs.
POWER DISSIPATION
The lowest power drain is when the clock is stopped. As the
frequency increases so does current. Current is also lower
at lower operating voltages. Therefore, to minimize power
consumption, the user should run at the lowest speed and
voltage that his application will allow. The user should take
care that all pins swing to full supply levels to ensure that
outputs are not loaded down and that inputs are not at
some intermediate level which may draw current. Any input
with a slow rise or fall time will draw additional current. A
crystal- or resonator-generated clock will draw additional
current. An RC oscillator will draw even more current since
the input is a slow rising signal.
If using an external squarewave oscillator, the following
equation can be used to calculate the COP410C current
drain.
Ic e Iq a (V c 20 c Fi) a (V c 1280 c Fl/Dv)
XAS INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register). If SIO is selected as a shift register, an XAS instruction must be performed once every four instruction cycle times to effect a
continuous data stream.
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower eight bits of the
ROM address register PC with the contents of ROM addressed by the 9-bit word, PC8, A, M. PC8 is not affected by
this instruction.
where Ic e chip current drain in microamps
Iq e quiescent leakage current (from curve)
Fl e CKI frequency in megahertz
V e chip VCC in volts
Dv e divide by option selected
Note: JID uses two instruction cycles if executed, one if skipped.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 9-bit word PC8, A, M.
LQID can be used for table look-up or code conversion such
as BCD to 7-segment. The LQID instruction ‘‘pushes’’ the
stack (PC a 1 x SA x SB) and replaces the least
significant eight bits of the PC as follows: A x PC7:4,
RAM(B) x PC3:0, leaving PC8 unchanged. The ROM data
pointed to by the new address is fetched and loaded into
the Q latches. Next, the stack is ‘‘popped’’ (SB x SA x
PC), restoring the saved value of the PC to continue sequential program execution. Since LQID pushes SA x
SB, the previous contents of SB are lost.
For example, at 5V VCC and 400 kHz (divide by 4),
Ic e 10 a (5 c 20 c 0.4) a (5 c 1280 c 0.4/4)
Ic e 10 a 40 a 640 e 690 mA
I/O OPTIONS
COP410C/411C outputs have the following optional configurations, illustrated in Figure 7 :
a. Standard. A CMOS push-pull buffer with an N-channel
device to ground in conjunction with a P-channel device
to VCC, compatible with CMOS and LSTTL.
b. Low Current. This is the same configuration as (a) above
except that the sourcing current is much less.
c. Open Drain. An N-channel device to ground only, allowing external pull-up as required by the user’s application.
d. Standard TRI-STATE L Output. A CMOS output buffer
similar to (a) which may be disabled by program control.
e. Low-Current TRI-STATE L Output. This is the same as
(d) above except that the sourcing current is much less.
f. Open-Drain TRI-STATE L Output. This has the N-channel device to ground only.
The SI and RESET inputs are Hi-Z inputs (Figure 7g ).
Note: LQID uses two instruction cycles if executed, one if skipped.
INSTRUCTION SET NOTES
a. The first word of a COP410C/411C program (ROM address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths take the
same number of cycle times whether instructions are
skipped or executed (except JID and LQID).
c. The ROM is organized into eight pages of 64 words
each. The program counter is a 9-bit binary counter, and
will count through page boundaries. If a JP, JSRP, JID, or
LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: A JP located in the last word of a page will
jump to a location in the next page. Also, a LQID or JID
located in the last word in page 3 or 7 will access data in
the next group of four pages.
When using either the G or L I/O ports as inputs, a pull-up
device is necessary. This can be an external device or the
following alternative is available: Select the low-current output option. Now, by setting the output registers to a logic
‘‘1’’ level, the P-channel devices will act as the pull-up load.
Note that when using the L ports in this fashion, the Q registers must be set to a logic ‘‘1’’ level and the L drivers must
be enabled by an LEI instruction.
13
Functional Description (Continued)
a. Standard Push-Pull Output
d. Standard TRI-STATE
‘‘L’’ Output
b. Low Current Push-Pull Output
e. Low Current TRI-STATE
‘‘L’’ Output
g. Hi-Z Input
c. Open Drain Output
f. Open Drain TRI-STATE
‘‘L’’ Output
TL/DD/5015 – 9
FIGURE 7. I/O Configurations
Typical Performance Characteristics
Minimum Sink Current
Standard
Minimum Source Current
Low Current Option
Minimum Source Current
COP410C/COP411C
Low Current Option
Maximum Source Current
COP310C/COP311C
Low Current Option
Maximum Source Current
Maximum Quiescent Current
TL/DD/5015 – 10
FIGURE 8
14
Option 6:
All output drivers uses one or more of three common devices numbered 1 to 3. Minimum and maximum current (IOUT
and VOUT) curves are given in Figure 8 for each of these
devices to allow the designer to effectively use these I/O
configurations.
Option 9:
Option 10:
Option 11:
Option 12:
Option 13:
Option 14:
Option List
The COP410C/411C mask-programmable options are assigned numbers which correspond with the COP410C pins.
The following is a list of COP410C options. When specifying
a COP411 chip, options 20, 21, and 22 must be set to 0. The
options are programmed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various I/O components using little or no external
circuitry.
Option 1: 0 e Ground Pin. No options available.
Option 2:
Option 3:
Option 4:
Option 5:
L6 Driver. (Same as Option 5.)
L5 Driver. (Same as Option 5.)
L4 Driver. (Same as Option 5.)
Option 7:
Option 8:
Option 15:
CKO I/O Port. (Determined by Option 3.)
e 0: No option.
(a. is crystal oscillator output for two pin
oscillator.
b. is HALT I/O for one pin oscillator.)
CKI Input.
e 0: Crystal-controlled oscillator input ( d 4).
e 1: Single-pin RC-controlled oscillator ( d 4).
e 2: External oscillator input ( d 4).
e 3: Crystal oscillator input ( d 8).
e 4: External oscillator input ( d 8).
e 5: Crystal oscillator input ( d 16).
e 6: External oscillator input ( d 16).
RESET Input e 1: Hi-Z input. No option available.
L7 Driver
Option 16:
Option 17:
Option 18:
Option 19:
Option 20:
Option 21:
Option 22:
Option 23:
Option 24:
Option 25:
Option 26:
Option 27:
e 0: Standard TRI-STATE push-pull output.
e 1: Low-current TRI-STATE push-pull output.
e 2: Open-drain TRI-STATE output.
VCC Pin e 0 no option.
L3 Driver. (Same as Option 5.)
L2 Driver. (Same as Option 5.)
L1 Driver. (Same as Option 5.)
L0 Driver. (Same as Option 5.)
SI Input.
No option available.
e 1: Hi-Z input.
SO Output.
e 0: Standard push-pull output.
e 1: Low-current push-pull output.
e 2: Open-drain output.
SK Driver. (Same as Option 15.)
G0 I/O Port. (Same as Option 15.)
G1 I/O Port. (Same as Option 15.)
G2 I/O Port. (Same as Option 15.)
G3 I/O Port. (Same as Option 15.)
D3 Output. (Same as Option 15.)
D2 Output. (Same as Option 15.)
D1 Output. (Same as Option 15.)
D0 Output. (Same as Option 15.)
Internal Initialization Logic.
e 0: Normal operation.
e 1: No internal initialization logic.
No option available.
COP Bonding
e 0: COP410C (24-pin device).
e 1: COP411C (20-pin device). See note.
e 2: COP410C and COP411C. See note.
Note: If opt. Ý27 e 1 or 2 then opt Ý20 must e 0.
Option Table
Please fill out a photocopy of the option table and send it along with your EPROM.
Option Table
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
1 Value e
2 Value e
3 Value e
4 Value e
5 Value e
6 Value e
7 Value e
8 Value e
9 Value e
10 Value e
11 Value e
12 Value e
13 Value e
14 Value e
0
0
1
0
1
is: Ground Pin
is: CKO Pin
is: CKI Input
is: RESET Input
is: L7 Driver
is: L6 Driver
is: L5 Driver
is: L4 Driver
is: VCC Pin
is: L3 Driver
is: L2 Driver
is: L1 Driver
is: L0 Driver
is: SI Input
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
Option
15 Value
16 Value
17 Value
18 Value
19 Value
20 Value
21 Value
22 Value
23 Value
24 Value
25 Value
e
e
e
e
e
e
e
e
e
e
e
Option 26 Value e
Option 27 Value e
15
0
is: SO Output
is: SK Driver
is: G0 I/O Port
is: G1 I/O Port
is: G2 I/O Port
is: G3 I/O Port
is: D3 Output
is: D2 Output
is: D1 Output
is: D0 Output
is: Internal
Initialization
Logic
is: N/A
is: COP Bonding
16
Physical Dimensions inches (millimeters)
Hermetic Dual-in-Line Package (D)
Order Number COP311C – XXX/D, COP411C – XXX/D
NS Package Number D20A
Hermetic Dual-in-Line Package (D)
Order Number COP310C – XXX/D, COP411C – XXX/D
NS Package Number D24C
17
Physical Dimensions inches (millimeters) (Continued)
SO Package (M)
Order Number COP311C – XXX/M, COP411C – XXX/M
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number COP311C – XXX/N or COP411C – XXX/N
NS Package Number N20A
18
Physical Dimensions inches (millimeters) (Continued)
24-Lead Molded Package (M)
Order Number COP310C – XXX/M or COP411C – XXX/M
NS Package Number M24B
20-Lead Molded Dual-In-Line Package (N)
Order Number COP311C – XXX/N, COP411C – XXX/N
NS Package Number N20A
19
COP410C/COP411C/COP310C/COP311C Single-Chip CMOS Microcontrollers
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number COP310C – XXX/N, COP410C – XXX/N
NS Package Number N24A
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