COP413C/COP413CH/COP313C/COP313CH Single-Chip CMOS Microcontrollers General Description Features The COP413C, COP413CH, COP313C, and COP313CH fully static, single-chip CMOS microcontrollers are members of the COPSTM family, fabricated using double-poly, silicongate CMOS technology. These controller-oriented processors are complete microcomputers containing all system timing, internal logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include single supply operation, with an instruction set, internal architecture, and I/O scheme designed to facilitate keyboard input, display output, and BCD data manipulation. The COP413CH is identical to the COP413C except for operating voltage and frequency. They are an appropriate choice for use in numerous human interface control environments. Standard test procedures and reliable high-density fabrication techniques provide a customized controller-oriented processor at a low end-product cost. The COP313C/COP313CH is the extended temperature range version of the COP413C/COP413CH. For emulation use the ROMless COP404C. Y Y Y Y Y Y Y Y Y Y Y Y Y Lowest power dissipation (40 mW typical) Low cost Power-saving HALT Mode Powerful instruction set 512 x 8 ROM, 32 x 4 RAM 15 I/O lines Two-level subroutine stack DC to 4 ms instruction time Single supply operation (3V to 5.5V) General purpose and TRI-STATEÉ outputs Internal binary counter register with MICROWIRETM compatible serial I/O Software/hardware compatible with other members of the COP400 family Extended temperature (b40§ C to a 85§ C) devices available Block Diagram TL/DD/8537 – 1 FIGURE 1. COP413C/413CH TRI-STATEÉ is a registered trademark of National Semiconductor Corp. COPSTM , MICROWIRETM and STARPLEXTM are trademarks of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/DD/8537 RRD-B30M105/Printed in U. S. A. COP413C/COP413CH/COP313C/COP313CH Single-Chip CMOS Microcontrollers November 1990 COP413C/COP413CH Absolute Maximum Ratings Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 6V b 0.3V to VCC a 0.3V Voltage at Any Pin Total Allowable Source Current Total Allowable Sink Current 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 25 mA 25 mA DC Electrical Characteristics 0§ C s TA s a 70§ C unless otherwise specified COP413C Parameter COP413CH Conditions Units Min Operating Voltage 3.0 Power Supply Ripple (Notes 4, 5) Max Min 5.5 4.5 Max 5.5 V 0.1 VCC 0.1 VCC V Supply Current (Note 1) VCC e 5.0V, tc e Min VCC e 3.0V, tc e Min (tc is inst. cycle) 500 300 2000 mA mA HALT Mode Current (Note 2) VCC e 5.0V, FI e 0 kHz VCC e 3.0V, FI e 0 kHz 30 10 30 mA mA Input Voltage Levels RESET, CKI Logic High Logic Low All Other Inputs Logic High Logic Low 0.9 VCC 0.9 VCC 0.1 VCC 0.7 VCC b1 Input Capacitance (Notes 5, 6) a1 b1 7 Output Voltage Levels (SO, SK, L Port) Logic High Logic Low IOH e b10 mA IOL e 10 mA Output Current Levels Sink (Note 3) Source (SO, SK, L Port) Source (G Port) VCC e Min, VOUT e VCC VCC e Min, VOUT e 0V VCC e Min, VOUT e 0V VCC b 0.2 0.2 1.2 b 0.1 b8 b 0.5 b 30 b 150 5 TRI-STATE Leakage Current b2 2 0.2 VCC V V a1 mA 7 pF 0.2 V V b 330 mA mA mA 5 mA a2 mA VCC b 0.2 0.2 Allowable Sink/Source Current Per Pin (Note 3) V V 0.7 VCC 0.2 VCC RESET, SI Input Leakage 0.1 VCC a2 b2 COP413C/COP413CH AC Electrical Characteristics 0§ C s TA s 70§ C unless otherwise specified COP413C Parameter Units Min Instruction Cycle Time DC 4 DC ms DC 2000 kHz 8 16 ms 32 16 32 ms 60 40 60 % 60 60 ns 40 40 ns R e 30k g 5%, VCC e 5V C e 82 pF g 5% Instruction Cycle Time RC Oscillator d 4 (Note 6) R e 56k g 5%, VCC e 5V C e 100 pF g 5% 16 Duty Cycle (Note 5) Fi e Max freq ext clk 40 Rise Time (Note 5) Fi e Max freq ext clk Fall Time (Note 5) Fi e Max freq ext clk Output Propagation Delay tPD1, tPD0 Max 500 Instruction Cycle Time RC Oscillator d 4 tc/4 a 2.8 1.2 6.8 1.0 tHOLD Min 16 d 8 Mode G Inputs SI Input L Inputs Max DC Operating CKI Frequency Inputs (See Figure 3 ) tSETUP COP413CH Conditions tc/4 a 0.7 0.3 1.7 0.25 ms ms ms ms VOUT e 1.5, CL e 100 pF RL e 5k 4.0 1.0 ms Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled to VCC with 5k resistors. Note 2: The Halt mode will stop CKI from oscillating. Note 3: SO output sink current must be limited to keep VOL less tha 0.2 VCC when part is running in order to prevent entering test mode. Note 4: Voltage change must be less than 0.5V in a 1 ms period. Note 5: This parameter is only sampled and not 100% tested. Note 6: Variation due to the device included. 3 COP313C/COP313CH Absolute Maximum Ratings Total Allowable Sink Current Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 6V b 0.3V to VCC a 0.3V Voltage at Any Pin Total Allowable Source Current 25 mA b 40§ C to a 85§ C b 65§ C to a 150§ C Storage Temperature Range Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 25 mA DC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified Parameter COP313C Conditions Min Operating Voltage 3.0 Power Supply Ripple (Notes 4, 5) COP313CH Max Min 5.5 4.5 Units Max 5.5 V 0.1 VCC 0.1 VCC V Supply Current (Note 1) VCC e 5.0V, tc e Min VCC e 3.0V, tc e Min (tc is inst. cycle) 600 360 2500 mA mA Halt Mode Current (Note 2) VCC e 5.0V, Fi e 0 kHz VCC e 3.0V, Fi e 0 kHz 50 20 50 mA mA Input Voltage Levels RESET, CKI Logic High Logic Low All Other Inputs Logic High Logic Low 0.9 VCC 0.9 VCC 0.1 VCC 0.7 VCC b2 Input Capacitance (Notes 5, 6) a2 b2 7 Output Voltage Levels (SO, SK, L Port) Logic High Logic Low IOH e b10 mA IOL e 10 mA Output Current Levels Sink (Note 3) Source (SO, SK, L Port) Source (G Port) VCC e Min, VOUT e VCC VCC e Min, VOUT e 0V VCC e Min, VOUT e 0V VCC b 0.2 0.2 1.2 b 0.1 b8 b 0.5 b 30 b 200 5 TRI-STATE Leakage Current (Note 3) b4 4 0.2 VCC V V a2 mA 7 pF 0.2 V V b 440 mA mA mA 5 mA a4 mA VCC b 0.2 0.2 Allowable Sink/Source Current Per Pin (Note 3) V V 0.7 VCC 0.2 VCC RESET, SI Input Leakage 0.1 VCC a4 b4 COP313C/COP313CH AC Electrical Characteristics b40§ C s TA s a 85§ C unless otherwise specified Parameter COP313C Conditions Min Instruction Cycle Time DC 4 DC ms 500 DC 2000 kHz 8 16 ms 32 16 32 ms 60 40 60 % 60 60 ns 40 40 ns Instruction Cycle Time RC Oscillator d 4 R e 30k g 5%, VCC e 5V C e 82 pF g 5% Instruction Cycle Time RC Oscillator d 4 (Note 6) R e 56k g 5%, VCC e 5V C e 100 pF g 5% 16 Duty Cycle (Note 5) Fi e Max Freq Ext Clk 40 Rise Time (Note 5) Fi e Max Freq Ext Clk Fall Time (Note 5) Fi e Max Freq Ext Clk tc/4 a 2.8 1.2 6.8 1.0 tHOLD Output Propagation Delay tPD1, tPD0 Units Max 16 d 8 Mode G Inputs SI Input L Inputs Min DC Operating CKI Frequency Inputs (See Figure 3 ) tSETUP COP313CH Max tc/4 a 0.7 0.3 1.7 0.25 ms ms ms ms VOUT e 1.5V, CL e 100 pF RL e 5k 4.0 1.0 ms Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to VCC with 5k resistors. See current drain equation on page 13. Note 2: The Halt mode will stop CKI from oscillating. Note 3: SO output sink current must be limited to keep VOL less than 0.2 VCC when part is running in order to prevent entering test mode. Note 4: Voltage change must be less than 0.5V in a 1 ms period. Note 5: This parameter is only sampled and not 100% tested. Note 6: Variation due to the device included. Connection Diagram Pin Descriptions DIP Pin L7 –L0 G3 –G0 SI SO SK CKI CKO RESET VCC GND TL/DD/8537 – 2 Top View FIGURE 2 Order Number COP313C-XXX/D, COP313CH-XXX/D, COP413C-XXX/D or COP413CH-XXX/D See NS Hermetic Package Number D20A Order Number COP313C-XXX/N, COP313CH-XXX/N, COP413C-XXX/N or COP413CH-XXX/N See NS Molded Package Number N20A Order Number COP313C-XXX/WM or COP413C-XXX/WM See NS Small Outline Package Number M20B 5 Description 8-bit bidirectional I/O port with TRI-STATE 4-bit bidirectional I/O port Serial input (or counter input) Serial output (or general purpose output) Logic-controlled clock (or general purpose output) System oscillator input Crystal oscillator output, or NC System reset input System power supply System Ground Timing Waveform TL/DD/8537 – 3 FIGURE 3. Input/Output Timing Diagrams (Divide-by-8 Mode) Development Support The personality board contains the necessary hardware and firmware needed to emulate the target microcontroller. The emulation cable which replaces the target controller attaches to this board. The software contains a cross assembler and a communications program for up loading and down loading code from the MOLE. The MOLE (Microcontroller On Line Emulator) is a low cost development system and real time emulator for COPS’ products. They also include TMP, 8050 and the new 16 bit HPC microcontroller family. The MOLE provides effective support for the development of both software and hardware in the user’s application. The purpose of the MOLE is to provide a tool to write and assemble code, emulate code for the target microcontroller and assist in debugging of the system. The MOLE can be connected to various hosts, IBM PC, STARPLEXTM , Kaypro, Apple and Intel systems, via RS-232 port. This link facilitates the up loading/down loading of code, supports host assembly and mass storage. The MOLE consists of three parts; brain, personality and optional host software. The brain board is the computing engine of the system. It is a self-contained computer with its own firmware which provides for all system operation, emulation control, communication, from programming and diagnostic operation. It has three serial ports which can be connected to a terminal, host system, printer, modem or to other MOLE’s in a multiMOLE environment. MOLE Ordering Information P/N Description MOLE-BRAIN MOLE Computer Board MOLE-COPS-PB1 COPS Personality Board MOLE-XXX-YYY Optional Software Where XXX e COPS YYY e Host System, IBM, Apple, KAY (Kaypro), CP/M 6 Functional Description To ease reading of this description, only COP413C is referenced; however, all such references apply equally to COP413CH, COP313C, and COP313CH. A block diagram of the COP413C is given in Figure 1. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic ‘‘1’’; when a bit is reset, it is a logic ‘‘0’’. INTERNAL LOGIC The internal logic of the COP413C is designed to ensure fully static operation of the device. The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory access operations. It can also be used to load the Bd portion of the B register, to load four bits of the 8-bit Q latch data and to perform data exchanges with the SIO register. The 4-bit adder performs the arithmetic and logic functions of the COP413C, storing its results in A. It also outputs the carry information to a 1-bit carry register, most often employed to indicate arithmetic overflow. The C register, in conjunction with the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or can enable SK to be a sync clock each instruction cycle time. (See XAS instruction and EN register description below.) The G register contents are outputs to four general purpose bidirectional I/O ports. The Q register is an internal, latched, 8-bit register, used to hold data loaded from RAM and A, as well as 8-bit data from ROM. Its contents are output to the L I/O ports when the L drivers are enabled under program control. (See LEI instruction.) The eight L drivers, when enabled, output the contents of latched Q data to the L I/O ports. Also, the contents of L may be read directly into A and RAM. PROGRAM MEMORY Program memory consists of a 512-byte ROM. As can be seen by an examination of the COP413C instruction set, these words may be program instructions, program data, or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID, and LQID instructions, ROM must often be thought of as being organized into 8 pages of 64 words (bytes) each. ROM ADDRESSING ROM addressing is accomplished by a 9-bit PC register. Its binary value selects one of the 512 8-bit words contained in ROM. A new address is loaded into the PC register during each instruction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequential 9-bit binary count value. Two levels of subroutine nesting are implemented by two 9-bit subroutine save registers, SA and SB. ROM instruction words are fetched, decoded, and executed by the instruction decode, control and skip logic circuitry. DATA MEMORY Data Memory consists of a 128-bit RAM, organized as four data registers of 8 c 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper two bits (Br) selects one of four data registers and lower three bits of the 4bit Bd select one of eight 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from, or exchanged with, the A register (accumulator), they may also be loaded into the Q latches or loaded from the L ports. RAM addressing may also be performed directly by the XAD 3, 15 instruction. The most significant bit of Bd is not used to select a RAM digit. Hence, each physical digit of RAM may be selected by two different values of Bd as shown in Figure 4. The skip condition for XIS and XDS instructions will be true if Bd changes between 0 to 15, but not between 7 and 8 (see Table III). * Can be directly addressed by LBI instruction (See Table 3) TL/DD/8537 – 4 FIGURE 4. RAM Digit Address to Physical RAM Digit Mapping 7 Functional Description (Continued) register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected, disables SO as the shift register output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to ‘‘0’’. The SIO register functions as a 4-bit serial-in/serial-out shift register or as a binary counter, depending upon the contents of the EN register. (See EN register description below.) Its contents can be exchanged with A, allowing it to input or output a continuous serial data stream. With SIO functioning as a serial-in/serial-out shift register and SK as a sync clock, the COP413C is MICROWIRE compatible. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL; in the shift register mode, SK is a sync clock, inhibited when SKL is a logic ‘‘0’’. The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register (EN3–EN0). 1. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or as a 4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output is equal to the value of EN3. With EN0 reset, SIO is a serial shift register, shifting left each instruction cycle time. The data present at SI is shifted into the least significant bit of SIO. SO can be enabled to output the most significant bit of SIO each instruction cycle time. (See 4, below.) The SK output becomes a logic-controlled clock. 2. EN 1 is not used, it has no effect on the COP413C. 3. With EN2 set, the L drivers are enabled to output the data in Q to the L I/O ports. Resetting EN2 disables the L drivers, placing the L I/O ports in a high impedance input state. 4. EN3, in conjunction with EN0, affects the SO output. With EN0 set (binary counter option selected), SO will output the value loaded into EN3. With EN0 reset (serial shift INITIALIZATION The external RC network shown in Figure 5 must be connected to the RESET pin. The RESET pin is configured as a Schmitt trigger input. If not used, it should be connected to VCC. Initialization will occur whenever a logic ‘‘0’’ is applied to the RESET input, providing it stays low for at least three instruction cycle times. Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, EN, and G registers are cleared. The SK output is enabled as a SYNC output, providing a pulse each instruction cycle time. Data memory (RAM) is not cleared upon initialization. The first instruction at address 0 must be a CLRA (clear A register). TL/DD/8537 – 5 RC l 5 c Power Supply Rise Time and RC l 100 c CKI Period FIGURE 5. Power-Up Clear Circuit TABLE I. Enable Register ModesÐBits EN0 and EN3 EN0 EN3 0 0 Shift Register SIO 0 1 Shift Register 1 1 0 1 Binary Counter Binary Counter SI SO Input to Shift Register Input to Shift Register Input to Counter Input to Counter 0 8 Serial out 0 1 SK If SKL e 1, SK If SKL e 0, SK If SKL e 1, SK If SKL e 0, SK SK e SKL SK e SKL e e e e clock 0 clock 0 Functional Description (Continued) OSCILLATOR OPTIONS HALT MODE The COP413C is a fully static circuit; therefore, the user may stop the system oscillator at any time to halt the chip. The chip may be halted by the HALT instruction. Once in the HALT mode, the internal circuitry does not receive any clock signal, and is therefore frozen in the exact state it was in when halted. All information is retained until continuing. The HALT mode is the minimum power dissipation state. The HALT mode may be entered into by program control (HALT instruction) which forces CKO to a logic ‘‘1’’ state. The circuit can be awakened only by the RESET function. There are two options available that define the use of CKI and CKO. a. Cyrstal-Controlled Oscillator. CKI and CKO are connected to an external crystal. The instruction cycle time equals the crystal frequency divided by 8. b. RC-Controlled Oscillator. CKI is configured as a single pin RC-controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO is NC. The RC oscillator is not recommended in systems that require accurate timing or low current. The RC oscillator draws more current than an external oscillator (typically an additional 100 mA at 5V). However, when the part halts, it stops with CKI high and the halt current is at the minimum. POWER DISSIPATION The lowest power drain is when the clock is stopped. As the frequency increases so does current. Current is also lower at lower operating voltages. Therefore, to minimize power consumption, the user should run at the lowest speed and voltage that his application will allow. The user should take care that all pins swing to full supply levels to ensure that outputs are not loaded down and that inputs are not at some intermediate level which may draw current. Any input with a slow rise or fall time will draw additional current. A crystal- or resonator-generated clock will draw more than a square-wave input. An RC oscillator will draw even more current since the input is a slow rising signal. If using an external squarewave oscillator, the following equation can be used to calculate the COP413C current drain. Ic e Iq a (V c 20 c Fi) a (V c 1280 c Fl/Dv) where Ic e chip current drain in microamps Iq e quiescent leakage current (from curve) Fl e CKI frequency in megahertz V e chip VCC in volts Dv e divide by option selected For example, at 5V VCC and 400 kHz (divide by 8), Ic e 30 a (5 c 20 c 0.4) a (5 c 1280 c 0.4/8) Ic e 30 a 40 a 320 e 390 mA TL/DD/8537 – 6 FIGURE 6. COP413C Oscillator RC-Controlled Oscillator Crystal or Resonator Crystal Value R1 R2 32 kHz 455 kHz 2.000 MHz 220k 5k 2k 20M 10M 1M Component Value C1 pF C2 pF 30 80 30 5 – 36 40 6 – 36 R C Cycle Time 15k 82 pF 4 – 9 ms 30k 82 pF 8 – 16 ms 47k 100 pF 16 – 32 ms 56k 100 pF 16 – 32 ms Note: 15k s R s 150k, 50 pF s C s 150 pF 9 VCC t 4.5V COP413CH Only t 4.5V COP413CH Only 3.0 to 4.5V COP413C Only t 4.5V Functional Description (Continued) The SI and RESET inputs are Hi-Z inputs (Figure 7d ). I/O CONFIGURATIONS COP413C outputs have the following configurations, illustrated in Figure 7 : a. Standard SO, SK Output. A CMOS push-pull buffer with an N-channel device to ground in conjunction with a P-channel device to VCC, compatible with CMOS and LSTTL. b. Low Current G Output. This is the same configuration as (a) above except that the sourcing current is much less. c. Standard TRI-STATE L Output. L output is a CMOS output buffer similar to (a) which may be disabled by program control. When using the G I/O port as an input, set the output register to a logic ‘‘1’’ level. The P-channel device will act as a pull-up load. When using the L I/O port as an input, disable the L drivers with the LEI instruction. The drivers are then in TRI-STATE mode and can be driven externally. All output drivers use one or more of three common devices numbered 1 to 3. Minimum and maximum current (IOUT and VOUT) curves are given in Figure 8 for each of these devices to allow the designer to effectively use these I/O configurations. a. Standard Push-Pull Output b. Low Current Push-Pull Output TL/DD/8537 – 7 c. Standard TRI-STATE ‘‘L’’ Output FIGURE 7. I/O Configurations d. Hi-Z Input SO, SK, L Port, G Port Minimum Sink Current SO, SK, L Port Standard Minimum Source Current G Port Low Current Minimum Source Current COP413C/COP413CH Low Current G Port Maximum Source Current COP313C/COP313CH Low Current G Port Maximum Source Current Maximum Quiescent Current TL/DD/8537 – 8 FIGURE 8 10 COP413C Instruction Set Table III provides the mnemonic, operand, machine code, data flow, skip conditions and description associated with each instruction in the COP413C instruction set. Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table. TABLE II. COP413C Instruction Set Table Symbols Symbol Symbol Definition Definition INTERNAL ARCHITECTURE SYMBOLS INSTRUCTION OPERAND SYMBOLS A B Br Bd C EN G L M d r PC Q SA SB SIO SK 4-bit Accumulator 6-bit RAM Address Register Upper 2 bits of B (register address) Lower 4 bits of B (digit address) 1-bit Carry Register 4-bit Enable Register 4-bit Register to latch data for G I/O Port 8-bit TRI-STATE I/O Port 4-bit contents of RAM Memory pointed to by B Register 9-bit ROM Address Register (program counter) 8-bit Register to latch data for L I/O Port 9-bit Subroutine Save Register A 9-bit Subroutine Save Register B 4-bit Shift Register and Counter Logic-Controlled Clock Output 4-bit Operand Field, 0 – 15 binary (RAM Digit Select) 2-bit Operand Field, 0 – 3 binary (RAM Register Select) a 9-bit Operand Field, 0 – 511 binary (ROM Address) y 4-bit Operand Field, 0 – 15 binary (Immediate Data) RAM(s) Contents of RAM location addressed by s ROM(t) Contents of ROM location addressed by t OPERATIONAL SYMBOLS a b x Ý e A Z : Plus Minus Replaces Is exchanged with Is equal to The one’s complement of A Exclusive-OR Range of values TABLE III. COP413C Instruction Set Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description ARITHMETIC INSTRUCTIONS ASC 30 À 0011 À 0000 À A a C a RAM(B) Carry x C ADD 31 À 0011 À 0001 À A a RAM(B) 5b À 0101 À Aay CLRA 00 À 0000 À 0000 À 0 COMP 40 À 0100 À 0000 À A NOP 44 À 0100 À 0100 À None RC 32 À 0011 À 0010 À ‘‘0’’ SC 22 À 0010 À 0010 À XOR 02 À 0000 À 0010 À AISC y y À xA Carry Add with Carry, Skip on Carry None Add RAM to A Carry Add immediate, Skip on Carry (y i 0) xA None Clear A xA None One’s complement of A to A None No Operation xC None Reset C ‘‘1’’ xC None Set C A RAM(B) None Exclusive-OR RAM with A Z xA xA 11 xA COP413C Instruction Set (Continued) TABLE III. COP413C Instruction Set (Continued) Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description TRANSFER OF CONTROL INSTRUCTIONS JID FF À 1111 À 1111 À ROM (PC8, A,M) PC7:0 x None Jump Indirect (Note 2) JMP a 6b – À 0110 À 000 À a8 À a7:0 À À a x PC None Jump JP a – a6:0 À1À À (pages 2, 3 only) or a5:0 À 11 À À (all other pages) a x PC6:0 None Jump within Page (Note 1) a x PC5:0 None Jump to Subroutine Page (Note 2) None Jump to Subroutine None Return from Subroutine Always Skip on Return Return from Subroutine then Skip None Halt processor – JSRP a – À 10 À a5:0 JSR a 6b – À 0110 À 100 À a8 À a7:0 À À RET 48 À 0100 À 1000 À RETSK 49 À 0100 À 10011 À HALT 33 38 À 0011 À 0011 À À 0011 À 1000 À À x SA x SB 010 x PC8:6 a x PC5:0 PC a 1 x SA x SB a x PC SB x SA x PC SB x SA x PC PC a 1 MEMORY REFERENCE INSTRUCTIONS CAMQ 33 3C À 0011 À 0011 À À 0011 À 1100 À A x Q7:4 RAM(B) x Q3:0 None Copy A, RAM to Q CQMA 33 2C À 0011 À 0011 À À 0010 À 1100 À Q7:4 x RAM(B) Q3:0 x A None Copy Q to RAM, A b5 À 00 À r À 0101 À RAM(B) x A Br Z r x Br None Load RAM into A Exclusive-OR Br with r BF À 1011 À 1111 À ROM(PC8,A,M) SA x SB None Load Q Indirect 0 0 0 0 None Reset RAM Bit None Set RAM Bit None Store Memory Immediate and Increment Bd None Exchange RAM with A, Exclusive-OR Br with r None Exchange A with RAM (3,15) LD r LQID RMB 0 1 2 3 4C 45 42 43 À 0100 À 1100 À À 0100 À 0101 À À 0100 À 0010 À À 0100 À 0011 À SMB 0 1 2 3 4D 47 46 4B À 0100 À 1101 À À 0100 À 0111 À À 0100 À 0110 À À 0100 À 1011 À STII y 7b À 0111 À X r b6 À 00 À r À 0110 À XAD 3,15 23 BF À 0010 À 0011 À À 1011 À 1111 À y À xQ x RAM(B)0 x RAM(B)1 x RAM(B)2 x RAM(B)3 1 x RAM(B)0 1 x RAM(B)1 1 x RAM(B)2 1 x RAM(B)3 y x RAM(B) Bd a 1 x Bd RAM(B) Ý A Br Z r x Br RAM(3,15) Ý A 12 COP413C Instruction Set (Continued) TABLE III. COP413C Instruction Set (Continued) Mnemonic Operand Hex Code Machine Language Code (Binary) Data Flow Skip Conditions Description MEMORY REFERENCE INSTRUCTIONS (Continued) XDS r b7 À 00 À r À 0111 À RAM(B) Ý A Bd – 1 x Bd Br Z r x Br Bd decrements past 0 Exchange RAM with A and Decrement Bd Exclusive-OR Br with r XIS r b4 À 00 À r À 0100 À RAM(B) Ý A Bd a 1 x Bd Br Z r x Br Bd increments past 15 Exchange RAM with A and Increment Bd Exclusive-OR Br with r x Bd None Copy A to Bd REGISTER REFERENCE INSTRUCTIONS CAB 50 À 0101 À 0000 À A CBA 4E À 0100 À 1110 À Bd xA None Copy Bd to A xB Skip until not a LBI Load B Immediate with r,d None Load EN Immediate LBI r,d – À 00 À r À (d - 1) À (d e 0,9:15) r,d LEI y 33 6b À 0011 À 0011 À À 0010 À y À y SKC 20 À 0010 À 0000 À C e ‘‘1’’ Skip if C is True SKE 21 À 0010 À 0001 À A e RAM(B) Skip if A Equals RAM SKGZ 33 21 À 0011 À 0011 À À 0010 À 0001 À G3:0 e 0 Skip if G is Zero (all 4 bits) 0 1 2 3 33 01 11 03 13 À 0011 À 0011 À À 0000 À 0001 À À 0001 À 0001 À À 0000 À 0011 À À 0010 À 0011 À 0 1 2 3 01 11 03 13 À 0000 À 0001 À À 0001 À 0001 À À 0000 À 0011 À À 0001 À 0011 À x EN TEST INSTRUCTIONS SKGBZ SKMBZ 1st byte * 2nd byte Skip if G Bit is Zero G0 G1 G2 G3 e e e e 0 0 0 0 RAM(B)0 RAM(B)1 RAM(B)2 RAM(B)3 e e e e 0 0 0 0 Skip if RAM Bit is Zero INPUT/OUTPUT INSTRUCTIONS xA ING 33 2A À 0011 À 0011 À À 0010 À 1010 À G INL 33 2E À 0011 À 0011 À À 0010 À 1110 À L7:4 L3:0 OMG 33 3A À 0011 À 0011 À À 0011 À 1010 À RAM(B) XAS 4F À 0100 À 1111 À A x RAM(B) xA xG Ý SIO, C x SKL None Input G Ports to A None Input L Ports to RAM, A None Output RAM to G Ports None Exchange A with SIO Note 1: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page. Note 2: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP may not jump to the last word in page 2. 13 Description of Selected Instructions The following information is provided to assist the user in understanding the operation of several unique instructions and to provide notes useful to programmers in writing COP413C programs. INSTRUCTION SET NOTES a. The first word of a COP413C program (ROM address 0) must be a CLRA (Clear A) instruction. b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of the skipped instruction. Thus all program paths take the same number of cycle times whether instructions are skipped or executed (except JID and LQID). c. The ROM is organized into eight pages of 64 words each. The program counter is a 9-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID, or LQID instruction is located in the last word of a page, the instruction operates as if it were in the next page. For example: A JP located in the last word of a page will jump to a location in the next page. Also, a LQID or JID located in the last word in page 3 or 7 will access data in the next group of four pages. XAS INSTRUCTION XAS (Exchange A with SIO) exchanges the 4-bit contents of the accumulator with the 4-bit contents of the SIO register. The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register.) If SIO is selected as a shift register, an XAS instruction must be performed once every four instruction cycle times to effect a continuous data stream. JID INSTRUCTION JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower eight bits of the ROM address register PC with the contents of ROM addressed by the 9-bit word, PC8, A, M. PC8 is not affected by this instruction. COPS Programming Manual For detailed information on writing. COPS programs, the COPS Programming Manual 424410284-001 provides an indepth discussion of the COPS architecture, instruction set and general techniques of COPS programming. This manual is written with the programmer in mind. Note: JID uses two instruction cycles if executed, one if skipped. LQID INSTRUCTION LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 9-bit word PC8, A, M. LQID can be used for table look-up or code conversion such as BCD to 7-segment. The LQID instruction ‘‘pushes’’ the stack (PC a 1 x SA x SB) and replaces the least significant eight bits of the PC as follows: A x PC7:4, RAM(B) x PC3:0, leaving PC8 unchanged. The ROM data pointed to by the new address is fetched and loaded into the Q latches. Next, the stack is ‘‘popped’’ (SB x SA x PC), restoring the saved value of the PC to continue sequential program execution. Since LQID pushes SA x SB, the previous contents of SB are lost. OPTION LISTÐOSCILLATOR SELECTION The oscillator option selected must be sent in with the EPROM of ROM Code for masking into the COP413C. Select the appropriate option, make a photocopy of the table and send it with the EPROM. COP413C/COP313C Option 1: Oscillator selection e 0 Ceramic Resonator input frequency divided by 8. CKO is oscillator output. e 1 Single pin RC controlled oscillator divided by 4. CKO is no connection. Note: The following option information is to be sent to National along with the EPROM. Option 1: Value e ÐÐ is Oscillator Selected. Note: LQID uses two instruction cycles if executed, one if skipped. 14 Physical Dimensions inches (millimeters) 20-Lead Hermetic Dual-In-Line Package (D) Order Number COP313C – XXX/D, COP313CH – XXX/D, COP413C – XXX/D, COP413CH – XXX/D NS Package Number D20A 15 COP413C/COP413CH/COP313C/COP313CH Single-Chip CMOS Microcontrollers Physical Dimensions inches (millimeters) (Continued) Lit. Ý101975 20-Lead Molded Dual-In-Line Package (N) Order Number COP313C – XXX/N, COP313CH – XXX/N, COP413C–XXX/N or COP413CH – XXX/N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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