CIRRUS CS2000-CP

CS2000-CP
Fractional-N Clock Synthesizer & Clock Multiplier
Features
General Description
 Delta-Sigma Fractional-N Frequency Synthesis
The CS2000-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2000-CP is based on a hybrid analog-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for both frequency synthesis/clock generation from a
stable reference clock as well as generation of a lowjitter clock relative to an external noisy synchronization
clock. The design is also unique in that it can generate
low-jitter clocks relative to noisy external synchronization clocks at frequencies as low as 50 Hz. The
CS2000-CP supports both I²C and SPI for full software
control.
–






Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to
30 MHz Clock Source
Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in HighResolution Mode
I²C™ / SPI™ Control Port
Configurable Auxiliary Output
Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
Minimal Board Space Required
– No External Analog Loop-filter
Components
The CS2000-CP is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer
development kits are also available for device evaluation. Please see “Ordering Information” on page 36 for
complete details.
3.3 V
I²C/SPI
Software Control
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
I²C / SPI
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Fractional-N
Frequency Synthesizer
Output to Input
Clock Ratio
50 Hz to 30 MHz
Frequency
Reference
Auxiliary
Output
6 to 75 MHz
PLL Output
N
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
http://www.cirrus.com
Copyright  Cirrus Logic, Inc. 2009
(All Rights Reserved)
AUG '09
DS761F1
CS2000-CP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 5
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
RECOMMENDED OPERATING CONDITIONS .................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8
PLL PERFORMANCE PLOTS ............................................................................................................... 9
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................. 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 11
4. ARCHITECTURE OVERVIEW ............................................................................................................. 12
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 12
4.2 Hybrid Analog-Digital Phase Locked Loop .................................................................................... 12
4.2.1 Fractional-N Source Selection for the Frequency Synthesizer .............................................. 13
5. APPLICATIONS ................................................................................................................................... 14
5.1 Timing Reference Clock Input ........................................................................................................ 14
5.1.1 Internal Timing Reference Clock Divider ............................................................................... 14
5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 15
5.1.3 External Reference Clock (REF_CLK) .................................................................................. 15
5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 15
5.2.1 CLK_IN Skipping Mode ......................................................................................................... 15
5.2.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 17
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 19
5.3.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 19
5.3.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 19
5.3.3 Ratio Modifier (R-Mod) .......................................................................................................... 20
5.3.4 Effective Ratio (REFF) .......................................................................................................... 20
5.3.5 Fractional-N Source Selection ............................................................................................... 21
5.3.6 Ratio Configuration Summary ............................................................................................... 22
5.4 PLL Clock Output ........................................................................................................................... 23
5.5 Auxiliary Output .............................................................................................................................. 23
5.6 Clock Output Stability Considerations ............................................................................................ 24
5.6.1 Output Switching ................................................................................................................... 24
5.6.2 PLL Unlock Conditions .......................................................................................................... 24
5.7 Required Power Up Sequencing .................................................................................................... 24
6. SPI / I²C CONTROL PORT ................................................................................................................... 24
6.1 SPI Control ..................................................................................................................................... 25
6.2 I²C Control ...................................................................................................................................... 25
6.3 Memory Address Pointer ............................................................................................................... 27
6.3.1 Map Auto Increment .............................................................................................................. 27
7. REGISTER QUICK REFERENCE ........................................................................................................ 27
8. REGISTER DESCRIPTIONS ................................................................................................................ 28
8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 28
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 28
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 28
8.2 Device Control (Address 02h) ........................................................................................................ 28
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 28
8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 28
8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 29
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 29
8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 29
8.3.2 Ratio Selection (RSel[1:0]) .................................................................................................... 29
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8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 29
8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 30
8.4 Device Configuration 2 (Address 04h) ........................................................................................... 30
8.4.1 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 30
8.4.2 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 30
8.5 Global Configuration (Address 05h) ............................................................................................... 30
8.5.1 Device Configuration Freeze (Freeze) ................................................................................ 30
8.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 31
8.6 Ratio 0 - 3 (Address 06h - 15h) ...................................................................................................... 31
8.7 Function Configuration 1 (Address 16h) ........................................................................................ 31
8.7.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 31
8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 32
8.7.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 32
8.8 Function Configuration 2 (Address 17h) ........................................................................................ 32
8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 32
8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 32
8.9 Function Configuration 3 (Address 1Eh) ........................................................................................ 33
8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 33
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 34
9.1 High Resolution 12.20 Format ....................................................................................................... 34
9.2 High Multiplication 20.12 Format ................................................................................................... 34
10. PACKAGE DIMENSIONS .................................................................................................................. 35
THERMAL CHARACTERISTICS ......................................................................................................... 35
11. ORDERING INFORMATION .............................................................................................................. 36
12. REFERENCES .................................................................................................................................... 36
13. REVISION HISTORY .......................................................................................................................... 36
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 6
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 9
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 9
Figure 4. CLK_IN Random Jitter Rejection and Tolerance ......................................................................... 9
Figure 5. Control Port Timing - I²C Format ................................................................................................ 10
Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 11
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 12
Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 13
Figure 9. Fractional-N Source Selection Overview ................................................................................... 13
Figure 10. Internal Timing Reference Clock Divider ................................................................................. 14
Figure 11. REF_CLK Frequency vs a Fixed CLK_OUT ............................................................................ 14
Figure 12. External Component Requirements for Crystal Circuit ............................................................ 15
Figure 13. CLK_IN removed for > 223 SysClk cycles ................................................................................ 16
Figure 14. CLK_IN removed for < 223 SysClk cycles but > tCS .................................................................................. 16
Figure 15. CLK_IN removed for < tCS .................................................................................................................................. 17
Figure 16. Low bandwidth and new clock domain .................................................................................... 18
Figure 17. High bandwidth with CLK_IN domain re-use ........................................................................... 18
Figure 18. Ratio Feature Summary ........................................................................................................... 22
Figure 19. PLL Clock Output Options ....................................................................................................... 23
Figure 20. Auxiliary Output Selection ........................................................................................................ 23
Figure 21. Control Port Timing in SPI Mode ............................................................................................. 25
Figure 22. Control Port Timing, I²C Write .................................................................................................. 26
Figure 23. Control Port Timing, I²C Aborted Write + Read ....................................................................... 26
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LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 20
Table 2. Example 12.20 R-Values ............................................................................................................ 34
Table 3. Example 20.12 R-Values ............................................................................................................ 34
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1. PIN DESCRIPTION
VD
1
10
SDA/CDIN
GND
2
9
SCL/CCLK
CLK_OUT
3
8
AD0/CS
AUX_OUT
4
7
XTI/REF_CLK
CLK_IN
5
6
XTO
Pin Name
#
Pin Description
VD
1
Digital Power (Input) - Positive power supply for the digital and analog sections.
GND
2
Ground (Input) - Ground reference.
CLK_OUT
3
PLL Clock Output (Output) - PLL clock output.
4
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on register configuration.
5
Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference.
6
7
Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
8
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C
Mode. CS is the chip select signal in SPI Mode.
9
Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in I²C and SPI
mode.
AUX_OUT
CLK_IN
XTO
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
DS761F1
10 Serial Control Data (Input/Output) - SDA is the data I/O line in I²C Mode. CDIN is the input data
line for the control port interface in SPI Mode.
5
CS2000-CP
2. TYPICAL CONNECTION DIAGRAM
Note1
Notes:
1. Resistors
required for I2C
operation.
0.1 µF
2 kΩ
1 µF
+3.3 V
2 kΩ
VD
SCL/CCLK
System MicroController
SDA/CDIN
AD0/CS
CS2000-CP
Frequency Reference
CLK_IN
1
or
2
XTI/REF_CLK
CLK_OUT
To circuitry which requires
a low-jitter clock
AUX_OUT
To other circuitry or
Microcontroller
XTO
GND
Low-Jitter
Timing Reference
REF_CLK
1
N.C. x
XTO
or
Crystal
XTI
2
XTO
40 pF
40 pF
Figure 1. Typical Connection Diagram
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CS2000-CP
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1)
Parameters
DC Power Supply
Symbol
Min
Typ
Max
Units
VD
3.1
3.3
3.5
V
TAC
-10
-
+70
°C
Ambient Operating Temperature (Power Applied)
Commercial Grade
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits
may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground.
Parameters
Symbol
Min
Max
Units
DC Power Supply
VD
-0.3
6.0
V
Input Current
IIN
-
±10
mA
Digital Input Voltage (Note 2)
VIN
-0.3
VD + 0.4
V
Ambient Operating Temperature (Power Applied)
TA
-55
125
°C
Storage Temperature
Tstg
-65
150
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade).
Parameters
Symbol
Min
Typ
Max
Units
Power Supply Current - Unloaded
(Note 3)
ID
-
12
18
mA
Power Dissipation - Unloaded
(Note 3)
PD
-
40
60
mW
Input Leakage Current
IIN
-
-
±10
µA
Input Capacitance
IC
-
8
-
pF
High-Level Input Voltage
VIH
70%
-
-
VD
Low-Level Input Voltage
VIL
-
-
30%
VD
High-Level Output Voltage (IOH = -1.2 mA)
VOH
80%
-
-
VD
Low-Level Output Voltage (IOH = 1.2 mA)
VOL
-
-
20%
VD
Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output
frequency by load capacitance and power supply voltage.
For example, fCLK_OUT (49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to
these loading conditions on CLK_OUT.
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CS2000-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
CL = 15 pF.
Parameters
Crystal Frequency
Fundamental Mode XTAL
Symbol
Conditions
Min
Typ
Max
Units
fXTAL
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
RefClkDiv[1:0] = 10
RefClkDiv[1:0] = 01
RefClkDiv[1:0] = 00
8
16
32
-
14
28
50
MHz
MHz
MHz
8
16
32
-
14
28
56
MHz
MHz
MHz
45
-
55
%
Reference Clock Input Frequency
fREF_CLK
Reference Clock Input Duty Cycle
DREF_CLK
Internal System Clock Frequency
fSYS_CLK
8
14
MHz
fCLK_IN
50 Hz
-
30
MHz
2
10
-
-
UI
ns
Clock Input Frequency
Clock Input Pulse Width (Note 4)
Clock Skipping Timeout
pwCLK_IN
fCLK_IN < fSYS_CLK/96
fCLK_IN > fSYS_CLK/96
tCS
(Notes 5, 6)
20
-
-
ms
Clock Skipping Input Frequency
fCLK_SKIP
(Note 6)
50 Hz
-
80
kHz
PLL Clock Output Frequency
fCLK_OUT
6
-
75
MHz
PLL Clock Output Duty Cycle
tOD
Measured at VD/2
45
50
55
%
Clock Output Rise Time
tOR
20% to 80% of VD
-
1.7
3.0
ns
Clock Output Fall Time
tOF
80% to 20% of VD
-
1.7
3.0
ns
Period Jitter
tJIT
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
(Note 7)
-
70
-
ps rms
(Notes 7, 8)
-
50
-
ps rms
(Notes 7, 9)
-
175
-
ps rms
PLL Lock Time - CLK_IN (Note 10)
tLC
fCLK_IN < 200 kHz
fCLK_IN > 200 kHz
-
100
1
200
3
UI
ms
PLL Lock Time - REF_CLK
tLR
fREF_CLK = 8 to 75 MHz
-
1
3
ms
Output Frequency Synthesis Resolution (Note 11)
ferr
High Resolution
High Multiplication
0
0
-
±0.5
±112
ppm
ppm
Notes: 4. 1 UI (unit interval) corresponds to tSYS_CLK or 1/fSYS_CLK.
5. tCS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequency, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of tCS.
6. Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 15 for more information.
7. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
8. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
9. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
10. 1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN.
11. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
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PLL PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): VD = 3.3 V; TA = 25 °C (Commercial Grade); CL = 15 pF;
fCLK_OUT = 12.288 MHz; fCLK_IN = 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz);
AuxOutSrc[1:0] = 11.
10,000
10
1 Hz Bandwidth
128 Hz Bandwidth
1 Hz Bandwidth
128 Hz Bandwidth
0
-10
Jitter Transfer (dB)
Max Input Jitter Level (usec)
1,000
100
10
-20
-30
-40
1
-50
0.1
1
10
100
1,000
-60
10,000
1
10
Input Jitter Frequency (Hz)
100
1000
10000
Input Jitter Frequency (Hz)
Figure 2. CLK_IN Sinusoidal Jitter Tolerance
Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
1000
1 Hz Bandwidth
128 Hz Bandwidth
Output Jitter Level (nsec)
100
Unlock
10
1
Unlock
0.1
0.01
0.01
0.1
1
10
100
1000
Input Jitter Level (nsec)
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
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CS2000-CP
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
Bus Free-Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low Time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 12)
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
tr
-
1
µs
Fall Time SCL and SDA
tf
-
300
ns
SDA Setup Time to SCL Rising
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Delay from Supply Voltage Stable to Control Port Ready
tdpor
100
-
µs
Notes: 12. Data must be held for sufficient time to bridge the transition time, tf, of SCL.
VD
t dpor
Repeated
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
Stop
Start
t
low
t
hdd
t sud
t sust
tr
Figure 5. Control Port Timing - I²C Format
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CS2000-CP
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF.
Parameter
Symbol
Min
Max
Unit
fccllk
-
6
MHz
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CCLK Clock Frequency
CCLK Edge to CS Falling
(Note 13)
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 14)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 15)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 15)
tf2
-
100
ns
tdpor
100
-
µs
Delay from Supply Voltage Stable to Control Port Ready
Notes: 13. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For fcclk < 1 MHz.
VD
tdpor
CS
t spi
t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu
tdh
Figure 6. Control Port Timing - SPI Format (Write Only)
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CS2000-CP
4. ARCHITECTURE OVERVIEW
4.1
Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies
the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input
clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 7).
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase
reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The
delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the
reference clock and the VCO output (thus the one’s density of the modulator sets the fractional value). This
allows the design to be optimized for very fast lock times for a wide range of output frequencies without the
need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference
clock should be stable and jitter-free.
Timing Reference
Clock
Phase
Comparator
Internal
Loop Filter
Voltage Controlled
Oscillator
PLL Output
Fractional-N
Divider
Delta-Sigma
Modulator
N
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer
4.2
Hybrid Analog-Digital Phase Locked Loop
The addition of the Digital PLL and Fractional-N Logic (shown in Figure 8) to the Fractional-N Frequency
Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical analog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges
without the need to change external loop filter components while maintaining impressive jitter reduction performance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the frequency reference and compares that to the desired ratio. The digital logic generates a value of N which is
then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice
that the frequency and phase of the timing reference signal do not affect the output of the PLL since the
digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which
the loop filter bandwidth can be altered. The PLL bandwidth is automatically set to a wide-bandwidth mode
to quickly achieve lock and then reduced for optimal jitter rejection.
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Delta-Sigma Fractional-N Frequency Synthesizer
Timing Reference
Clock
Phase
Comparator
Internal
Loop Filter
Voltage Controlled
Oscillator
PLL Output
Fractional-N
Divider
Delta-Sigma
Modulator
Digital PLL and Fractional-N Logic
N
Digital Filter
Frequency
Comparator for
Frac-N Generation
Frequency Reference
Clock
Output to Input Ratio for Hybrid mode
Figure 8. Hybrid Analog-Digital PLL
4.2.1
Fractional-N Source Selection for the Frequency Synthesizer
The fractional-N value for the frequency synthesizer can be sourced from either a static ratio or a dynamic
ratio generated from the digital PLL (see Figure 9). This allows for the selection between operating in the
static ratio based Frequency Synthesizer Mode as a simple frequency synthesizer (for frequency generation from the Timing Reference Clock) and in the dynamic ratio based Hybrid PLL Mode (for jitter reduction and clock multiplication). Selection between these two modes can either be made automatically
based on the presence of the Frequency Reference Clock or manually through register controls.
.
Fractional-N
Frequency Synthesizer
Timing Reference Clock
PLL Output
N
Output to Input Ratio for Synthesizer Mode
Frequency Reference Clock
Digital PLL & Fractional-N Logic
Output to Input ratio for Hybrid Mode
Figure 9. Fractional-N Source Selection Overview
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5. APPLICATIONS
5.1
Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL output the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock
directly affects the performance of the PLL and hence the quality of the PLL output.
5.1.1
Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on
the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls
within the valid range as indicated in “AC Electrical Characteristics” on page 8.
Timing Reference Clock
XTI/REF_CLK
8 MHz < RefClk <
50 MHz (XTI)
58 MHz (REF_CLK)
Timing Reference
Clock Divider
÷1
÷2
÷4
Internal Timing
Reference Clock
Fractional-N
Frequency
Synthesizer
8 MHz < SysClk < 14 MHz
PLL Output
N
RefClkDiv[1:0]
Figure 10. Internal Timing Reference Clock Divider
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent
upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Characteristics” on page 8 for more details.
For the lowest possible output jitter, attention should be paid to the absolute frequency of the Timing Reference Clock relative to the PLL Output frequency (CLK_OUT). To minimize output jitter, the Timing Reference Clock frequency should be chosen such that fRefClk is at least +/-15 kHz from fCLK_OUT*N/32
where N is an integer. Figure 11 shows the effect of varying the RefClk frequency around fCLK_OUT*N/32.
It should be noted that there will be a jitter null at the zero point when N = 32 (not shown in Figure 11). An
example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to
achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
f L ≤ f RefClk ≤ f H where:
CLK__OUT Jitter
180
= 12.288MHz × 0.96875 + 15kHz
= 11.919MHz
and
f H = f CLK_OUT × 32
------ – 15kHz
32
= 12.288MHz × 1 + 15kHz
Typical Base Band Jitter (psec)
f
CLK__OUT
f L = f CLK_OUT × 31
------ + 15kHz
32
160
140
120
100
-15 kHz
80
+15 kHz
60
40
20
-80
= 12.273MHz
*32/N
-60
-40
-20
0
20
40
60
80
Normalized REF__CLK Frequency (kHz)
Figure 11. REF_CLK Frequency vs a Fixed CLK_OUT
Referenced Control
Register Location
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 32
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5.1.2
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 12. As shown,
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the “AC Electrical Characteristics” on page 8 for the allowed crystal frequency range.
XTI
40 pF
XTO
40 pF
Figure 12. External Component Requirements for Crystal Circuit
5.1.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to
GND.
5.2
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used in Hybrid PLL Mode by the Digital PLL and FractionalN Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL” on page 13). The Digital PLL first compares the CLK_IN frequency to the PLL output. The
Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal
timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock
which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference
clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 8.
5.2.1
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to 20 ms (tCS) at a time (see “AC Electrical Characteristics” on page 8 for specifications). CLK_IN
skipping mode can only be used when the CLK_IN frequency is below 80 kHz and CLK_IN is reapplied
within 20 ms of being removed. The ClkSkipEn bit enables this function.
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CS2000-CP
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 223 SysClk cycles (466 ms
to 1048 ms) after CLK_IN is removed (see Figure 13). This is true as long as CLK_IN does not glitch or
have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as
a change in frequency causing clock skipping and the 223 SysClk cycle time-out to be bypassed and the
PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 223 SysClk cycles
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock
Output” on page 23. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
time listed in the “AC Electrical Characteristics” on page 8 after which lock will be acquired and the PLL
output will resume.
223 SysClk cycles
223 SysClk cycles
Lock Time
Lock Time
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
= invalid clocks
Figure 13. CLK_IN removed for > 223 SysClk cycles
If it is expected that CLK_IN will be removed and then reapplied within 223 SysClk cycles but later than
tCS, the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in
Figure 14; note that the lower figure shows that the PLL output frequency may change and be incorrect
without an indication of an unlock condition.
223 SysClk cycles
tCS
223 SysClk cycles
tCS
Lock Time
Lock Time
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
= invalid clocks
tCS
223 SysClk cycles
Lock Time
CLK_IN
ClkSkipEn= 1
ClkOutUnl=1
PLL_OUT
UNLOCK
= invalid clocks
Figure 14. CLK_IN removed for < 223 SysClk cycles but > tCS
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If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn bit determines whether PLL_OUT
continues while the PLL re-acquires lock (see Figure 15). When ClkSkipEn is disabled and CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only
for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this
time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous
throughout the missing CLK_IN period including the time while the PLL re-acquires lock.
tCS
tCS
Lock Time
CLK_IN
ClkSkipEn=1
ClkOutUnl=0 or 1
CLK_IN
ClkSkipEn=0
ClkOutUnl=1
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
= invalid clocks
tCS
Lock Time
CLK_IN
ClkSkipEn=0
ClkOutUnl=0
PLL_OUT
UNLOCK
Figure 15. CLK_IN removed for < tCS
Referenced Control
Register Location
ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 31
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32
5.2.2
Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128
Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter
transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL
input directly to the PLL output without attenuation. In some applications it is desirable to have a very low
minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others
it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the
PLL without attenuation.
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Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other system clocks and associated data are derived will benefit from the maximum jitter and wander rejection of
the lowest PLL bandwidth setting. See Figure 16.
PLL
BW = 1 Hz
CLK_IN
Wander > 1 Hz
PLL_OUT
Wander and Jitter > 1 Hz Rejected
MCLK
Jitter
MCLK
Subclocks generated
from new clock domain.
or
LRCK
LRCK
SCLK
SCLK
D0
SDATA
D1
SDATA
D0
D1
Figure 16. Low bandwidth and new clock domain
Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data
are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the
system. See Figure 17. If there is substantial wander on the CLK_IN signal in these applications, it may
be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the
CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment
with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system
timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and
those synchronous to the PLL_OUT domain.
PLL
BW = 128 Hz
CLK_IN
Wander < 128 Hz
PLL_OUT
Jitter > 128 Hz Rejected
Wander < 128 Hz Passed to Output
MCLK
Jitter
MCLK
or
Subclocks and data re-used
from previous clock domain.
LRCK
LRCK
SCLK
SCLK
SDATA
D0
D1
SDATA
D0
D1
Figure 17. High bandwidth with CLK_IN domain re-use
It should be noted that manual adjustment of the minimum loop bandwidth is not necessary to acquire
lock; this adjustment is made automatically by the Digital PLL. While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to
the minimum value selected by the ClkIn_BW[2:0] bits.
Referenced Control
Register Location
ClkIn_BW[2:0] .......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 33
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5.3
Output to Input Frequency Ratio Configuration
5.3.1
User Defined Ratio (RUD), Frequency Synthesizer Mode
The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the
desired input to output clock ratio. Up to four different ratios, Ratio0-3, can be stored in the CS2000 register
space. The ratio pointed to by the RSel[1:0] bits is the currently selected ratio for the static ratio based
Frequency Synthesizer Mode. The 32-bit RUD is represented in a high-resolution 12.20 format where the
12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary
portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this
configuration. See “Calculating the User Defined Ratio” on page 34 for more information.
The status of internal dividers, such as the internal timing reference clock divider, are automatically taken
into account. Therefore RUD is simply the desired ratio of the output to input clock frequencies.
Referenced Control
Register Location
Ratio0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 31
Rsel[1:0] ................................“Ratio Selection (RSel[1:0])” on page 29
5.3.2
User Defined Ratio (RUD), Hybrid PLL Mode
The same four ratio locations, Ratio0-3, are used to store the User Defined Ratios for Hybrid PLL Mode.
The User Defined Ratio pointed to by the LockClk[1:0] bits is the currently selected ratio for the dynamic
ratio based Hybrid PLL Mode.
In addition to the High-Resolution format, a High-Multiplication format is also available. In the High-Multiplication Format Mode, the 32-bit RUD is represented in a 20.12 format where the 20 MSBs represent the
integer binary portion while the remaining 12 LSBs represent the fractional binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM.
The ratio format default is 20.12. The 20.12 ratio format is only available when both the LFRatioCfg bit is
cleared (20.12) and the FracNSrc bit is set (dynamic ratio). In Auto Fractional-N Source Mode (see section
5.3.5.2 on page 21) when CLK_IN is not present the LFRatioCfg bit is ignored and the ratio format is
12.20.
It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less
than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the
timing reference clock and the resolution of the RUD.
Referenced Control
Register Location
LockClk[1:0] ..........................“Lock Clock Ratio (LockClk[1:0])” section on page 30
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 32
FracNSrc ...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
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CS2000-CP
5.3.3
Ratio Modifier (R-Mod)
The Ratio Modifier is used to internally multiply/divide the currently addressed RUD (the Ratio0-3 stored
in the register space remain unchanged). The available options for RMOD are summarized in Table 1 on
page 20.
The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio
(REFF), see “Effective Ratio (REFF)” on page 20. If R-Mod is not desired, RModSel[2:0] should be left at
its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio
modifier.
RModSel[2:0]
Ratio Modifier
000
1
001
2
010
4
011
8
100
0.5
101
0.25
110
0.125
111
0.0625
Table 1. Ratio Modifier
Referenced Control
Register Location
Ratio0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 31
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 29
5.3.4
Effective Ratio (REFF)
The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as
previously described. REFF is calculated as follows:
REFF = RUD • RMOD
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For example
if RUD is 1024 an RMOD of 8 would produce an REFF value of 8192 which exceeds the 4096 limit of the
12.20 format. In all cases, the maximum and minimum allowable values for REFF are dictated by the frequency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on
page 8.
Selection of the user defined ratio from the four stored ratios is made by using the RSel[1:0] bits unless
auto clock switching is enabled in which case the LockClk[1:0] bits also select the ratio (see “Manual Fractional-N Source Selection for the Frequency Synthesizer” on page 21).
Referenced Control
Register Location
RSel[1:0] ...............................“Ratio Selection (RSel[1:0])” on page 29
LockClk[1:0] ..........................“Lock Clock Ratio (LockClk[1:0])” section on page 30
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5.3.5
Fractional-N Source Selection
To select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based Hybrid
PLL Mode, the source for the fractional-N value for the Frequency Synthesizer must be changed. The
Fractional-N value can either be sourced directly from the Effective Ratio (static ratio) or from the output
of the Digital PLL (dynamic ratio) (see Figure 18 on page 22). The setting of this function can be made
manual or automatically depending on the presence of CLK_IN.
5.3.5.1
Manual Fractional-N Source Selection for the Frequency Synthesizer
Manual selection of the fractional-N source for the frequency synthesizer is made by setting the
FracNSrc bit to select the desired ratio source. The LockClk[1:0] bits (even if unused) must be set
to the same value as the RSel[1:0] bits in order to maintain manual selectability of this function (see
Section 5.3.5.2 on page 21).
Referenced Control
Register Location
Rsel[1:0]................................ “Device Configuration 1 (Address 03h)” on page 29
LockClk[1:0] .......................... “Device Configuration 2 (Address 04h)” section on page 30
FracNSrc............................... “Device Configuration 2 (Address 04h)” section on page 30
5.3.5.2
Automatic Fractional-N Source Selection for the Frequency Synthesizer
Automatic source selection allows for the selection of the frequency synthesizer’s fractional-N value
to be made dependent on the presence of the CLK_IN signal. When CLK_IN is present the device
will use the dynamic ratio generated from the Digital PLL and CLK_IN for Hybrid PLL Mode. When
CLK_IN is not present, the device will use RefClk and the static ratio for Frequency Synthesizer
Mode. Before switching to SysClk and re-acquiring lock the CS2000 will wait for 223 SysClk cycles
after losing CLK_IN (see “CLK_IN Skipping Mode” on page 15).
The User Defined Ratio pointed to by RSel[1:0] should contain the desired CLK_OUT to RefClk ratio to be used when CLK_IN is not present. The User Defined Ratio pointed to by LockClk[1:0]
should contain the desired CLK_OUT to CLK_IN ratio to be used when CLK_IN is present. Automatic source selection is enabled when the LockClk[1:0] bits are set to point to a different User Defined Ratio from the one pointed to by the RSel[1:0] bits.
When automatic source selection is enabled, the FracNSrc bit (used for manual clock selection) will
be ignored.
To disable the automatic source selection feature, set the LockClk[1:0] bits and the RSel[1:0] bits
to the same value. The FracNSrc bit must then be used to select the desired clock used for the
PLL’s frequency reference.
Referenced Control
Register Location
RSel[1:0] ............................... “Ratio Selection (RSel[1:0])” on page 29
LockClk[1:0] .......................... “Lock Clock Ratio (LockClk[1:0])” section on page 30
FracNSrc............................... “Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
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5.3.6
Ratio Configuration Summary
The RUD is the user defined ratio for which up to four different values (Ratio0-3) can be stored in the register space. The RSel[1:0] or LockClk[1:0] bits then select the user defined ratio to be used (depending
on if static or dynamic ratio mode is to be used). The resolution for the RUD is selectable, for the dynamic
ratio mode, by setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, and ratio modifier
make up the effective ratio REFF, the final calculation used to determine the output to input clock ratio. The
effective ratio is then corrected for the internal dividers. The frequency synthesizer’s fractional-N source
selection is made between the static ratio (in frequency synthesizer mode) or the dynamic ratio generated
from the digital PLL (in Hybrid PLL mode) by either the FracNSrc bit for manual mode or the presence of
CLK_IN in automatic mode. The conceptual diagram in Figure 18 summarizes the features involved in the
calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer.
Timing Reference Clock
(XTI/REF_CLK)
RSel[1:0]
≠ LockClk[1:0]
CLK_IN sense
(auto selection)
Divide
Effective Ratio REFF
RSel[1:0] = LockClk[1:0]
RefClkDiv[1:0]
FracNSrc
(manual selection)
RSel[1:0]
User Defined Ratio RUD
Ratio 0
Ratio Format
Ratio 1
12.20
only
Ratio 2
RModSel[2:0]
RefClkDiv[1:0]
Ratio
Modifier
R Correction
SysClk
Frequency
Synthesizer
PLL Output
Static Ratio
N
Dynamic Ratio
Ratio 3
12.20
20.12
Ratio
Modifier
R Correction
LFRatioCfg
Digital PLL &
Fractional N Logic
Frequency Reference Clock
(CLK_IN)
LockClk[1:0]
Figure 18. Ratio Feature Summary
Referenced Control
Register Location
Ratio0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 31
RSel[1:0] ...............................“Ratio Selection (RSel[1:0])” on page 29
LockClk[1:0] ..........................“Lock Clock Ratio (LockClk[1:0])” section on page 30
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 32
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 29
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 32
FracNSrc ...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
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5.4
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl
PLL Locked/Unlocked
0
0
2:1 Mux
ClkOutDis
0
1
2:1 Mux
PLL Clock Output
PLL Clock Output Pin
(CLK_OUT)
PLLClkOut
1
PLL Output
Figure 19. PLL Clock Output Options
Referenced Control
Register Location
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32
ClkOutDis ..............................“PLL Clock Output Disable (ClkOutDis)” on page 29
5.5
Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 20, to one of four signals: reference clock (RefClk), input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator
(Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is
then used to control the output driver type and polarity of the LOCK signal (see section 8.7.2 on page 32).
If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the
CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit.
AuxOutSrc[1:0]
Timing Reference Clock
(RefClk)
AuxOutDis
Frequency Reference Clock
(CLK_IN)
Auxiliary Output Pin
(AUX_OUT)
4:1 Mux
PLL Clock Output
(PLLClkOut)
AuxLockCfg
PLL Lock/Unlock Indication
(Lock)
Figure 20. Auxiliary Output Selection
Referenced Control
Register Location
AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 29
AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 28
AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 32
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5.6
Clock Output Stability Considerations
5.6.1
Output Switching
CS2000 is designed such that re-configuration of the clock routing functions do not result in a partial clock
period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an
output, changing the auxiliary output source between REF_CLK and CLK_OUT, changing between Frequency Synthesizer and Hybrid PLL Mode, and the automatic disabling of the output(s) during unlock will
not cause a runt or partial clock period.
The following exceptions/limitations exist:
•
Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator).
•
Switching AuxOutSrc[1:0] to or from 01 (PLL clock input) and to or from 11 (unlock indicator)
(Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
•
Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
5.6.2
PLL Unlock Conditions
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the presence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked:
5.7
•
Changes made to the registers which affect the Fraction-N value that is used by the Frequency Synthesizer. This includes all the bits shown in Figure 18 on page 22.
•
Any discontinuities on the Timing Reference Clock, REF_CLK.
•
Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature
is enabled and the requirements of Clock Skipping are satisfied (see “CLK_IN Skipping Mode” on
page 15).
•
Gradual changes in CLK_IN frequency greater than ±30% from the starting frequency.
•
Step changes in CLK_IN frequency.
Required Power Up Sequencing
•
Apply power to the device. The output pins will remain low until the device is configured with a valid ratio
via the control port.
•
Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 during the initialization register writes; the order does not matter.
–
The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect
at the same time.
6. SPI / I²C CONTROL PORT
The control port is used to access the registers and allows the device to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs
and outputs. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
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The control port operates with either the SPI or I²C interface, with the CS2000 acting as a slave device. SPI Mode
is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting
the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state.
In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Referenced Control
Register Location
EnDevCfg1 ............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 30
EnDevCfg2 ............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 31
6.1
SPI Control
In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller),
and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The
device only supports write operations.
Figure 21 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first
eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are
the data which will be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the
MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically increment after each byte is read or written, allowing block writes of successive registers.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CCLK
CHIP ADDRESS
CDIN
1
0
0
1
1
1
MAP BYTE
1
0
INCR
6
5
4
3
2
DATA +n
DATA
1
0
7
6
1
0
7
6
1
0
Figure 21. Control Port Timing in SPI Mode
6.2
I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL.
There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected
to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the
device.
The signal timings for a read and write cycle are shown in Figure 22 and Figure 23. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS2000 after
a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The
eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or
writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from
the CS2000 after each input byte is read and is input from the microcontroller after each transmitted byte.
DS761F1
25
CS2000-CP
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
1
1
AD0
MAP BYTE
0
INCR
6
5
4
3
2
1
0
ACK
7
6
DATA +n
DATA +1
DATA
1
0
ACK
7
6
1
0
7
6
1
0
ACK
ACK
STOP
START
Figure 22. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
STOP
MAP BYTE
1 1 AD0 0
INCR
6
5
4
3
2
1
ACK
START
CHIP ADDRESS (READ)
1
0
0
ACK
0
1
1
DATA
1 AD0 1
7
ACK
START
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 23. Control Port Timing, I²C Aborted Write + Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 22, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100111x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
26
DS761F1
CS2000-CP
6.3
Memory Address Pointer
The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read
or written. Refer to the pseudocode above for implementation details.
6.3.1
Map Auto Increment
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is read or written, allowing block reads or writes of successive registers.
7. REGISTER QUICK REFERENCE
This table shows the register and bit names with their associated default values.
EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Adr
Name
01h Device ID
p 28
02h Device Ctrl
p 28
03h Device Cfg 1
p 29
04h Device Cfg 2
p 30
05h Global Cfg
p 30
06h
32-Bit
Ratio 0
09h
0Ah
32-Bit
Ratio 1
0Dh
0Eh
32-Bit
Ratio 2
11h
12h
32-Bit
Ratio 3
15h
16h Funct Cfg 1
p 31
17h Funct Cfg 2
p 32
1Eh Funct Cfg 3
p 32
DS761F1
7
6
5
4
3
2
1
Device4
Device3
Device2
Device1
Device0
Revision2
Revision1
0
0
0
0
0
x
x
Unlock
Reserved
Reserved
Reserved
Reserved
Reserved
AuxOutDis
x
x
x
0
0
0
0
RModSel2 RModSel1 RModSel0
RSel1
RSel0
AuxOutSrc1 AuxOutSrc0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
LockClk1
LockClk0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Freeze
Reserved
Reserved
0
0
0
0
0
0
0
MSB
...........................................................................................................................
MSB-8
...........................................................................................................................
LSB+15
...........................................................................................................................
LSB+7
...........................................................................................................................
MSB
...........................................................................................................................
MSB-8
...........................................................................................................................
LSB+15
...........................................................................................................................
LSB+7
...........................................................................................................................
MSB
...........................................................................................................................
MSB-8
...........................................................................................................................
LSB+15
...........................................................................................................................
LSB+7
...........................................................................................................................
MSB
...........................................................................................................................
MSB-8
...........................................................................................................................
LSB+15
...........................................................................................................................
LSB+7
...........................................................................................................................
ClkSkipEn AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved
Reserved
0
0
0
0
0
0
0
Reserved
Reserved
Reserved ClkOutUnl LFRatioCfg Reserved
Reserved
0
0
0
0
0
0
0
Reserved ClkIn_BW2 ClkIn_BW1 ClkIn_BW0 Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Revision0
x
ClkOutDis
0
EnDevCfg1
0
FracNSrc
0
EnDevCfg2
0
MSB-7
MSB-15
LSB+8
LSB
MSB-7
MSB-15
LSB+8
LSB
MSB-7
MSB-15
LSB+8
LSB
MSB-7
MSB-15
LSB+8
LSB
Reserved
0
Reserved
0
Reserved
0
27
CS2000-CP
8. REGISTER DESCRIPTIONS
In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Reserved” registers must maintain their default state to ensure proper functional operation. The default state of each
bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register
Quick Reference” on page 27.
Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins
and the EnDevCfg1 and EnDevCfg2 bits are set to 1.
8.1
Device I.D. and Revision (Address 01h)
7
Device4
8.1.1
6
Device3
5
Device2
4
Device1
3
Device0
2
Revision2
1
Revision1
0
Revision0
2
Reserved
1
AuxOutDis
0
ClkOutDis
Device Identification (Device[4:0]) - Read Only
I.D. code for the CS2000.
8.1.2
Device[4:0]
Device
00000
CS2000.
Device Revision (Revision[2:0]) - Read Only
CS2000 revision level.
REVID[2:0]
8.2
Revision Level
100
B2 and B3
110
C1
Device Control (Address 02h)
7
Unlock
8.2.1
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Unlock Indicator (Unlock) - Read Only
Indicates the lock state of the PLL.
8.2.2
Unlock
PLL Lock State
0
PLL is Locked.
1
PLL is Unlocked.
Auxiliary Output Disable (AuxOutDis)
This bit controls the output driver for the AUX_OUT pin.
AuxOutDis
28
Output Driver State
0
AUX_OUT output driver enabled.
1
AUX_OUT output driver set to high-impedance.
Application:
“Auxiliary Output” on page 23
DS761F1
CS2000-CP
8.2.3
PLL Clock Output Disable (ClkOutDis)
This bit controls the output driver for the CLK_OUT pin.
8.3
ClkOutDis
Output Driver State
0
CLK_OUT output driver enabled.
1
CLK_OUT output driver set to high-impedance.
Application:
“PLL Clock Output” on page 23
Device Configuration 1 (Address 03h)
7
RModSel2
8.3.1
6
RModSel1
5
RModSel0
4
RSel1
3
RSel0
2
AuxOutSrc1
1
AuxOutSrc0
0
EnDevCfg1
R-Mod Selection (RModSel[2:0])
Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.
8.3.2
RModSel[2:0]
R-Mod Selection
000
Left-shift R-value by 0 (x 1).
001
Left-shift R-value by 1 (x 2).
010
Left-shift R-value by 2 (x 4).
011
Left-shift R-value by 3 (x 8).
100
Right-shift R-value by 1 (÷ 2).
101
Right-shift R-value by 2 (÷ 4).
110
Right-shift R-value by 3 (÷ 8).
111
Right-shift R-value by 4 (÷ 16).
Application:
“Ratio Modifier (R-Mod)” on page 20
Ratio Selection (RSel[1:0])
Selects one of the four stored User Defined Ratios for use in the static ratio based Frequency Synthesizer
Mode.
8.3.3
RSel[1:0]
Ratio Selection
00
Ratio 0.
01
Ratio 1.
10
Ratio 2.
11
Ratio 3.
Application:
“User Defined Ratio (RUD), Frequency Synthesizer Mode” on page 19
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
Auxiliary Output Source
00
RefClk.
01
CLK_IN.
10
CLK_OUT.
11
PLL Lock Status Indicator.
Application:
“Auxiliary Output” on page 23
Note: When set to 11, AuxLckCfg sets the polarity and driver type. See “AUX PLL Lock Output Configuration (AuxLockCfg)” on page 32.
DS761F1
29
CS2000-CP
8.3.4
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
EnDevCfg1
Register State
0
Disabled.
1
Enabled.
Application:
“SPI / I²C Control Port” on page 24
Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 24.
8.4
Device Configuration 2 (Address 04h)
7
Reserved
8.4.1
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
LockClk1
1
LockClk0
0
FracNSrc
Lock Clock Ratio (LockClk[1:0])
Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.
8.4.2
LockClk[1:0]
CLK_IN Ratio Selection
00
Ratio 0.
01
Ratio 1.
10
Ratio 2.
11
Ratio 3.
Application:
Section 5.3.2 on page 19
Fractional-N Source for Frequency Synthesizer (FracNSrc)
Selects static or dynamic ratio mode when auto clock switching is disabled.
FracNSrc
8.5
Static Ratio directly from REFF for Frequency Synthesizer Mode
1
Dynamic Ratio from Digital PLL for Hybrid PLL Mode
Application:
“Fractional-N Source Selection” on page 21
Global Configuration (Address 05h)
7
Reserved
8.5.1
Fractional-N Source Selection
0
6
Reserved
5
Reserved
4
Reserved
3
Freeze
2
Reserved
1
Reserved
0
EnDevCfg2
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
30
FREEZE
Device Control and Configuration Registers
0
Register changes take effect immediately.
1
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
DS761F1
CS2000-CP
8.5.2
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
EnDevCfg2
Register State
0
Disabled.
1
Enabled.
Application:
“SPI / I²C Control Port” on page 24
Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 24.
8.6
Ratio 0 - 3 (Address 06h - 15h)
7
MSB
MSB-8
LSB+15
LSB+7
6
5
4
3
2
1
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
...................................................................................................................................................
0
MSB-7
MSB-15
LSB+8
LSB
These registers contain the User Defined Ratios as shown in the “Register Quick Reference” section on
page 27. Each group of 4 registers forms a single 32-bit ratio value as shown above. See “Output to Input
Frequency Ratio Configuration” on page 19 and “Calculating the User Defined Ratio” on page 34 for more
details.
8.7
Function Configuration 1 (Address 16h)
7
ClkSkipEn
8.7.1
6
AuxLockCfg
5
Reserved
4
RefClkDiv1
3
RefClkDiv0
2
Reserved
1
Reserved
0
Reserved
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
ClkSkipEn
Disabled.
1
Enabled.
Application:
“CLK_IN Skipping Mode” on page 15
Note:
DS761F1
PLL Clock Skipping Mode
0
fCLK_IN must be < 80 kHz and re-applied within 20 ms to use this feature.
31
CS2000-CP
8.7.2
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg
AUX_OUT Driver Configuration
0
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application:
“Auxiliary Output” on page 23
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. Therefore, the pin polarity is defined relative to the unlock condition.
8.7.3
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
8.8
RefClkDiv[1:0]
Reference Clock Input Divider
REF_CLK Frequency Range
00
÷ 4.
32 MHz to 56 MHz (50 MHz with XTI)
01
÷ 2.
16 MHz to 28 MHz
10
÷ 1.
8 MHz to 14 MHz
11
Reserved.
Application:
“Internal Timing Reference Clock Divider” on page 14
Function Configuration 2 (Address 17h)
7
Reserved
8.8.1
6
Reserved
5
Reserved
4
ClkOutUnl
3
LFRatioCfg
2
Reserved
1
Reserved
0
Reserved
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
8.8.2
ClkOutUnl
Clock Output Enable Status
0
Clock outputs are driven ‘low’ when PLL is unlocked.
1
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application:
“PLL Clock Output” on page 23
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based
Hybrid PLL Mode is selected (either manually or automatically, see section 5.3.5 on page 21).
LFRatioCfg
Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN
0
20.12 - High Multiplier.
1
12.20 - High Accuracy.
Application:
“User Defined Ratio (RUD), Hybrid PLL Mode” on page 19
Note: When the static ratio based Frequency Synthesizer Mode is selected (either manually or automatically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value,
regardless of the state of this bit.
32
DS761F1
CS2000-CP
8.9
Function Configuration 3 (Address 1Eh)
7
Reserved
8.9.1
6
ClkIn_BW2
5
ClkIn_BW1
4
ClkIn_BW0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0]
Minimum Loop Bandwidth
000
1 Hz
001
2 Hz
010
4 Hz
011
8 Hz
100
16 Hz
101
32 Hz
110
64 Hz
111
128 Hz
Application:
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 17
Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set
prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to
initiate the setting change). In production systems these bits should be configured with the desired values
prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock.
DS761F1
33
CS2000-CP
9. CALCULATING THE USER DEFINED RATIO
Note:
The software for use with the evaluation kit has built in tools to aid in calculating and converting the User
Defined Ratio. This section is for those who are not interested in the software or who are developing their
systems without the aid of the evaluation kit.
Most calculators do not interpret the fixed point binary representation which the CS2000 uses to define the output
to input clock ratio (see Section 5.3.1 on page 19); However, with a simple conversion we can use these tools to
generate a binary or hex value which can be written to the Ratio0-3 registers.
9.1
High Resolution 12.20 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN or RefClk). Then multiply the desired ratio by the scaling factor of 220
to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 2.
Scaled Decimal
Representation =
(output clock/input clock) • 220
Hex Representation of
Binary RUD
12.288 MHz/10 MHz=1.2288
1288490
00 13 A9 2A
11.2896 MHz/44.1 kHz=256
268435456
10 00 00 00
Desired Output to Input Clock Ratio
(output clock/input clock)
Table 2. Example 12.20 R-Values
9.2
High Multiplication 20.12 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 212 to get the
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in Table 3.
Desired Output to Input Clock Ratio
(output clock/input clock)
Scaled Decimal
Representation =
(output clock/input clock) • 212
Hex Representation of
Binary RUD
12.288 MHz/60 Hz=204,800
838860800
32 00 00 00
11.2896 MHz/59.97 Hz =188254.127...
771088904
2D F5 E2 08
Table 3. Example 20.12 R-Values
34
DS761F1
CS2000-CP
10.PACKAGE DIMENSIONS
10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1)
N
D
E11
c
E
A2
A
∝
e
b
A1
SIDE VIEW
1 2 3
END VIEW
L
SEATING
PLANE
L1
TOP VIEW
DIM
MIN
INCHES
NOM
A
A1
A2
b
c
D
E
E1
e
L
L1
-0
0.0295
0.0059
0.0031
----0.0157
--
-----0.1181 BSC
0.1929 BSC
0.1181 BSC
0.0197 BSC
0.0236
0.0374 REF
MAX
0.0433
0.0059
0.0374
0.0118
0.0091
----0.0315
--
MIN
MILLIMETERS
NOM
NOTE
MAX
-0
0.75
0.15
0.08
----0.40
--
-----3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
0.95 REF
1.10
0.15
0.95
0.30
0.23
----0.80
--
4, 5
2
3
Notes: 1. Reference document: JEDEC MO-187
2. D does not include mold flash or protrusions which is 0.15 mm max. per side.
3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.
4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
5. Exceptions to JEDEC dimension.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
DS761F1
JEDEC 2-Layer
JEDEC 4-Layer
Symbol
Min
Typ
Max
Units
θJA
θJA
-
170
100
-
°C/W
°C/W
35
CS2000-CP
11.ORDERING INFORMATION
Product
Description
Package
Pb-Free
CS2000-CP
Clocking Device
10L-MSOP
Yes
CS2000-CP
Clocking Device
10L-MSOP
Yes
CDK2000
Evaluation Platform
-
Yes
Grade
Temp Range Container
Commercial
-
Order#
-10° to +70°C
Rail
CS2000CP-CZZ
-10° to +70°C
Tape and
Reel
CS2000CP-CZZR
-
-
CDK2000-CLK
12.REFERENCES
1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements Jitter performance specifications,” May 2007.
2. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998.
http://www.semiconductors.philips.com
13.REVISION HISTORY
Release
F1
Changes
Updated Period Jitter specification in “AC Electrical Characteristics” on page 8.
Updated Crystal and Ref Clock Frequency specifications in “AC Electrical Characteristics” on page 8.
Added “PLL Performance Plots” section on page 9.
Updated “Internal Timing Reference Clock Divider” on page 14 and added Figure 11 on page 14.
Updated use conditions for “CLK_IN Skipping Mode” section on page 15 and page 31.
Updated Figure 13 on page 16.
Removed FsDetect and Auto R-Mod features per ER758rev2.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
36
DS761F1