FUJITSU SEMICONDUCTOR DATA SHEET DS06-20208-3E Semicustom CMOS Standard cell array CS91 Series ■ DESCRIPTION The CS91 series 0.11 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16 ps, resulting in both integration and speed about three times higher than conventional products. ■ FEATURES : 0.11 µm silicon-gate CMOS, 5- to 8-layer wiring (Copper is used as wire material.) , Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity) Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip. Supply voltage : +1.2 V ± 0.1 V (standard specification) Junction temperature range : −40 °C to +125 °C Gate delay time : tpd = 16 ps (1.2 V, inverter, F/O = 1) Gate power consumption : Pd = 6.6 nW/MHz/BC (1.2 V, inverter, F/O = 1) Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for transmission Special interfaces* : P-CML, LVDS, PCI, SSTL, HSTL, T-LVTTL, and others. Buffer cell dedicated to crystal oscillator IP macros* : CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others. Compiled cells (RAM/ROM/multiplier, and others.) Uses industry standard tools and supports the optimum tools for the application Short-term development using a physical prototyping tool Hierarchical design environment for supporting large-scale circuits Support for SIGNAL INTEGRITY, EMI noise reduction Support for High resolution RC extraction base delay calculation environment Support for optimization environment of power supply wire (Continued) • Technology • • • • • • • • • • • • • • • • Copyright©2002-2006 FUJITSU LIMITED All rights reserved CS91 Series (Continued) • Support for static timing sign off • Support for memory (RAM/ROM) BIST • Support for boundary SCAN • Support for LOGIC BIST • A variety of package options* : FCBGA (2116 pin Max) , EBGA, FBGA, and others. * : Including items under development. ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 400 types) • • • • • • • • • • Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop ENOR AND-OR • • • • • • • • • Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND Inverter OR Selector EOR Others 2. IP macros CPU/DSP ARM9, ARM7TDMI, Communications DSP, DSP for AV Ultra high speed I/F macros 622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps Interface macros PCI, IEEE1394, USB, IrDA, etc. Multimedia processing macros JPEG, MPEG, etc. Mixed signal macros ADC, DAC, OPAMP, etc. Compiled macros RAM, ROM, multiplier, adder, multiplier-accumulator, etc. PLL Analog PLL, digital PLL 3. Special I/O interface macros • T-LVTTL • LVDS 2 • SSTL • PCI • HSTL • USB • P-CML CS91 Series ■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS91 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.) 1. Clock synchronous single-port RAM (1 address : 1 RW) Column type Memory capacity Word range Bit range Unit 4 32 to 128 K 16 to 1 K 2 to 128 bit 16 2176 to 288 K 1088 to 8 K 2 to 36 bit 2. Clock synchronous dual-port RAM (2 addresses : 2 RW) Column type Memory capacity Word range Bit range Unit 4 32 to 288 K 16 to 2 K 2 to 144 bit 16 128 to 288 K 64 to 8 K 2 to 36 bit 3. Clock synchronous ROM Column type Memory capacity Word range Bit range Unit 16 256 to 1 M 128 to 8 K 2 to 128 bit 64 1024 to 1 M 512 to 32 K 2 to 32 bit 4. High-capacity memory type of clock synchronous single port RAM (1 address : 1 RW) Column type Memory capacity Word range Bit range Unit 32 16 K to 4 M 8 K to 32 K 2 to 128 bit 3 CS91 Series ■ ABSOLUTE MAXIMUM RATINGS (VSS = 0 V) Parameter Power supply voltage Input voltage*1 Output voltage Storage temperature Output current*2 Symbol VDD VI VO TST IO Application Rating Unit Min Max VDDI (Internal) − 0.5 + 1.8 V VDDE (External 2.5 V) − 0.5 + 3.6 V VDDE (External 3.3 V) − 0.5 + 4.0 V 1.2 V − 0.5 VDDI + 0.5 ( ≤ 1.8 V) V 2.5 V − 0.5 VDDE + 0.5 ( ≤ 3.6 V) V 3.3 V − 0.5 VDDE + 0.5 ( ≤ 4.0 V) V 1.2 V − 0.5 VDDI + 0.5 ( ≤ 1.8 V) V 2.5 V − 0.5 VDDE + 0.5 ( ≤ 3.6 V) V 3.3 V − 0.5 VDDE + 0.5 ( ≤ 4.0 V) V Plastic package −55 +125 °C L type simultaneous switching noise : minimum, delay : long ⎯ ± 25 mA M type simultaneous switching noise : small, delay : middle ⎯ ± 25 mA H type simultaneous switching noise : middle, delay : short ⎯ ± 25 mA *1 : Values are determined separately for LVDS, etc. *2 : Maximum output current which can be supplied constantly. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 4 CS91 Series ■ RECOMMENDED OPERATING CONDITIONS • Single power supply (VDD = 1.2 V ± 0.1 V) Parameter (VSS = 0 V) Symbol Value Min Typ Max Unit Power supply voltage VDD 1.1 1.2 1.3 V “H” level input voltage VIH VDD × 0.7 ⎯ VDD + 0.3 V “L” level input voltage VIL −0.3 ⎯ VDD × 0.3 V Junction temperature Tj −40 ⎯ +125 °C • Dual power supply (VDDE = 3.3 V ± 0.3 V, VDDI = 1.2 V ± 0.1 V) Parameter Power supply voltage “H” level input voltage “L” level input voltage Symbol (VSS = 0 V) Value Min Typ Max 3.3 V supply voltage VDDE 3.0 3.3 3.6 V 1.2 V supply voltage VDDI 1.1 1.2 1.3 V 2.0 ⎯ VDDE + 0.3 V VDDI × 0.7 ⎯ VDDI + 0.3 V −0.3 ⎯ +0.8 V −0.3 ⎯ VDDI × 0.3 V −40 ⎯ +125 °C 3.3 V CMOS level 1.2 V CMOS level 3.3 V CMOS level 1.2 V CMOS level Junction temperature VIH VIL Tj • Dual power supply (VDDE = 2.5 V ± 0.2 V, VDDI = 1.2 V ± 0.1 V) Parameter Power supply voltage “H” level input voltage “L” level input voltage Junction temperature Unit Symbol (VSS = 0 V) Value Min Typ Max Unit 2.5 V supply voltage VDDE 2.3 2.5 2.7 V 1.2 V supply voltage VDDI 1.1 1.2 1.3 V 1.7 ⎯ VDDE + 0.3 V VDDI × 0.7 ⎯ VDDI + 0.3 V −0.3 ⎯ +0.7 V −0.3 ⎯ VDDI × 0.3 V −40 ⎯ +125 °C 2.5 V CMOS level 1.2 V CMOS level 2.5 V CMOS level 1.2 V CMOS level VIH VIL Tj WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 CS91 Series ■ ELECTRICAL CHARACTERISTICS • Single power supply : VDD = 1.2 V (VDD = 1.2 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Condition “H” level output voltage VOH IOH = −100 µA “L” level output voltage VOL IOL = 100 µA Input leakage current* IL Pull-up/pull-down resistance RP *: ⎯ Pull-up : VIL = 0 Pull-down : VIH = VDD Value Unit Min Typ Max VDD − 0.2 ⎯ VDD V 0 ⎯ 0.2 V ⎯ ⎯ ±10 µA ⎯ 12 ⎯ kΩ The input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. • Dual power supply : VDDE = 3.3 V, VDDI = 1.2 V (VDDE = 3.3 V ± 0.3 V, VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter “H” level output voltage “L” level output voltage Input leakage current* Pull-up/pull-down resistance *: 6 Symbol Condition Value Min Typ Max Unit VOH4 IOH = −100 µA VDDE − 0.2 ⎯ VDDE V VOH2 IOH = −100 µA VDDI − 0.2 ⎯ VDDI V VOL4 IOL = 100 µA 0 ⎯ 0.2 V VOL2 IOL = 100 µA 0 ⎯ 0.2 V ⎯ ⎯ ±10 µA 3.3 V Pull-up : VI = 0 Pull-down : VI = VDDE 15 33 70 kΩ 1.2 V Pull-up : VI = 0 Pull-down : VI = VDDI ⎯ 12 ⎯ kΩ IL RP ⎯ The input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. CS91 Series • Dual power supply : VDDE = +2.5 V, VDDI = +1.2 V (VDDE = 2.5 V ± 0.2 V, VDDI = 1.2 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol “H” level output voltage “L” level output voltage Min Typ Max Unit VOH3 IOH = −100 µA VDDE − 0.2 ⎯ VDDE V VOH2 IOH = −100 µA VDDI − 0.2 ⎯ VDDI V VOL3 IOL = 100 µA 0 ⎯ 0.2 V VOL2 IOL = 100 µA 0 ⎯ 0.2 V ⎯ ⎯ ±10 µA 2.5 V Pull-up : VI = 0 Pull-down : VI = VDDE ⎯ 25 ⎯ kΩ 1.2 V Pull-up : VI = 0 Pull-down : VI = VDDI ⎯ 12 ⎯ kΩ Input leakage current* ⎯ IL Pull-up/pull-down resistance *: Value Condition RP The input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. ■ AC CHARACTERISTICS Parameter Delay time Rating Symbol tpd*1 Min Typ Max typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 Unit ns *1 : Delay time = Propagation delay time, Enable time, Disable time *2 : “typ” is calculated from the cell specification. *3 : Measurement conditions Measurement condition tmin ttyp tmax VDD = 1.2 V ± 0.1 V, VSS = 0 V, T j = −40 °C to +125 °C 0.65 1.00 1.66 Note : Reference values. The values according to the cell. 7 CS91 Series ■ INPUT/OUTPUT PIN CAPACITANCE (f = 1 MHz, VDD = VDI = 0 V, Tj = +25 °C) Parameter Symbol Value Unit CIN 16 Max pF Output pin COUT 16 Max pF Input/output pin CI/O 16 Max pF Input pin Note : Capacitance values according to the package and the location of the pin. ■ DESIGN METHOD Fujitsu’s Reference Design Flow provides the following functions that shorten the development time of large scale and high quality LSIs. • High reliability design estimation in the early stage of physical design realized by physical prototyping. • Layout synthesis with optimized timing realized by physical synthesis tools. • High accuracy design environment considering drop in power supply voltage, signal noise, delay penalty, and crosstalk. • I/O design environment (power line design, assignment and selection of I/Os, package selection) considering noise. ■ PACKAGES A variety of package types Development of chips with narrow-pitch solder bump technology and high-pin count packages enables users to respond to the high-pin count, high-speed requirements of the network market. A variety of packages from existing series are also available for smooth transition from previously developed models. Contact your FUJITSU representative for availability dates. FCBGA package EBGA package FBGA package QFP package 8 : maximum 2116 pins : maximum 672 pins : maximum 304 pins : maximum 304 pins CS91 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0609