CXA2016S Sync Identification for CRT Display Description The CXA2016S is used for sync signal identification and waveform shaping in the CRT computers display for multi-scan system. There are three types of sync input signals for identification: separate sync, composite sync, and sync on video signals. 22 pin SDIP (Plastic) Features • Power save function available (5 V power supply) • Clamp pulse output position selectable among sync interval, back porch interval, and AUTO. • Polarity information of sync signals is output. • Polarity and amplitude of input signals: Absolute Maximum Ratings (Ta=25°C) • Supply voltage VCC 12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 962 mW Polarity Amplitude (Vp-p) V. separate sync: Positive/Negative 1 to 5 H. separate sync: Positive/Negative 1 to 5 Composite sync: Positive/Negative 1 to 5 Sync on video: Sync signals part of Negative 0.2 to 0.4 Video part 0 to 1.4 Operating Conditions Supply voltage VCC 5 ± 0.25 V Applications CRT display monitor Pin Configuration (Top View) 1 VS IN VCC 22 2 PVC VD 21 3 EVC VSS IN 20 4 CS IN 5 6 7 8 PHC EHC Video IN HD SEL VS IN 1 PV 17 PH 16 CS IN 4 PHC 5 EHC 6 Video IN 7 PVC EVC 2 3 Polarity Check V. Ramp Generator Exist Check 21 VD 8 HD SEL VSS OUT 19 HD 18 Polarity Check 18 HD Exist Check Logic PV 17 9 ISC 13 CLP OUT Clamp Pulse Generator PH 16 14 CLP OUT CLP SEL 15 9 ISC CLP OUT 14 10 ISJ CLP OUT 13 11 GND Block Diagram Sync Sep Sync Check 15 CLP SEL Bias Level Control VSS REF 12 10 19 ISJ VSS OUT 20 12 VSS IN VSS REF 11 22 GND VCC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E95422B78-TE CXA2016S Pin Description Pin No Symbol (Ta=25 °C, VCC=5 V) Pin voltage Equivalent circuit Description VCC 1k 1 VS IN 2.6 V 1 V. separate sync (positive/negative polarity) as capacitor input. Amplitude is 1 to 5 Vp-p. 100 GND VCC 1k 96k 2 PVC — 2 1k 8k GND This pin connects a 0.22 µF integrating capacitor for the vertical signal polarity check circuit to GND. When connecting the capacity at positive polarity, it is 2.9 V and at negative polarity, 120 mV. VCC 3 EVC — 3 200 200 200 1k V. ramp waveforms generation part of vertical signal exist check circuit. Generates ramp waveforms synchronously with the input signal cycle and connects 0.22 µF to GND. GND VCC Inputs composite sync (positive/negative polarity) and H. separate sync (positive/negative polarity) as capacitor input. Amplitude is 1 to 5 Vp-p. 1k 4 CS IN 2.6 V 4 100 GND VCC 96k 5 PHC — 5 1k 8k GND VCC 1k 6 EHC — 1k 100 6 1k GND —2— This pin connects a 0.1 µF integrating capacitor for the horizontal signal polarity check circuit to GND. When connecting the capacity at positive polarity, it is 2.6 V and at negative polarity, 350 mV. A 33 kΩ resistance and a nearly peak hold circuit for 0.22 µF capacitor are connected to this pin for input signal exist check at CS IN input pin. When a signal is input at CS IN pin, a nearly peak hold is executed at 2.1 V to 2.7 V, a comparison is made with the 1.4 V reference voltage, and input signal exist is identified. CXA2016S Pin No Symbol Pin voltage Equivalent circuit Description VCC 2k 7 Video IN — Inputs sync on video (sync at negative polarity). Connects in series a 1 µF capacitor and a 270 Ω resistance to input signals. 7 GND VCC 8 HD SEL — 8 1k GND VCC 2k 9 ISC 1k 1.2 V 9 100 50k GND VCC 4k 10 ISJ 1k 1.2 V 10 100 50k GND 11 GND — 0V Selects output processing of HD (H. Drive Pulse) at a VD interval. Input at TTL level. When Low level is selected, HD is not output at a VD interval. When High level is selected, HD is output at the VD interval. Resistance connecting pin for reference current source of clamp pulse output circuit, and connects 12 kΩ resistance to GND. When a 12 kΩ resistance is connected, a 100 µA current flows through this pin (pulse width is approximately 300 ns). Clamp pulse output pulse width is varied by changing the value of the resistance. ∗Use a metal film resistor with an accuracy of ±1 % Resistance connecting pin for reference current source and connecting 12 kΩ resistance to GND. When the resistance is connected, a 100 µA current flows through this pin. ∗Use a metal film resistor with an accuracy of ±1 % GND pin. VCC 12k 12 VSS REF Reference pin for V. sync separator of composite sync and video sync. 3.125 V 12 1k 20k GND —3— CXA2016S Pin No Symbol Pin voltage CLP OUT — Equivalent circuit Description VCC 13 Clamp pulse output; Open collectortype pin at positive polarity. 500 13 Clamp pulse output; Open collectortype pin at negative polarity. 40k 14 CLP OUT — 7k GND VCC 30k 20k 15 CLP SEL — 15 1k 43k GND Selects output position of a clamp pulse. Input at TTL level. When Low level is selected, a clamp pulse is output at a back porch interval. When High level is selected, clamp pulse is output at a sync interval. See the Description of Operation for Input/Output Matrix. VCC Output polarity information of horizontal and vertical sync signals. See the Description of Operation for Input/Output Matrix. 20k 16 17 PH PV — 16 20k GND VCC 333 18 HD — 6k 18 HD (H. Drive Pulse) output; Push-pull type pin at positive polarity. 6k 6k GND VCC 200 19 VSS OUT — 19 5k Composite sync or sync signal separated from video sync is output. Output is at positive polarity. 2.5k 17.5k GND VCC 20 VSS IN — Input for V. sync separator comparator. Integrates the output at Pin 19 and inputs it. 20 1k GND —4— CXA2016S Pin No Symbol Pin voltage Equivalent circuit Description VCC 10k 21 VD — 21 VD (V. Drive Pulse) output pin. Output is at positive polarity. 10k 10k GND 22 VCC 5V Power supply pin. — —5— CXA2016S Electrical Characteristics No. 1 Item VD output voltage Symbol EVD (Ta=25 °C, VCC=5 V. See the Electrical Characteristics Measurement Circuit.) Measurement contents Measure VD output peak value during V. separate sync input. Input signal A. (tw=60 µs) Measurement point Min. 2 HD output voltage EHD 260 305 380 ns 260 310 380 ns HD (Pin 18) — 75 100 ns CLAMP (Pin 13) — 5.0 30 HD (Pin 18) CLAMP (Pin 13) 3 4 5 6 Clamp pulse output voltage Clamp pulse output pulse width HD delay Clamp pulse delay ECP tC thd tcd1 PN 7 Polarity identification output voltage PP 8 Current consumption ICC Measure clamp pulse output pulse width during composite sync input. Input signal B. (tw=1 µs) Measure delay difference between CS and HD during composite sync input. Or the time from CS (positive polarity) rise time (50 %) to HD output rise time (50 %). Input signal D. Measure delay difference between HD and clamp pulse during composite sync input. Or the time from HD output fall time (50 %) to clamp pulse output rise time∗1 (50 %). Input signal B. Sync signal polarity information is output. Measure high level voltage. (No load) Sync signal polarity information is output. Measure low level voltage. (No load) VCC=5 V. Measure current consumption during no signal input. ∗1 CLAMP is for the fall time. —6— Unit — VD (Pin 21) 4.3 3.3 — Measure clamp pulse output peak value during composite sync input. Input signal B. (tw=1 µs) Max. High level 4.9 Low level 0.1 High level 4.2 Low level 0.3 High level 4.9 Low level 0.3 High level 4.9 Low level 0.4 — Measure HD output peak value during sync on video input. Input signal C. (tw=1 µs) Typ. 4.3 — CLAMP (Pin 14) CLAMP (Pin 13) CLAMP (Pin 14) 4.3 — V 0.4 — V 0.5 — V 0.8 — V 0.9 ns CLAMP (Pin 14) — 5.0 30 PH, PV (Pins 16 and 17) 4.3 — — V PH, PV (Pins 16 and 17) — — 0.4 V VCC (Pin 22) — 26.5 45 mA CXA2016S Types of Signal Source Signal A Item V. SYNC IN (Pin 1) Composite SYNC IN (Pin 4) fv=40 Hz tWV=60 µs 1 1WV Negative logic 1 Vp-p fv=40 Hz tWV=60 µs V 1WV B Video IN (Pin 7) 3, 4, 6 H 1WH Negative logic 1 Vp-p fH=50 kHz tWH=1 µs Negative logic 1 Vp-p V 0.7V 10H 60µs C 2 0.2V 3H fV=40 Hz tWV=60 µs 15µs H 0.7V 3µs 1µs D 5 fH=50 kHz tWH=1 µs Positive logic 1 Vp-p —7— 0.2V fH=50 kHz tWH=1 µs CXA2016S Electrical Characteristics Measurement Circuit HS Video or Sync CS VS 1 75 VS IN VCC 22 0.01µ 2.2µ 2 PVC 1µ 5V 10µ VD 21 1k 0.22µ VD 3 EVC VSS IN 20 0.22µ 4 CS IN VSS OUT 19 2.2k 1µ 75 3300p 5 PHC HD 18 HD 6 EHC PV 17 PV 7 Video IN PH 16 PH 8 HD SEL CLP SEL 15 0.1µ 75 33k 0.22µ 1µ 220 10k 0.1µ 12k 9 ISC CLP OUT 14 1k CLAMP 12k 10 ISJ CLP OUT 13 1k CLAMP 11 GND VSS Ref 12 0.01µ —8— CXA2016S Description of Operation Input signal • VS IN (Pin 1) fV : 40 to 200 Hz VS : 1 to 5Vp-p (positive/negative polarity) • HS IN (Pin 4) fH : 15k to 130 kHz VS : 1 to 5 Vp-p (positive/negative polarity) • CS IN (Pin 4) fH : 15 k to 130 kHz fV : 40 to 200 Hz VS : 1 to 5 Vp-p (positive/negative polarity) • Video IN (Pin 7) fH : 15 k to 130 kHz fV : 40 to 200 Hz VV : 0 to 1.4 Vp-p VS : 0.2 to 0.4 Vp-p Clamp Pulse Output • Clamp pulse (Pins 13 and 14) is output under the following conditions. Pin 13 is for open collector output and is at positive polarity. Pin 14 is for open collector output and is at negative polarity. td: Clamp pulse delays for 10 to 20 ns from HD. tw: Clamp pulse width varies depending on the value of the resistance connected to Pin 9. <Conditions> (1) When CS IN or Video IN is selected, a clamp pulse at the VD interval is not output. (2) During H./V. Separate Sync, a clamp pulse at the VD interval is also output. (3) When Pin 15 (CLP SEL) is connected to GND, a clamp pulse is output at the back porch interval. When Pin 15 (CLP SEL) is connected to VCC, a clamp pulse is output at the SYNC interval. If a capacitor is connected between this pin and GND, the output position is automatically selected. Clamp Pulse Input/Output Matrix CLP SEL GND VCC AUTO VS IN ∗ ∗ ∗ ∗ ∗ CS IN ∗ ∗ — O — [O] indicates that input SYNC exists. [—] indicates no signal (no SYNC). [ ∗ ] has no relation with input signal. —9— Video IN ∗ ∗ O — — Clamp pulse output position Back porch interval SYNC interval Back porch interval SYNC interval (Back porch interval) CXA2016S HD Select Function When HD SEL is Low, HD at the VD interval is not output. When HD SEL is High, HD at the VD interval is output. During separate sync output, HD is output regardless of HD SEL. Mode Matrix of SYNC Polarity Identification Signal VS IN (Pin 1) VS (positive polarity) VS (negative polarity) No signal CS IN (Pin 4) No signal HS (positive polarity) HS (negative polarity) No signal HS (positive polarity) HS (negative polarity) No signal COMP (positive polarity) COMP (negative polarity) PV out (Pin 17) Low Low Low High High High Low Low Low PH out (Pin 16) Low Low High Low Low High Low Low High Low level: 0 to 0.4 V, High level: VCC Input/Output Matrix VS IN O — — — O O CS IN O O — — — — Video IN ∗ ∗ O — O — Note) The corresponding sync signals are input to VSIN and Video IN. [O] indicates that input SYNC exists. [—] indicates no signal. [ ∗ ] has no relation with input signal. —10— VD OUT VS CS Video (Video) VS VS HD OUT CS CS Video (Video) Video (Video) CXA2016S Application Circuit CS Video or (G) HS VS 1 VS IN VCC 22 2 PVC VD 21 3 EVC VSS IN 20 VCC 5V 2.2µ 75 VD OUT 0.22µ 0.22µ 2.2k VSS OUT 19 4 CS IN 3300p 1µ 75 5 PHC HD 18 HD OUT 6 EHC PV 17 PV 7 Video IN PH 16 PH 8 HD SEL CLP SEL 15 0.1µ 33k 0.22µ 75 1µ 270 0.1µ 12k∗ 9 ISC CLP OUT CLP OUT 14 1k 12k∗ 10 ISJ CLP OUT CLP OUT 13 1k 11 GND VSS Ref 12 0.01µ Use metal film resistor with an accuracy of ±1% for the resistor marked ∗. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —11— CXA2016S Unit : mm + 0.1 0.05 0.25 – 22PIN SDIP (PLASTIC) + 0.4 19.2 – 0.1 7.62 + 0.3 6.4 – 0.1 12 22 0° to 15° 11 1 0.5 ± 0.1 + 0.15 0.9 – 0.1 + 0.4 3.9 – 0.1 0.51 MIN 1.778 + 0.15 3.25 – 0.2 Package Outline Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE MOLDING COMPOUND EPOXY RESIN SONY CODE SDIP-22P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP022-P-0300 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.95g JEDEC CODE —12—