CXK5V8512TM -85LLX/10LLX
65536-word × 8-bit High Speed CMOS Static RAM
For the availability of this product, please contact the sales office.
Description
The CXK5V8512TM is a high speed CMOS static
RAM organized as 65536-words by 8-bits.
A polysilicon TFT cell technology realized
extremely low stand-by current and higher data
retention stability.
Operating on a single 3.3V supply, and special
feature are low power consumption, high speed.
The CXK5V8512TM is a suitable RAM for portable
equipment with battery back up.
Features
• Extended operating temperature range:
–25 to +85°C
• Fast access time:
(Access time)
-85LLX
85ns (Max.)
-10LLX
100ns (Max.)
• Low standby current:
14µA (Max.)
• Low data retention current: 12µA (Max.)
• Single 3.3V supply:
3.3V ± 0.3V
• Low voltage data retention: 2.0V (Min.)
• Package
8mm × 20mm 32 pin TSOP package
Function
65536-word × 8-bit static RAM
32 pin TSOP (Plastic)
Block Diagram
A15
A13
A8
A11
A9
A7
A6
A5
A14
A12
Buffer
A4
A3
A10
A0
A2
A1
Buffer
Memory
Matrix
1024 × 512
VCC
GND
I/O Gate
Column
Decoder
OE
Buffer
WE
Structure
Silicon gate CMOS IC
Row
Decoder
CE1
CE2
I/O Buffer
I/O1
I/O8
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95716-PP
CXK5V8512TM
Pin Configuration (Top View)
Pin Description
Symbol
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
NC
A14
A12
A7
A6
A5
A4
1
32 OE
2
31 A10
3
30 CE1
4
5
29 I/O8
28 I/O7
6
7
27 I/O6
26 I/O5
8
25 I/O4
CXK5V8512TM
9
A0 to A15
Address input
I/O1 to I/O8
Data input output
CE1, CE2
Chip enable 1, 2 input
WE
Write enable input
OE
Output enable input
VCC
Power supply
GND
Ground
NC
No connection
24 GND
10
23 I/O3
11
22 I/O2
12
21 I/O1
13
20 A0
19 A1
14
18 A2
17 A3
15
16
Absolute Maximum Ratings
Item
(Ta = 25°C, GND = 0V)
Symbol
Rating
Unit
V
Supply voltage
VCC
Input voltage
VIN
–0.5 to +4.6
–0.5∗ to VCC + 0.5
Input and output voltage
VI/O
–0.5∗ to VCC + 0.5
V
Allowable power dissipation
PD
0.7
W
Operating temperature
Topr
–25 to +85
°C
Storage temperature
Tstg
–55 to +150
°C
Soldering temperature · time Tsolder
235 • 10
∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns.
V
°C • s
Truth Table
CE1 CE2
OE
WE
Mode
I/O pin
VCC Current
H
×
×
×
Not selected
High Z
ISB1, ISB2
×
L
×
×
Not selected
High Z
ISB1, ISB2
L
H
H
H
Output disable
High Z
ICC1, ICC2, ICC3
L
H
L
H
Read
Data out
ICC1, ICC2, ICC3
L
H
×
L
Write
Data in
ICC1, ICC2, ICC3
×: “H” or “L”
DC Recommended Operating Conditions
Item
Description
(Ta = –25 to +85°C, GND = 0V)
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
VCC
3.0
3.3
3.6
V
Input high voltage
VIH
2.2
—
VCC + 0.3
V
Input low voltage
VIL
–0.3∗
—
0.6
V
∗ VIL = –3.0V Min. for pulse width less than 50ns.
–2–
CXK5V8512TM
Electrical Characteristics
• DC Characteristics
Item
(VCC = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C)
Typ.∗
Test conditions
Min.
Max. Unit
Symbol
Input leakage current
ILI
VIN = GND to VCC
–1
—
+1
µA
Output leakage current
ILO
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = GND to VCC
–1
—
+1
µA
Operating power supply
current
ICC1
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
—
1
3
mA
Min. cycle
duty = 100%
IOUT = 0mA
85LLX
—
30
40
ICC2
10LLX
—
25
35
—
5
10
mA
ICC3
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 ≤ 0.2V
CE2 ≥ Vcc – 0.2V
VIL ≤ 0.2V
VIH ≥ Vcc – 0.2V
—
—
14
ISB1
–25 to +85°C
CE2 ≤ 0.2V
CE1 ≥ Vcc – 0.2V –25 to +70°C
or
CE2 ≥ Vcc – 0.2V
+25°C
—
—
7
—
0.24
—
ISB2
CE1 = VIH or CE2 = VIL
—
0.12
1.4
mA
Output high voltage
VOH
IOH = –2.0mA
2.4
—
—
V
Output low voltage
VOL
IOL = 2.0mA
—
—
0.4
V
Average operating current
Standby current
{
∗ VCC = 3.3V, Ta = 25°C
–3–
mA
µA
CXK5V8512TM
I/O capacitance
(Ta = 25°C, f = 1MHz)
Item
Symbol Test conditons
Min.
Typ.
Max.
Unit
Input capacitance
CIN
VIN = 0V
—
—
8
pF
I/O capacitance
CI/O
VI/O = 0V
—
—
10
pF
Note) This parameter is sampled and is not 100% tested.
AC Characteristics
• AC test conditions
(VCC = 3.3V ± 0.3V, Ta = –25 to +85°C)
Item
Conditions
Input pulse high level
VIH = 2.2V
Input pulse low level
VIL = 0.6V
Input rise time
tr = 5ns
tf = 5ns
Input fall time
Input and output reference level
Output load conditions
• Test circuit
TTL
CL
-85LLX
1.4V
CL∗ = 30pF, 1TTL
-10LLX
CL∗ = 100pF, 1TTL
∗ CL includes scope and jig capacitances.
–4–
CXK5V8512TM
• Read cycle (WE = “H”)
Item
(Vcc = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C)
Symbol
tRC
tAA
Address access time
tCO1
Chip enable access time (CE1)
tCO2
Chip enable access time (CE2)
tOE
Output enable to output valid
tOH
Output hold from address change
Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2
tOLZ
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2) tHZ1∗, tHZ2∗
tOHZ∗
Output disable to output in high Z (OE)
Read cycle time
-85LLX
-10LLX
Unit
Min.
Max.
Min.
Max.
85
—
100
—
ns
—
85
—
100
ns
—
85
—
100
ns
—
85
—
100
ns
—
40
—
50
ns
10
—
10
—
ns
10
—
10
—
ns
5
—
5
—
ns
—
35
—
40
ns
—
30
—
35
ns
∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
(Vcc = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C)
• Write cycle
Item
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
Symbol
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ∗
-85LLX
-10LLX
Unit
Min.
Max.
Min.
Max.
85
—
100
—
ns
70
—
80
—
ns
70
—
80
—
ns
35
—
40
—
ns
0
—
0
—
ns
60
—
70
—
ns
0
—
0
—
ns
5
—
5
—
ns
5
—
5
—
ns
5
—
5
—
ns
—
35
—
40
ns
∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
CXK5V8512TM
Timing Waveform
• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH
tRC
Address
tAA
tOH
Data out
Previous data valid
Data valid
• Read cycle (2) : WE = VIH
tRC
Address
tAA
CE1
tCO1
ttHZ1
HZ
tLZ1
CE2
tCO2
tLZ2
tHZ2
OE
tOE
tOHZ
tOLZ
Data out
Data valid
High impedance
–6–
CXK5V8512TM
• Write cycle (1) : WE control
tWC
Address
tWR
tAW
OE
tCW
CE1
tCW
CE2
tAS
(∗1)
tWP
WE
tDW
tDH
Data valid
Data in
tWHZ
tOW
Data out
High impedance
(∗2)
(∗2)
• Write cycle (2) : CE1 control
tWC
Address
tAW
OE
tAS
tCW
tWR1 (∗3)
CE1
tCW
CE2
tWP
WE
tDW
Data valid
Data in
Data out
High impedance
–7–
tDH
CXK5V8512TM
• Write cycle (3) : CE2 control
tWC
Address
tAW
OE
tCW
CE1
tAS
tWR1 (∗3)
tCW
CE2
tWP
WE
tDW
tDH
Data valid
Data in
Data out
High impedance
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.
∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until
the end of the write cycle.
–8–
CXK5V8512TM
Data retention waveform
• Low supply voltage data retention waveform (1) (CE1 contol)
tCDRS
Data retention mode
tR
VCC
3.0V
2.2V
VDR
CE1
CE1 ≥ VCC – 0.2V
GND
• Low supply voltage data retention waveform (2) (CE2 contol)
Data retention mode
VCC
3.0V
tCDRS
tR
CE2
VDR
0.4V
CE2 ≤ 0.2V
GND
Data Retention Characteristics
Item
Data retention voltage
Data retention current
Symbol
VDR
ICCDR1
ICCDR2
Data retention setup time tCDRS
Recovery time
(Ta = –25 to +85°C)
Test conditions
Min.
Typ.
Max.
Unit
2.0
—
3.6
V
–25 to +85°C
—
—
12
–25 to +70°C
—
—
6
+25°C
—
0.2
—
VCC = 2.0 to 3.6V
—
0.24
14
µA
Chip disable to data retention mode
0
—
—
ns
5
—
—
ms
∗
VCC = 3.0V∗
tR
∗ CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)
–9–
µA
CXK5V8512TM
Package Outline
Unit: mm
32PIN TSOP (I) (PLASTIC)
+ 0.2
1.07 – 0.1
8.0 ± 0.2
17
32
0.1
0.5 ± 0.1
20.0 ± 0.2
∗18.4 ± 0.2
0.1 ± 0.1
0° to 10°
DETAIL A
A
+ 0.08
0.2 – 0.03
1
16
+ 0.05
– 0.02
7
2
.1
0
0.08 M
0.5
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
TSOP (I) -32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
TSOP (I) 032-P-0820-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 10 –