CY22801 Universal Programmable Clock Generator (UPCG) Features General Description ■ Integrated phase-locked loop (PLL) ■ Field-programmable ■ Input frequency range: ❐ Crystal: 8 MHz to 30 MHz ❐ CLKIN: 1 MHz to 133 MHz The CY22801 is a flash-programmable clock generator that supports various applications in consumer and communications markets. The device uses the Cypress-proprietary PLL along with Spread Spectrum and VCXO technology to make it one of the most versatile clock synthesizers in the market. The device uses a Cypress-proprietary PLL to drive up to three configurable outputs in an 8-pin SOIC. ■ Low-voltage complementary metal oxide semiconductor (LVCMOS) output frequency: ❐ 1MHz to 200 MHz (commercial grade) ❐ 1MHz to 166.6 MHz (industrial grade) The CY22801 is programmed with an easy-to-use programmer dongle, the CY36800, in conjunction with the CyClocksRT™ software. This enables fast sample generation of prototype builds for user-defined frequencies. ■ Special Features: ❐ Spread Spectrum ❐ VCXO ❐ Inputs: PD or OE, FS ■ Low-jitter, high-accuracy outputs ■ 3.3 V operation ■ Commercial and industrial temperature ranges ■ 8-pin small-outline integrated circuit (SOIC) package ■ Serial interface for device configuration Logic Block Diagram XIN/CLKIN XOUT SDAT/FS0/ VCXO/OE /PD# VCXO FS2 SCLK /FS1 SDAT /FS0 /PD# VCXO REF with Logic PLL Divider 1 CLKA Switch Matrix Serial I/F with Control Logic Divider 2 CLKB/ FS1/ SCLK CLKC /FS2 OE Cypress Semiconductor Corporation Document #: 001-15571 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 28, 2011 [+] Feedback CY22801 Contents Pin Configuration ............................................................. 3 External Reference Crystal/Clock Input ......................... 4 Output Clock Frequencies............................................... 4 VCXO ................................................................................. 4 VCXO Profile ............................................................... 4 Spread Spectrum Clock Generation (SSCG) ................. 4 Spread Percentage ..................................................... 5 Modulation Frequency................................................. 5 SSON Pin .................................................................... 5 Multifunction Pins ............................................................ 5 Frequency Calculation and Register Definitions ......................................................................... 5 Default Startup Condition for the CY22801.................... 6 Frequency Calculations and Register Definitions using the Serial (I2C) Interface......................................................... 6 PLL Frequency, Q Counter [42H(6..0)] ....................... 8 PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7)] .................................................... 8 PLL Post Divider Options [0CH(7..0)], [47H(7..0)]....... 8 Charge Pump Settings [40H(2..0)] .............................. 8 Clock Output Settings: CLKSRC – Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] ....... 9 Test, Reserved, and Blank Registers.......................... 9 Application Guideline..................................................... 11 Best Practices for Best Jitter Performance................ 11 Field Programming the CY22801 .................................. 11 CyClocksRT Software .................................................... 11 CY36800 InstaClock™ Kit .............................................. 11 Possible Configuration Examples ................................ 11 Document #: 001-15571 Rev. *E Informational Graphs ..................................................... 12 Absolute Maximum Conditions..................................... 13 Recommended Operating Conditions .......................... 13 Recommended Crystal Specifications ......................... 13 Pullable Crystal Specifications for VCXO Application Only.................................................. 13 DC Electrical Specifications ..................................................... 14 AC Electrical Characteristics ........................................ 14 Test Circuit...................................................................... 15 Timing Definitions .......................................................... 16 80% .................................................................................. 16 20% .................................................................................. 16 2-wire Serial (I2C) Interface Timing............................... 17 Data Valid.................................................................. 17 Data Frame ............................................................... 17 Acknowledge Pulse ................................................... 17 Ordering Information...................................................... 19 Possible Configurations............................................. 19 Ordering Code Definitions ......................................... 19 Package Diagram............................................................ 20 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support....................... 23 Products .................................................................... 23 PSoC Solutions ......................................................... 23 Page 2 of 23 [+] Feedback CY22801 Pin Configuration Figure 1. CY22801 8-Pin SOIC 8 XOUT 7 CLKC/FS2 3 6 CLKA 4 5 CLKB/FS1/SCLK XIN/CLKIN 1 VDD 2 SDAT/FS0/ VCXO/OE/PD# VSS CY22801 Table 1. Pin Definition Name Pin Number CLKIN/XIN 1 External reference crystal input/external reference clock input Description VDD 2 3.3 V voltage supply SDAT/FS0/VCXO /OE/PD# 3 Serial interface data line/frequency select 0 / VCXO analog control voltage / Output Enable / Power-down VSS 4 Ground CLKB/FS1/SCLK 5 Clock output B/frequency select 1/serial interface clock line CLKA 6 Clock output A CLKC/FS2 7 Clock output C / frequency select 3 / VSS XOUT 8 External reference crystal output: Connect to external crystal. When the reference is an external clock signal (applied to pin 1), this pin is not used and must be left floating. Document #: 001-15571 Rev. *E Page 3 of 23 [+] Feedback CY22801 External Reference Crystal/Clock Input VCXO CY22801 can accept external reference clock input as well as crystal input. External reference clock input frequency range is from 1MHz to 133 MHz. One of the key components of the CY22801 device is the VCXO. The VCXO is used to ‘pull’ the reference crystal higher or lower to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. The input crystal oscillator of the CY22801 is an important feature because of the flexibility it provides in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, enabling maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. Input load capacitors are placed on the CY22801 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL – CBRD – CCHIP)/0.09375 pF A special pullable crystal must be used to have adequate VCXO pull range. Pullable crystal specifications are included in this datasheet. VCXO is not compatible with Spread spectrum and Serial Interface. VCXO Profile Figure 3 shows an example of a VCXO profile. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This moves the PPM from a negative to positive offset. Figure 3. VCXO Profile In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22801. 200 150 Output Clock Frequencies The CY22801 is a very flexible clock generator with up to three individual outputs, generated from an integrated PLL. See Figure 2 for details. The output of the PLL runs at high frequency and is divided down to generate the output clocks. Two programmable dividers are available for this purpose. Therefore, although the output clocks may have different frequencies, they must be related, based on the PLL frequency. It is also possible to direct the reference clock input to any of the outputs, thereby bypassing the PLL. Lastly, the reference clock may be passed through either divider. Figure 2. Basic PLL Block Diagram REF (XIN/CLKIN) /Q PFD VCO Post Divider 1N CLKA /P Post Divider 2N Crosspoint Switch Matrix CLKB CLKC Tuning [ppm] 100 50 0 -50 0 0.5 1 1.5 2 2.5 3 3.5 -100 -150 -200 VCXO input [V] Spread Spectrum Clock Generation (SSCG) Spread spectrum clock generation (SSCG) in CY22801 helps to reduce EMI found in today’s high-speed digital electronic systems. The device uses the proprietary spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the input clock. By modulating the frequency of the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with the regulatory agency electromagnetic compatibility (EMC) requirements and improve time to market without degrading system performance. Programmed spread spectrum modulation will appear same on all three clock outputs as they come from same PLL even if operating at different frequencies. Spread spectrum is not compatible with VCXO feature. Document #: 001-15571 Rev. *E Page 4 of 23 [+] Feedback CY22801 Spread Percentage Table 2. Multi Function Pin Options The percentage of spread can be programmed from ±0.25% to ±2.5% for center spread and from –0.5% to –5.0% for down spread. The granularity is 0.25%. Modulation Frequency Pin# Pin Name OE PD# 7 CLKC/FS2 N N CLK VCXO FS OUTPUT N Y Y[4] I2 C N Table 3. Possible Combinations for Multifunction Pins The default modulation frequency is 31.5 kHz. Other modulation frequencies available through configuration software are 30.1 kHz and 32.9 kHz. Pin#3 Pin#5 Pin#7 A FS0 CLKB CLKC SSON Pin B FS0 CLKB FS2 SSON pin functionality can be used to turn Spread ON and OFF in clock output. Any one of the Multifunction pins can be configured as SSON pin. C FS0 FS1 FS2 D OE/PD# CLKB CLKC E OE/PD# FS1 CLKC Multifunction Pins F OE/PD# FS1 FS2 G SDAT SCLK CLKC H VCXO CLKB CLKC There are three pins with multiple functions either as control pins or as output pins. The following are the acronyms used for the different control function pins: ■ Output enable (OE): If OE = 1, all outputs are enabled ■ Frequency select (FS0,1,2): These pins can be used to select one of the programmed clock frequencies for clock output. All of three multifunction pins support this functionality. Any of these pins can also be configured as Spread spectrum ON (SSON) pin. If SSON = 1, clock output has programmed spread; if SSON = 0, clock output does not have spread. ■ Power-down: active low (PD#): If PD# = 0, all outputs are tristated and the device enters in the low-power state ■ ■ Possible Combinations Frequency Calculation and Register Definitions The CY22801 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, and the post divider, which can be a fixed or calculated value. There are three formulas to determine the final output frequency of a CY22801 based design: ■ CLK = ((REF x P)/Q) / Post divider Voltage controlled crystal oscillator (VCXO): Analog voltage on this pin controls the output frequency of oscillator ■ CLK = REF / Post divider ■ CLK = REF. Serial interface clock line (SCLK) and serial interface data line (SDAT): These pins are for serial interface and are compatible with I2C. The basic PLL block diagram is shown in Figure 4. Each of the three clock outputs on the CY22801 has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups. The post divider options can be applied to the calculated VCO frequency ((REF*P)/Q) or to the REF directly. Each of these three multi-function pins supports selected functions mentioned in Table 2. One of the supported functions can be programmed on the pin at a time. Table 2. Multi Function Pin Options Pin# Pin Name OE PD# 3 SDAT/FS0 /VCXO/OE /PD# Y Y Y[1] 5 CLKB/FS1/ SCLK N N N CLK OUTPUT I2 C Y[2] N[3] SDAT Y Y SCLK VCXO FS In addition to the six post divider output options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix. [1] Notes 1. VCXO and SSON functions as well as VCXO and Serial Interface functions are not compatible. 2. ‘Y’ means pin supports this function. 3. ‘N’ means pin does not support this function. 4. Do not use this pin as Reference Clock Output. Document #: 001-15571 Rev. *E Page 5 of 23 [+] Feedback CY22801 Figure 4. Basic Block Diagram of CY22801 PLL CLKSRC Crosspoint Divider Bank 1 Switch Matrix DIV1N[0CH] DIV1SRC[0CH] /DIV1N Qtotal REF (Q+2) PFD VCO Ptotal (2(PB+4)+PO) /2 DIV1CLK [42H] [45H] CLKA [44H, 45H] CLKB [45H, 46H] CLKC /3 Divider Bank 2 /DIV2N [40H, 41H, 42H] DIV2CLK /4 /2 DIV2SRC[47H] DIV1N[47H] CLKOE[09H] Default Startup Condition for the CY22801 The default (programmed) condition of the device is generally set by the distributor who programs the device using a customer specific JEDEC file produced by CyClocksRT™. Parts shipped from the factory are blank and unprogrammed. In this condition, all bits are set to 0, all outputs are three-stated, and the crystal oscillator circuit is active. While you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use CyClocksRT to produce the required register setting file. The serial interface address of the CY22801 is 69H. If there is a conflict with any other devices in your system, then this can also be changed using CyClocksRT. Frequency Calculations and Register Definitions using the Serial (I2C) Interface The CY22801 provides an industry standard serial interface for volatile, in-system programming of unique frequencies and options. Serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. The I2C Interface provides volatile programming. This means when the target system is powered down, the CY22801 reverts to its pre-I2C state, as defined above (programmed or unprogrammed). When the system is powered back up again, the I2C registers must be reconfigured again. Table 4 lists the I2C registers and their definitions. Specific register definitions and their allowable values are listed as follows. Reference Frequency The REF can be a crystal or a driven frequency (CLKIN). For crystals, the frequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between 1 MHz and 133 MHz. Programmable Crystal Input Oscillator Gain Settings The Input crystal oscillator gain (XDRV) is controlled by two bits in register 12H and are set according to Table 5 on page 7. The parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (ESR, available from the manufacturer), and the CapLoad setting during crystal startup. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 5 on page 7. All other bits in the register are reserved and should be programmed as shown in Table 6 on page 7. FTAAddrSrc[1:0] bits set Frequency tuning array address source. This will be set by CyClockRT software based on selected configuration. Using an External Clock as the Reference Input The CY22801 also accepts an external clock as reference, with speeds up to 133 MHz. With an external clock, the XDRV (register 12H) bits must be set according to Table 7 on page 7. All programmable registers in the CY22801 are addressed with eight bits and contain eight bits of data. The CY22801 is a slave device with an address of 1101001 (69H). Document #: 001-15571 Rev. *E Page 6 of 23 [+] Feedback CY22801 Table 4. Summary Table – CY22801 Programmable Registers Register Description 09H CLKOE control OCH DIV1SRC mux and DIV1N divider 12H D7 D6 D5 D4 D3 D2 D1 D0 0 0 CLKC CLKA 0 CLKB 0 0 DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) Input crystal oscillator drive control FTAAddrSrc[1] FTAAddrSrc[0] XCapSrc XDRV(1) XDRV(0) 0 0 0 13H Input load capacitor control CapLoad (7) CapLoad (6) CapLoad (5) CapLoad (4) CapLoad (3) CapLoad (2) CapLoad (1) CapLoad (0) 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) 41H Charge pump and PB counter PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) 42H PO counter, Q counter PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) 44H Crosspoint switch matrix control 1 1 1 1 1 1 45H CLKSRC0 for CLKB 1 1 1 46H CLKSRC1 CLKSRC0 for CLKC for CLKC 1 1 1 1 1 1 DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) 47H DIV2SRC mux and DIV2N divider DIV2SRC DIV2N(6) CLKSRC2 CLKSRC1 for CLKB for CLKB CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 for CLKA for CLKA for CLKA for CLKC Table 5. Programmable Crystal Input Oscillator Gain Settings Cap Register Settings 00H – 80H 80H – C0H C0H – FFH Effective Load Capacitance (CapLoad) 6 pF to 12 pF 12 pF to 18 pF 18 pF to 30 pF 30 Ω 60 Ω 30 Ω 60 Ω 30 Ω 60 Ω 8 to 15 MHz 00 01 01 10 01 10 15 to 20 MHz 01 10 01 10 10 10 Crystal ESR Crystal input frequency 20 to 25 MHz 01 10 10 10 10 11 25 to 30 MHz 10 10 10 11 11 N/A Table 6. Crystal Oscillator Gain Bit Locations and Values Address D7 D6 D5 D4 D3 D2 D1 D0 12H 0 0 1 XDRV(1) XDRV(0) 0 0 0 Table 7. Programmable External Reference Input Oscillator Drive Settings Reference Frequency Drive Setting Document #: 001-15571 Rev. *E 1 to 25 MHz 25 to 50 MHz 50 to 90 MHz 90 to 133 MHz 00 01 10 11 Page 7 of 23 [+] Feedback CY22801 Input Load Capacitors XCapSrc bit in 12H register selects the source of Input load capacitance. This will be set by CyClockRT software based on selected configuration. Input load capacitors allow you to set the load capacitance of the CY22801 to match the input load capacitance from a crystal. The value of the input load capacitors is determined by 8 bits in a programmable register [13H]. Total load capacitance is determined by the formula: CapLoad = (CL– CBRD – CCHIP)/0.09375 pF where: ■ CL = specified load capacitance of your crystal. ■ CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyClocksRT, this value defaults to 2 pF. ■ CCHIP = 6 pF. ■ 0.09375 pF = the step resolution available due to the 8-bit register. In CyclocksRT, only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula given earlier is used to calculate a new CapLoad value and programmed into register 13H. In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22801. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 0. See Table 8 on page 9 for CapLoad bit locations and values. The input load capacitors are placed on the CY22801 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when nonlinear load capacitance is affected by load, bias, supply, and temperature changes. PLL Frequency, Q Counter [42H(6..0)] The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7 bit divider with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: Qtotal = Q + 2 The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in the table. Stable operation of the CY22801 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 9 on page 9. PLL Frequency, P Counter [40H(1..0)], [41H(7..0)], [42H(7)] The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings. The three MSBs of register 40H are preset and reserved and cannot be changed. PO is a single bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining seven bits of 42H are used to define the Q counter, as shown in Table 9. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Stable operation of the CY22150 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. PLL Post Divider Options [0CH(7..0)], [47H(7..0)] The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are two select muxes (DIV1SRC and DIV2SRC) and two divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signal passing through DIV1SRC and DIV2SRC is referred to as DIV1CLK and DIV2CLK, respectively. The divider banks have four unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the two divider banks. The minimum value of DIVxN is 4. The maximum value of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. DIV1SRC is a single bit variable, controlled by register 0CH. The remaining seven bits of register 0CH determine the value of post divider DIV1N. DIV2SRC is a single bit variable, controlled by register 47H. The remaining seven bits of register 47H determine the value of post divider DIV2N. Register 0CH and 47H are defined in Table 10. Charge Pump Settings [40H(2..0)] The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and are dependent on internal variable PB (see “PLL Frequency, P Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 11 on page 9 summarizes the proper charge pump settings, based on Ptotal. See Table 12 on page 9 for register 40H bit locations and values. Document #: 001-15571 Rev. *E Page 8 of 23 [+] Feedback CY22801 Table 8. Input Load Capacitor Register Bit Settings Address D7 D6 D5 D4 D3 D2 D1 D0 13H CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0) Table 9. P Counter and Q Counter Register Definition Address D7 D6 D5 D4 D3 D2 D1 D0 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) 41H PB(7) PB(6) PB(5) PB(4) PB(3) PB(2) PB(1) PB(0) 42H PO Q(6) Q(5) Q(4) Q(3) Q(2) Q(1) Q(0) Table 10. PLL Post Divider Options Address D7 D6 D5 D4 D3 D2 D1 D0 0CH DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 47H DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) Table 11. Charge Pump Settings Charge Pump Setting – Pump(2..0) Calculated Ptotal 000 16 – 44 001 45 – 479 010 480 – 639 011 640 – 799 100 800 – 1023 101, 110, 111 Do not use – device will be unstable Table 12. Register 40H Change Pump Bit Settings Address D7 D6 D5 D4 D3 D2 D1 D0 40H 1 1 0 Pump(2) Pump(1) Pump(0) PB(9) PB(8) Although using the above table guarantees stability, it is recommended to use the Print preview function in CyClocksRT to determine the correct charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to determine the best charge pump setting. To configure device using serial interface, please refer CyClocksRT. guaranteed to CLKSRC(0,0,1). be rising edge phase-aligned with When DIV2N is divisible by four, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by eight, then CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). CLKOE – Clock Output Enable Control [09H(5..0)] Clock Output Settings: CLKSRC – Clock Output Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)], [46H(7..6)] Each clock output has its own output enable, controlled by register 09H(5..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 15 on page 10. Every clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H. The remainder of register 46H(5:0) must be written with the values stated in the register table when writing register values 46H(7:6). Test, Reserved, and Blank Registers When DIV1N is divisible by four, then CLKSRC(0,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is Document #: 001-15571 Rev. *E Writing to any of the following registers causes the part to exhibit abnormal behavior, as follows. [00H to 08H] [0AH to 0BH] [0DH to 11H] [14H to 3FH] [43H] [48H to FFH] – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved. Page 9 of 23 [+] Feedback CY22801 Table 13. Clock Output Setting CLKSRC2 CLKSRC1 CLKSRC0 Definition and Notes 0 0 0 Reference input. 0 0 1 DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. 0 1 0 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. 0 1 1 DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. 1 0 0 DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. 1 0 1 DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. 1 1 0 DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. 1 1 1 Reserved – do not use. Table 14. Clock Output Register Setting Address D7 D6 D5 D4 D3 D2 44H 1 1 1 1 1 1 45H CLKSRC0 for CLKB 1 1 1 46H CLKSRC1 for CLKSRC0 for CLKC CLKC 1 1 1 D1 D0 CLKSRC2 for CLKSRC1 for CLKB CLKB CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKA CLKA CLKA CLKC 1 1 1 Table 15. CLKOE Bit Setting Address D7 D6 D5 D4 D3 D2 D1 D0 09H 0 0 CLKC CLKA 0 CLKB 0 0 Document #: 001-15571 Rev. *E Page 10 of 23 [+] Feedback CY22801 Application Guideline Field Programming the CY22801 Best Practices for Best Jitter Performance The CY22801 is programmed using the CY36800 USB programmer dongle. The CY22801 is flash-technology based, so the parts are reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Jitter can be specified in different terminologies: Time Domain: ■ Cycle-to-cycle jitter ■ Period jitter ■ Long-term jitter Samples and small prototype quantities are programmed using the CY36800 programmer. Cypress’s value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others, are available for large production quantities. Frequency domain: ■ Deterministic jitter ■ Random jitter ■ Phase noise CyClocksRT Software These jitter terms are usually given in terms of root mean square (RMS), peak-to-peak, or in the case of phase noise, dBC/Hz with respect to fundamental frequency. Cycle-to-cycle and period jitter are generally used terminologies. Jitter depends on many factors and few of the them can be controlled in application: ■ Input reference jitter ■ Number of active clock outputs ■ Operating temperature ■ Clock output load ■ PLL frequencies ■ Termination and layout ■ Supply voltage accuracy CyClocksRT is an easy-to-use software application that enables the user to custom-configure the CY22801. Users can specify the XIN/CLKIN frequency, crystal load capacitance, and output frequencies. CyClocksRT then creates an industry-standard JEDEC file that is used to program the CY22801. When needed, an advanced mode is available that enables users to override the automatically generated voltage controlled oscillator (VCO) frequency and output divider values. CyClocksRT is a component of the CyberClocks™ software that you can download free of charge from the Cypress website at http://www.cypress.com. CY36800 InstaClock™ Kit Jitter is directly proportional to the input reference jitter, number of active clock outputs, operating temperature and clock output load, but inversely proportional to the PLL frequency. Best practices for termination, layout and supply voltage filtering are discussed in application note “Layout and Termination Techniques For Cypress Clock Generators-AN1111”. The Cypress CY36800 InstaClock kit comes with everything needed to design the CY22801 and program samples and small prototype quantities. The CyClocksRT software is used to quickly create a JEDEC programming file, which is then downloaded directly to the portable programmer that is included in the CY36800 InstaClock kit. The JEDEC file can also be saved for use in a production programming system for larger volumes. The CY36800 also comes with five samples of the CY22801, which are programmed with preconfigured JEDEC files using the InstaClock software. Possible Configuration Examples Table 16. Possible Configuration Possible Configurations Pin#1 Pin#3 A CLKIN:33 MHz OE B XIN:27 MHz crystal VCXO PD# CLKA: 74.25 /74.175824 MHz C CLKIN:10 MHz OE FS1 CLKA: FS2 25/40/33.3333/50 MHz NC D CLKIN:10 MHz SDAT SCLK CLKA NC Pin#5 Pin#6 CLKB: 33 MHz CLKA:100 MHz with +/-1% Spread Pin#7 Pin#8 SSON NC FS2 XOUT: 27 MHz crystal CLKB Contact your local Cypress field application engineer for functional feasibility and custom configuration with these advanced features. Document #: 001-15571 Rev. *E Page 11 of 23 [+] Feedback CY22801 Informational Graphs The informational graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. 172.5 171.5 68.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 170.5 169.5 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 68 67.5 168.5 167.5 166.5 67 66.5 Fnominal 165.5 164.5 163.5 162.5 Fnominal 66 65.5 65 64.5 64 161.5 63.5 160.5 159.5 0 0 20 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 40 60 80 100 120 Time (us) 140 160 180 20 40 60 80 200 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% 67.5 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 67 66.5 Fnominal Fnominal 66 65.5 65 64.5 162.5 0 0 20 40 60 80 100 120 Time (us) Document #: 001-15571 Rev. *E 140 160 180 200 20 40 60 80 100 120 Time (us) 140 160 180 200 Page 12 of 23 [+] Feedback CY22801 Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply voltage –0.5 4.6 V TS Storage temperature –65 150 °C TJ Junction temperature – 125 °C VIO Input and output voltage VSS – 0.5 VDD + 0.5 V ESD Electrostatic discharge voltage per MIL-STD-833, Method 3015 2000 – V Recommended Operating Conditions Parameter Description VDD Operating voltage TA Ambient temperature, commercial grade Ambient temperature, industrial grade CLOAD Maximum load capacitance on the CLK output tPU Power-up time for VDD to reach the minimum specified voltage (power ramps must be monotonic) Min Typ Max Unit 3.14 3.3 3.47 V 0 – 70 °C –40 -- 85 °C – – 15 pF 0.05 – 500 ms Min Typ Max Unit 8 – 30 MHz 6 – 30 pF Recommended Crystal Specifications for non-VCXO Applications Parameter Name Description FNOM Nominal crystal frequency Parallel resonance, fundamental mode, and AT cut CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode – 35 50 Ω DL Crystal drive level No external series resistor assumed – 0.5 2 mW Min Typ Max Unit – 14 – pF Pullable Crystal Specifications for VCXO Application Only[5] Parameter Name CLNOM Crystal load capacitance R1 Equivalent series resistance – – 25 Ω R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR. Ratio is used because typical R1 values are much less than the maximum spec. 3 – – – DL Crystal drive level. No external series resistor assumed F3SEPHI Third overtone separation from 3 × FNOM (high side) F3SEPLO Third overtone separation from 3 ×FNOM (low side) C0 Crystal shunt capacitance C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 – 0.5 2 mW 300 – – ppm – – –150 ppm 7 pF fF Note 5. Crystals that meet this specification include Ecliptek ECX-5788-13.500M, Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL, and PDI HA13500XFSA14XC. Document #: 001-15571 Rev. *E Page 13 of 23 [+] Feedback CY22801 DC Electrical Specifications[6] Parameter Name Description Min Typ Max Unit IOH Output high current VOH = VDD – 0.5, VDD = 3.3 V (source) 12 24 – mA IOL Output low current VOL = 0.5, VDD = 3.3 V (sink) 12 24 – mA CIN1 Input capacitance All input pins except XIN and XOUT – – 7 pF CIN2 Input capacitance XIN and XOUT pins for non-VCXO applications – 24 – pF IIH Input high current VIH = VDD – 5 10 μA IIL Input low current VIL = 0 V – – 50 μA fΔXO VCXO pullability range Using crystal in this datasheet VVCXO VCXO input range VIH Input high voltage VIL IDD[7] ±150 – 0 – VDD ppm V CMOS levels, 70% of VDD 0.7 × VDD – – V Input low voltage CMOS levels, 30% of VDD – – 0.3 × VDD V VDD supply current All three clock outputs are at 100 MHz – 30 – mA AC Electrical Characteristics Parameter[6] Min Typ Max Unit fREFC Reference frequency - crystal Name Description 8 – 30 MHz fREFD Reference frequency - driven 1 – 133 MHz fOUT Output frequency, commercial grade 1 – 200 MHz Output frequency, industrial grade 1 – 166.6 MHz DC Output duty cycle 50% of VDD, see Figure 6 45 50 55 % t3 Rising edge slew rate Output clock rise time, 20% - 80% of VDD, see Figure 7 0.8 1.4 – V/ns t4 Falling edge slew rate Output clock fall time, 80% - 20% of VDD, see Figure 7 0.8 1.4 – V/ns t5[8] Skew Output-output skew between related outputs, see Figure 9 – – 250 ps Clock jitter Peak-to-peak period jitter, see Figure 8 – 250 – ps Cycle-to-cycle jitter CLKA/B/C XIN = CLKA/B/C = 166 MHz, ± 2% spread and No REFOUT, VDD = 3.3 V, see Figure 10 – – 110 ps XIN = CLKA/B/C = 66.66 MHz, ± 2% spread and No REFOUT, VDD = 3.3 V, see Figure 10 – – 170 ps XIN = CLKA/B/C = 33.33 MHz, ± 2% spread and No REFOUT, VDD = 3.3 V, see Figure 10 – – 140 ps XIN = CLKA/B/C = 14.318 MHz, ± 2% spread and No REFOUT, VDD = 3.3 V, see Figure 10 – – 290 ps Time from falling edge on PD# Pin to tristated outputs (Asynchronous), see Figure 11 – 150 300 ns t6[9] tCCJ tPD [9] Power-down time Notes 6. Not 100% tested, guaranteed by design. 7. Power supply current is configuration dependent. Use CyClocksRT to calculate actual IDD for specific output frequency configurations. 8. Skew value guaranteed when outputs are generated from the same divider bank. 9. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage, temperature, and output load. Document #: 001-15571 Rev. *E Page 14 of 23 [+] Feedback CY22801 AC Electrical Characteristics (continued) Parameter[6] Name Description Min Typ Max Unit tOE1 Output disable time Time from falling edge on OE Pin to tristated outputs (Asynchronous), see Figure 12 – 150 300 ns tOE2 Output enable time Time from rising edge on OE Pin to valid clock outputs (asynchronous), see Figure 12 – 150 300 ns FMOD Spread spectrum modulation frequency 30.1 31.5 32.9 kHz t10 PLL lock time – – 3 ms Test Circuit Figure 5. Test Circuit Diagram VDD 0.1μF Output CLKout CLOAD GND Document #: 001-15571 Rev. *E Page 15 of 23 [+] Feedback CY22801 Timing Definitions Figure 6. Duty Cycle Definition; DC = t2/t1 Figure 7. Rise and Fall Time Definitions t3 t1 t2 CLK t4 80% CLK 50% 50% Figure 8. Period Jitter Definition 20% Figure 9. Skew Definition t5 t6 50% CLKx CLK 50% CLKy Figure 10. Cycle to Cycle Jitter Definition (CCJ) TCycle_i TCycle_i+1 50% Figure 11. Power-Down and Power-Up Timing POWER DOWN CLK CLK 50% VIH VIL tPU High Impedance tPD tCCJ = TCycle_i - TCycle_i+1 (over 1000 Cycles) Figure 12. Output Enable and Disable Timing OUTPUT ENABLE CLK VIH VIL tOE2 High Impedance tOE1 Document #: 001-15571 Rev. *E Page 16 of 23 [+] Feedback CY22801 2-wire Serial (I2C) Interface Timing When using I2C interface, the CY22801 should be programmed as I2C-capable prior to using this interface. The CY22801 uses a 2-wire serial-interface SDAT and SCLK that operates up to 400 kbits/second in read or write mode. The basic write serial format is as follows. Start Bit; seven-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); eight-bit Memory Address (MA); ACK; eight-bit data; ACK; eight-bit data in MA + 1 if desired; ACK; eight-bit data in MA+2; ACK; and so on, until STOP bit. The basic serial format is illustrated in Figure 14. Data Valid Data is valid when the Clock is HIGH, and may only be transitional when the clock is LOW, as illustrated in Figure 13. Start Sequence – Start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a Start signal is given, the next eight-bit data must be the device address (seven bits) and a R/W bit, followed by the register address (eight bits) and register data (eight bits). Stop Sequence – Stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write mode, the CY22801 responds with an ACK pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 16. (N = the number of eight-bit segments transmitted.) During Read mode, the ACK pulse, after the data packet is sent, is generated by the master. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 15. Figure 13. Data Valid and Data Transition Periods Data valid Transition to next bit SDAT CLKHIGH tDH tSU VIH SCLK VIL CLKLOW Figure 14. Data Frame Architecture SDAT Write Multiple Contiguous Registers 1-bit 1-bit 1-bit 1-bit 1-bit Slave Slave Slave Slave ACK ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit 8-bit Device Register Register Register Register Data Address Address Data Data (XXH) (XXH) (XXH+1) (XXH+2) 1-bit Slave ACK 1-bit Slave ACK 8-bit Register Data (FFH) 1-bit Slave ACK 8-bit Register Data (00H) Stop Signal Start Signal SDAT Read Multiple Contiguous Registers 1-bit Slave ACK 1-bit 1-bit 1-bit 1-bit Slave Slave 1-bit Master R/W = 1 ACK R/W = 0 ACK ACK 7-bit 8-bit 8-bit 8-bit Device Register 7-Bit Register Register Address Address Device Data Data (XXH) Address (XXH) (XXH+1) Start Signal Document #: 001-15571 Rev. *E 1-bit Master ACK 1-bit Master ACK 8-bit Register Data (FFH) 1-bit Master ACK 1-bit Master ACK 8-bit Register Data (00H) Stop Signal Page 17 of 23 [+] Feedback CY22801 Figure 15. Start and Stop Frame SDAT Transition to next bit START SCLK STOP Figure 16. Frame Format (Device Address, R/W, Register Address, Register Data SDAT + START DA6 SCLK DA5DA0 + R/W ACK RA7 RA6RA1 + RA0 ACK D7 + + D6 D1 D0 ACK STOP + Table 17. Two-wire Serial Interface Parameters Parameter fSCLK Description Frequency of SCLK Min Max Unit – 400 kHz Start mode time from SDA LOW to SCL LOW 0.6 – μs CLKLOW SCLK LOW period 1.3 – μs CLKHIGH SCLK HIGH period 0.6 – μs tSU Data transition to SCLK HIGH 100 – ns tDH Data hold (SCLK LOW to data transition) 100 – ns Rise time of SCLK and SDAT – 300 ns Fall time of SCLK and SDAT – 300 ns Stop mode time from SCLK HIGH to SDAT HIGH 0.6 – μs Stop mode to start mode 1.3 – μs Document #: 001-15571 Rev. *E Page 18 of 23 [+] Feedback CY22801 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY22801KFXC 8-pin SOIC Commercial, 0 °C to 70 °C 3.3 V CY22801KFXCT 8-pin SOIC - tape and reel Commercial, 0 °C to 70 °C 3.3 V CY22801KFXI 8-pin SOIC Industrial, – 40 °C to 85 °C 3.3 V CY22801KFXIT 8-pin SOIC - tape and reel Industrial, – 40 °C to 85 °C 3.3 V Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales representative for more information. Possible Configurations Ordering Code Package Type Operating Range Operating Voltage CY22801KSXC-xxx[9] 8-Pin SOIC Commercial, 0 °C to 70 °C 3.3 V CY22801KSXC-xxxT[9] 8-Pin SOIC - tape and reel Commercial, 0 °C to 70 °C 3.3 V CY22801KSXI-xxx[9] 8-Pin SOIC Industrial, – 40 °C to 85 °C 3.3 V CY22801KSXI-xxxT[9] 8-Pin SOIC - tape and reel Industrial, – 40 °C to 85 °C 3.3 V Ordering Code Definitions CY xxxxx K F X (X) (-xxx) T T = Tape and reel, Blank = Tube Dash code (Only for Factory Programmable Devices) Temperature range: C = Commercial, I = Industrial Pb-free, Blank = leaded Programming Option: F = Field Programmable, Blank = Factory Programmable Fixed value: K Part identifier Company ID: CY = Cypress Notes 10. Ordering codes with “xxx” are factory-programmed configurations. Factory programming is available for high volume orders. For more details, contact your local Cypress field application engineer or Cypress sales representative. Document #: 001-15571 Rev. *E Page 19 of 23 [+] Feedback CY22801 Package Diagram Figure 17. 8-Pin (150-Mil) SOIC SZ08 51-85066 *D Document #: 001-15571 Rev. *E Page 20 of 23 [+] Feedback CY22801 Acronyms Table 18. Acronyms Used in this Documnent Acronym ACK CLKIN EMI ESD EMC FS I2C JEDEC EIA LVCMOS OE Description Acknowledge Clock input Electromagnetic interference Electrostatic discharge Electromagnetic compatibility Frequency select Inter integrated circuit Joint electron device engineering council electronic industries alliance Low-voltage complementary metal oxide semiconductor Output enable Acronym PD PFD PLL SSON SCLK SDAT SSC VCO Description Power down Phase frequency detector Phase locked loop Spread spectrum ON Serial interface clock Serial interface data Spread spectrum clock Voltage controlled oscillator VCXO Voltage controlled crystal oscillator , Document Conventions Units of Measure Table 19. Units of Measure Symbol °C dB dBc/Hz fC fF Hz KB Kbit kHz kΩ MHz MΩ µA µF µH µs µV Unit of Measure degrees Celsius decibels decibels relative to the carrier per Hertz femto Coulomb femto Farads hertz 1024 bytes 1024 bits kilohertz kilohms megahertz megaohms microamperes microfarads microhenrys microseconds microvolts Document #: 001-15571 Rev. *E Symbol µVrms µW mA mm ms mV nA ns nV Ω pA pF pp ppm ps sps σ Unit of Measure microvolts root-mean-square microwatts milliamperes millimeters milliseconds millivolts nanoamperes nanoseconds nanovolts ohms picoamperes pico Farads peak-to-peak parts per million picoseconds samples per second sigma: one standard deviation Page 21 of 23 [+] Feedback CY22801 Document History Page Document Title: CY22801 Universal Programmable Clock Generator (UPCG) Document Number: 001-15571 Revision ECN Orig. of Change Submission Date ** 1058080 KVM/ KKVTMP 05/10/07 New data sheet *A 2440787 AESA 05/16/08 Updated template. Added Note 9 and 10. Added existing part numbers CY22801FXCT, CY22801FXI, CY22801FXIT, CY22801SXC-xxx and CY22801SXC-xxxT in ordering information table. Added new part numbers CY22801KFXC, CY22801KFXCT, CY22801KFXI, CY22801KFXIT, CY22801KSXC-xxx and CY22801KSXC-xxxT. *B 2724806 KVM/ AESA 6/26/09 Add Industrial Grade Ambient Temperature to Recommended Operating Conditions. Add separate Fout max limit for industrial temp. Add temperature ranges to the Ordering Information Table. Remove CY22801FXCT and CY22801FXIT from Ordering Information Table. Add CY22801KSXI-xxx and CY22801KSXI-xxxT to Ordering Information Table. Correct package reference from S8 to SZ08. *C 2897775 KVM 03/23/10 Removed inactive parts from the Ordering Information table. Moved xxx parts to Possible Configurations table.Updated package diagram *D 2981862 BASH 07/15/2010 Features: Added SS, VCXO, FS, PD, OE Removed Benefits section from page 1. Updated Logic Block Diagram, Pin Configuration, and Pin Definition Added SSCG and VCXO description, Frequency Calculation and Register Definitions, Multi Function Pin Options and Possible Configurations sections Added information graphs of Spread Spectrum Added serial interface description Added crystal specs for VCXO Added VCXO specs in DC specifications Table Added CTCJ, PD and OE timing in AC char Table Added and Ordering Code Definitions. Added Crystal part numbers in footnote “a” on page 13. *E 3207656 CXQ 03/28/2011 Changed tDH min spec from 0 ns to 100 ns. Document #: 001-15571 Rev. *E Description of Change Page 22 of 23 [+] Feedback CY22801 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-15571 Rev. *E Revised March 28, 2011 Page 23 of 23 CyClocksRT, CyberClocks, and InstaClock are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback