CY24207 MediaClock™ PDP Clock Generator Features • • • • Benefits Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs VCXO with Analog Adjust 3.3V operation • Internal PLL with up to 400-MHz internal operation • Meets critical timing requirements in complex system designs • Large ±200-ppm range, better linearity • Enables application compatibility Part Number Outputs Input Frequency CY24207-1 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 54/53.946053/67.425/67.357642 MHz (frequency selectable) Output Frequency Range CY24207-2 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 54/53.946053/67.425/68.400599 MHz (frequency selectable) Pin Configuration Block Diagram 16-pin TSSOP XIN Q OSC. Φ XOUT OUTPUT MULTIPLEXER AND DIVIDERS P VCXO REFCLK2 FS0 16 XOUT 2 15 13 OE FS1 VSS 12 CLK1 AVDD 3 4 AVSS 5 VSSL REFCLK2 6 REFCLK1 8 CLK2 REFCLK1 1 VCXO CLK1 PLL XIN VDD 7 24207-1,-2 VCO 14 11 VDDL 10 FS0 9 CLK2 FS1 OE VDDL VDD AVDD AVSS VSS VSSL Frequency Select Options OE FS1 FS0 CLK1/CLK2 (-1)[1] CLK1/CLK2 (-2)[1] REFCLK 1/2 Unit 0 0 0 off off 27 MHz 0 0 1 off off 27 MHz 0 1 0 off off 27 MHz 0 1 1 off off 27 MHz 1 0 0 54 54 27 MHz 1 0 1 53.946053 (–1 ppm) 53.946053 (–1 ppm) 27 MHz 1 1 0 67.425 67.425 27 MHz 1 1 1 67.357642 (3.8 ppm) 68.400599(–8.8 ppm) 27 MHz Note: 1. “off” = output is driven high. Cypress Semiconductor Corporation Document #: 38-07553 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 31, 2003 CY24207 Pin Description Pin No. Name Description 1 XIN Reference crystal input 2 VDD Voltage supply 3 AVDD Analog voltage supply 4 VCXO Input analog control for VCXO 5 AVSS Analog ground 6 VSSL CLK ground 7 REFCLK2 Reference clock output 8 REFCLK1 Reference clock output 9 CLK1 (–1) 54/53.946053/67.425/67.357642 MHz clock output (frequency selectable) 9 CLK1 (–2) 54/53.946053/67.425/68.400599 MHz clock output (frequency selectable) 10 FS0 Frequency Select 0, weak internal pull-up 11 VDDL CLK voltage supply 12 CLK2 (–1) 54/53.946053/67.425/67.357642 MHz clock output (frequency selectable) 12 CLK2 (–2) 54/53.946053/67.425/68.400599 MHz clock output (frequency selectable) 13 VSS Ground 14 FS1 Frequency Select 1, weak internal pull-up 15 OE Output Enable, weak internal pull-up 16 XOUT Reference crystal output Document #: 38-07553 Rev. *A Page 2 of 6 CY24207 Data Retention @ Tj = 125°C................................> 10 years Absolute Maximum Conditions Package Power Dissipation...................................... 350 mW Supply Voltage (VDD, AVDDL, VDDL)..................–0.5 to +7.0V ESD (Human Body Model) MIL-STD-883.................... 2000V DC Input Voltage........................................ –0.5V to VDD+0.5 (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (Non-condensing).....–55°C to +125°C Junction Temperature ................................ –40°C to +125°C Pullable Crystal Specifications Parameter Description FNOM Nominal crystal frequency CLNOM Nominal load capacitance Conditions Min. Parallel resonance, fundamental mode, AT cut R1 Equivalent series resistance (ESR) Fundamental mode R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec DL Crystal drive level No external series resistor assumed Typ. Max. Units 27.0 MHz 14 pF 25 Ω 2 mW –150 ppm 7 pF 3 0.5 F3SEPHI Third overtone separation from 3*FNOM High side F3SEPLO Third overtone separation from 3*FNOM Low side 300 C0 Crystal shunt capacitance C0/C1 Ratio of shunt to motional capacitance 180 C1 Crystal motional capacitance 14.4 ppm 250 18 21.6 fF Recommended Operating Conditions Parameter Description VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. 3.135 3.3 Unit 3.465 V 0 70 °C 15 pF 0.05 500 ms DC Electrical Specifications Parameter2 Name Description Min. Typ. 12 24 VOL = 0.5, VDD/VDDL = 3.3V 12 24 CMOS levels, 70% of VDD 0.7 Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V IOL Output Low Current VIH Input High Voltage VIL Input Low Voltage CMOS levels, 30% of VDD 0.3 VDD IVDD Supply Current AVDD/VDD Current 25 mA IVDDL Supply Current VDDL Current (VDDL = 3.47V) 20 mA CIN Input Capacitance excluding XIN and XOUT 7 pF f∆XO VCXO pullability range VVCXO VCXO input range RUP Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured at VIN = 0V Document #: 38-07553 Rev. *A mA mA VDD ±200 0 100 ppm VDD V 150 kΩ Page 3 of 6 CY24207 AC Electrical Specifications Parameter[2] Description Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter t10 PLL Lock Time 120 ps 3 ms Test and Measurement Set-up VDDs Outputs 0.1 µF CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Note: 2. Not 100% tested. Document #: 38-07553 Rev. *A Page 4 of 6 CY24207 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24207ZC-1 16-pin TSSOP Commercial 3.3V CY24207ZC-1T 16-pin TSSOP Commercial 3.3V CY24207ZC-2 16-pin TSSOP Commercial 3.3V CY24207ZC-2T 16-pin TSSOP Commercial 3.3V Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-07553 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY24207 Document History Page Document Title: CY24207 MediaClock™ PDP Clock Generator Document Number: 38-07553 REV. ECN NO. Issue Date *.* 127230 06/26/03 *A 128248 07/31/03 Document #: 38-07553 Rev. *A Orig. of Change RGL Description of Change New Data Sheet IJATMP Added -2 part number Added CLK1/CLK2 (-2) column to Frequency Select Options Added new definitions for Pins 9 and 12 in Pin Description table Page 6 of 6