CY26211 PRELIMINARY PacketClock™ T1/E1 Clock Generator Features Benefits • Integrated phase-locked loop High performance PLL tailored for T1/E1 clock generation • Low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • 3.3V Operation Enables application compatibility Part Number Outputs Input Frequency Range Output Frequencies CY26211 2 1.544 or 2.048 MHz 19.44 MHz, 77.76 MHz Logic Block Diagram Q Fref Φ VCO OUTPUT DIVIDERS CLK1 P CLK2 PLL FS VDD VSS Pin Configuration CY26211 8-pin SOIC Table 1. CY26211 Frequency Select Option Fref 1 8 NC VDD FS 2 7 3 6 NC CLK1 VSS 4 5 CLK2 Cypress Semiconductor Corporation Document #: 38-07447 Rev. ** • Frequency Select Fref CLK1 CLK2 Unit 0 1.544 19.44 77.76 MHz 1 2.048 19.44 77.76 MHz 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 9, 2002 CY26211 Pin Description Name Pin Number Description Fref 1 1.544-MHz/2.048-MHz Reference Input VDD 2 Voltage Supply FS 3 Frequency Select. Weak internal pull-up. See Table 1 for a description of pin function. VSS 4 Ground CLK2 5 77.76-MHz Clock Output CLK1 6 19.44-MHz Clock Output NC 7 No Connect NC 8 No Connect Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[1] –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Junction Temperature TJ Electro-Static Discharge 2000 V Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature (Commercial) CLOAD Max. Load Capacitance fREF Reference Frequency Min Typ Max 3.135 3.3 Unit 3.465 V 0 70 °C 15 pF 1.544 2.048 MHz DC Electrical Specifications (Commercial) Min Typ IOH Parameter Output High Current Name VOH = VDD – 0.5, VDD = 3.3V Description 12 24 IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 CIN Input Capacitance Max Unit mA mA 7 pF IIH Input Low Current VIL = 0V 50 µA IIL Input High Current VIH = VDD 5 µA IDD Supply Current Sum of Core and Output Current 20 mA VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD RUP Pull-up resistor VDD=3.14V to 3.47V, measured at VIN = 0V 0.7VDD V 100 0.3VDD V 150 kΩ AC Electrical Specifications (VDD = 3.3V) Parameter[2] Name Description Min Typ Max 55 Unit DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 ERO Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15pF See Figure 2. 0.8 1.4 V/ns EFO Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15pF See Figure 2. 0.8 1.4 V/ns Clock Jitter Peak to Peak Period Jitter 200 ps t9 t10 PLL Notes: 1. Rated for 10 years 2. Not 100% tested Lock Time Document #: 38-07447 Rev. ** 3 % ms Page 2 of 5 CY26211 Test and Measurement Set-up VDD CLK out 0.1 µF CLOAD OUTPUTS GND Voltage and Timing Definitions t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26211SC S8 8-Pin SOIC Commercial 3.3V CY26211SCT S8 8-Pin SOIC - Tape and Reel Commercial 3.3V Document #: 38-07447 Rev. ** Page 3 of 5 PRELIMINARY CY26211 Package Drawing and Dimensions 8-Lead (150-Mil) SOIC S8 51-85066-*A All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07447 Rev. ** Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26211 Document History Page Document Title: CY26211 PacketClock™ T1/E1 Clock Generator Document Number: 38-07447 REV. ECN NO. Issue Date Orig. of Change ** 121428 12/10/02 CKN Document #: 38-07447 Rev. ** Description of Change New data sheet Page 5 of 5