CY28439 PRELIMINARY Clock Generator for Intel Grantsdale Chipset Features • Watchdog • Two independent overclocking PLLs • Compliant to Intel CK410 • Low-voltage frequency select input • Supports Intel Prescott and Tejas CPU • I2C support with readback capabilities • Selectable CPU frequencies • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Differential CPU clock pairs • 100-MHz differential SRC clocks (two selectable between Fixed and Overclocking) • 3.3V power supply • 56-pin SSOP and TSSOP packages • 96-MHz differential dot clock • 48-MHz USB clocks CPU SRC • 33-MHz PCI clock • x2 x6 PCI x9 REF DOT96 x2 x1 USB 24-48M x1 x1 Dial-A-Frequency Block Diagram Xin Xout Pin Configuration VDD_RE F RE F 14.318MHz Crystal PLL Reference IREF VDD_CPU PLL1 CPU CPUT CPUC Divider FS_[E:A] VDD_SRC SRCT (PCI Ex) SRCC (PCI Ex) PLL2 SRC Divider PLL3 SATA Divider PLL4 Fixed Divider VDD_SRC SRCT4_SATA SRCC4_SATA VDD_48Mhz DOT96T DOT96C VDD_48 USB48 VTTPWR_GD#/PD VDD_48 24/48 VDD_PCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28439 VSS_PCI PCI3 *FS_E/PCI4 PCI5 VSS_PCI VDD_PCI PCIF0 **FS_A/PCIF1 *FS_B/PCIF2 VDD_48 **SEL24_48#/24_48M USB48 VSS_48 DOT96T DOT96C VTTPWRGD#/PD SRCT0 SRCC0 VDD_SRC VSS_SRC SRCT1 SRCC1 SRCT2 SRCC2 VSS_SRC SRCT_SATAT SRCC_SATAC VDD_SRC 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_PCI PCI2 PCI1 PCI0 SRESET# REF1/FS_C** REF0/FS_D** VSS_REF XIN XOUT VDD_REF SCLK SDATA CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 VSS_CPU IREF VSSA VDDA VDD_SRC SRCT4 SRCC4 SRCT3 SRCC3 VSS_SRC PCI * Indicates internal pull-up ** Indicates internal pull-down VDD_PCI PCIF SDATA SCLK I2C Logic Cypress Semiconductor Corporation Document #: 38-07668 Rev. *D Watchdog Timer • SRESET# 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 13, 2005 CY28439 PRELIMINARY Pin Description Pin No. Name Type Description 6,56 VDD_PCI PWR 3.3V power supply for outputs. 1,5 VSS_PCI GND Ground for outputs. 3 FS_E/PCI4 2,4,53,54, PCI 55 I,O, 3.3V-tolerant input for CPU frequency selection/33-MHz clock. PU,SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. O, SE 33-MHz clocks. 7 PCIF0 8 FS_A/PCIF1 I/O,PD, 3.3V-tolerant input for CPU frequency selection/Free running 33-MHz clock. SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. O,SE 33-MHz free running clock 9 FS_B/PCIF2 I/O, PU, 3.3V-tolerant input for CPU frequency selection/Free running 33-MHz clock. SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 16 VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C,FS_D, FS_E, SEL24_48. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power down (active HIGH). 10 VDD_48 PWR 3.3V power supply for outputs. 11 SEL24_48#/24_48 I/O, PD, Latched select input for 24-/48-MHz output/ 24-/48-MHz output M SE 0 = 48 MHz, 1 = 24 MHz 12 USB48 I/O, 48-MHz clock output. GND Ground for outputs. 13 VSS_48 14,15 DOT96T, DOT96C O, DIF Fixed 96-MHz clock output. 17,18,21, 22,23,24, 30,31,32, 33 SRCT/C O, DIF Differential serial reference clocks. Outputs have overclocking capability. 19,28,34 VDD_SRC 26,27 SRCT/C_SATAT/C 20,25,29 VSS_SRC GND Ground for outputs. 35 VDDA PWR 3.3V power supply for PLL. 36 VSSA GND Ground for PLL. 37 IREF I 41 VDD_CPU 39,40,42,43 CPUT/C PWR 3.3V power supply for outputs. O, DIF Differential serial reference clock. Recommended output for SATA. PWR A precision resistor is attached to this pin, which is connected to the internal current reference. 3.3V power supply for outputs. O, DIF Differential CPU clock outputs. 38 VSS_CPU 45 SCLK I 44 SDATA I/O 46 VDD_REF PWR 47 XOUT O, SE 14.318-MHz crystal output. 48 XIN 49 VSS_REF 50 REF0/FS_D I/O, SE, 3.3V-tolerant input for CPU frequency selection/Reference clock. Refer to DC PD Electrical Specifications table for Vil_FS and Vih_FS specifications. 51 REF1/FS_C O, SE, 3.3V-tolerant input for CPU frequency selection/Reference clock. PD Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. 52 SRESET# O, SE 3.3V output for Watchdog reset. This output is open drain type with a high (>100-kΩ) internal pull-up resistor. Document #: 38-07668 Rev. *D GND I GND Ground for outputs. SMBus-compatible SCLOCK. SMBus-compatible SDATA. 3.3V power supply for outputs. 14.318-MHz crystal input. Ground for outputs. Page 2 of 22 CY28439 PRELIMINARY Frequency Select Pins (FS_[A:E]) The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and FS_E inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, FS_C, FS_D, and FS_E input values. For all logic levels of FS_A, FS_B, FS_C, FS_D, and FS_E, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C, FS_D, and FS_E transitions will be ignored, except in test mode. FS_C is a three level input, when sampled at a voltage greater than 2.1V by VTTPWRGD#, the device will enter test mode as selected by the voltage level on the FS_B input. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. Serial Data Interface The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. Input Conditions Output Frequency FS_D FS_C FS_B FS_A CPU SRC FSEL_3 FSEL_2 FSEL_1 FSEL_0 (MHz) (MHz) SRC M CPU PLL CPU M CPU N CPU N SRC PLL SRC N SRC N divider (not DEFAULT allowable Gear divider DEFAULT allowable Gear Constants range for Constants changeable range for by user) DAF DAF (G) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 100 133.3333333 166.6666667 200 266.6666667 333.3333333 400 100.952381 133.968254 167 200.952381 266.6666667 334 400.6451613 100 100 100 100 100 100 100 100 100 100 100 100 100 100 30 40 60 60 80 120 120 30 40 60 60 80 120 120 60 60 63 60 60 63 60 63 63 60 63 60 60 62 200 200 175 200 200 175 200 212 211 167 211 200 167 207 200 - 250 200 - 250 175 - 262 200 - 250 200 - 250 175 - 262 200 - 250 212 - 262 211 - 262 167 - 250 211 - 262 200 - 250 167 - 250 207 - 258 X X HIGH HIGH LOW HIGH X X Tristate REF/N Tristate REF/N Tristate REF/N Tristate REF/N Tristate REF/N Tristate REF/N 30 30 30 30 30 30 30 30 30 30 30 30 30 30 60 60 60 60 60 60 60 60 60 60 60 60 60 60 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 200 - 266 200 167 - 266 200 167 - 266 Figure 1. CPU and SRC Frequency Select Tables Document #: 38-07668 Rev. *D Page 3 of 22 CY28439 PRELIMINARY Table 1. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Block Read Protocol Bit 1 Slave address – 7 bits 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeated start 19 27:20 28 Acknowledge from slave 29 Stop Document #: 38-07668 Rev. *D 9 Description Start 27:21 Write Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Page 4 of 22 CY28439 PRELIMINARY Control Registers Byte 0: Control Register 0 Bit @Pup Name Description 7 1 RESERVED 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable 4 1 SATA[T/C] SATA[T/C] Output Enable 0 = Disable (Tri-state), 1 = Enable 3 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable 2 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable 1 1 RESERVED 0 1 SRC[T/C]0 RESERVED RESERVED SRC[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name Description 7 1 PCIF0 6 1 DOT_96[T/C] 5 1 24_48M 24_48 MHz Output Enable 0 = Disabled, 1 = Enabled 4 1 REF0 REF0 Output Enable 0 = Disabled, 1 = Enabled 3 0 RESERVED 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled 0 1 CPU PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled RESERVED PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name 7 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 PCI1 PCI1 Output Enable 0 = Disabled, 1 = Enabled 2 1 PCI0 PCI0 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCIF2 PCIF2 Output Enable 0 = Disabled, 1 = Enabled Document #: 38-07668 Rev. *D Description Page 5 of 22 CY28439 PRELIMINARY Byte 2: Control Register 2 (continued) Bit @Pup Name 0 1 PCIF1 Description PCIF1 Output Enable 0 = Disabled, 1 = Enabled Byte 3: Control Register 3 Bit @Pup Name Description 7 0 RESERVED 6 0 SRC4 Allow control of SRC[T/C]4 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 5 0 SRC3 Allow control of SRC[T/C]3 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 4 0 SATA[T/C] Allow control of SATA[T/C] with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 SRC2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC1 Allow control of SRC[T/C]1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 RESERVED 0 0 SRC0 RESERVED, Set = 0 RESERVED Allow control of SRC[T/C]0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit @Pup Name Description 7 HW FS_E FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E was low during VTT_PWRGD# assertion. 6 0 DOT96[T/C] 5 0 PCIF2 Allow control of SRC[T/C]2 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 1 RESERVED RESERVED, Set = 1 1 1 RESERVED RESERVED, Set = 1 0 1 RESERVED RESERVED, Set = 1 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state Byte 5: Control Register 5 Bit @Pup Name 7 0 SRC[T/C] 6 0 RESERVED RESERVED, Set = 0 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED RESERVED, Set = 0 3 0 SRC[T/C][4:0] 2 0 RESERVED 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted Document #: 38-07668 Rev. *D Description SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted RESERVED, Set = 0 Page 6 of 22 CY28439 PRELIMINARY Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL 6 0 TEST_MODE 5 HW FS_D FS_D reflects the value of the FS_D pin sampled on power-up. 0 = FS_D was low during VTT_PWRGD# assertion 4 1 REF REF Output Drive Strength 0 = High, 1 = Low 3 1 2 HW FS_C FS_C Reflects the value of the FS_C pin sampled on power-up 0 = FS_C was low during VTT_PWRGD# assertion 1 HW FS_B FS_B Reflects the value of the FS_B pin sampled on power-up 0 = FS_B was low during VTT_PWRGD# assertion 0 HW FS_A FS_A Reflects the value of the FS_A pin sampled on power-up 0 = FS_A was low during VTT_PWRGD# assertion REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode PCI, PCIF and SRC clock SW PCI_STP# Function outputs except those set 0=SW PCI_STP# assert, 1= SW PCI_STP# deassert to free running When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID Bit @Pup Name Description 7 0 Revision Code Bit 3 Revision Code Bit 3 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 0 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name 7 0 CPU_SS Spread Selection for CPU PLL 0: –0.5% (peak to peak) 1: –1.0% (peak to peak) 6 0 CPU_DWN_SS Spread Selection for CPU PLL 0: Down spread. 1: Center spread 5 0 SRC_SS_OFF SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on 4 0 SRC_SS Spread Selection for SRC PLL 0: –0.5% (peak to peak) 1: –1.0% (peak to peak) 3 0 RESERVED 2 1 USB USB 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 1 1 PCI 33-MHz Output Drive Strength 0 = 2x, 1 = 1x 0 0 RESERVED Document #: 38-07668 Rev. *D Description RESERVED, Set = 0 RESERVED Page 7 of 22 CY28439 PRELIMINARY Byte 9: Control Register 9 Bit @Pup Name 7 0 RESERVED 6 0 5 0 4 0 3 0 FSEL_D 2 0 FSEL_C 1 0 FSEL_B 0 0 FSEL_A Description RESERVED SW Frequency selection bits. See Table 1. Byte 10: Control Register 10 Bit @Pup Name Description 7 0 Recovery_Frequency 6 0 Timer_SEL Timer_SEL selects the WD reset function at SRESET pin when WD time out. 0 = Reset and Reload Recovery_Frequency 1 = Only Reset 5 1 Time_Scale Time_Scale allows selection of WD time scale 0 = 294 ms 1 = 2.34 s 4 0 WD_Alarm WD_Alarm is set to “1” when the Watchdog times out. It is reset to “0” when the system clears the WD_TIMER time stamp. 3 0 WD_TIMER2 2 0 WD_TIMER1 1 0 WD_TIMER0 0 0 WD_EN This bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: Use HW settings 1: Recovery N[8:0] Watchdog timer time stamp selection 000: Reserved (test mode) 001: 1 * Time_Scale 010: 2 * Time_Scale 011: 3 * Time_Scale 100: 4 * Time_Scale 101: 5 * Time_Scale 110: 6 * Time_Scale 111: 7 * Time_Scale Watchdog timer enable, when the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable, 1 = Enable Byte 11: Control Register 11 Bit @Pup Name Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. 7 0 CPU_DAF_N7 6 0 CPU_DAF_N6 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 Document #: 38-07668 Rev. *D Page 8 of 22 CY28439 PRELIMINARY Byte 12: Control Register 12 Bit @Pup Name Description If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the CPU output frequency. The setting of FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. 7 0 CPU_DAF_N8 6 0 CPU_DAF_M6 5 0 CPU_DAF_M5 4 0 CPU_DAF_M4 3 0 CPU_DAF_M3 2 0 CPU_DAF_M2 1 0 CPU_DAF_M1 0 0 CPU_DAF_M0 Byte 13: Control Register 13 Bit @Pup Name Description 7 0 SRC_N7 SRC Dial-A-Frequency Bit N7 6 0 SRC_N6 SRC Dial-A-Frequency Bit N6 5 0 SRC_N5 SRC Dial-A-Frequency Bit N5 4 0 SRC_N4 SRC Dial-A-Frequency Bit N4 3 0 SRC_N3 SRC Dial-A-Frequency Bit N3 2 0 SRC_N2 SRC Dial-A-Frequency Bit N2 1 0 SRC_N1 SRC Dial-A-Frequency Bit N1 0 0 SRC_N0 SRC Dial-A-Frequency Bit N0 Byte 14: Control Register 14 Bit @Pup Name 7 0 SRC_N8 Description 6 0 SW_RESET 5 0 FS_[E:A] 4 0 SMSW_SEL Smooth switch select 0: Select CPU_PLL 1: Select SRC_PLL. 3 0 RESERVED RESERVED, Set = 0 2 0 RESERVED RESERVED, Set = 0 1 1 PCIF 0 0 Recovery_N8 SRC Dial-A-Frequency Bit N8 Software Reset. When set the device will assert a reset signal on SRESET# upon completion of the block/word/byte write that set it. After asserting and deasserting the SRESET# this bit will self clear (set to 0). The SRESET# pin must be enabled by latching SRESET#_EN on VTT_PRWGD# to utilize this feature. FS_Override 0 = Select operating frequency by FS(E:A) input pins 1 = Select operating frequency by FSEL_(4:0) settings Free running 33-MHz Output Drive Strength 0 = 2x, 1 = 1x Watchdog Recovery Bit Byte 15: Control Register 15 Bit @Pup Name 7 0 Recovery N7 Watchdog Recovery Bit 6 0 Recovery N6 Watchdog Recovery Bit 5 0 Recovery N5 Watchdog Recovery Bit 4 0 Recovery N4 Watchdog Recovery Bit 3 0 Recovery N3 Watchdog Recovery Bit Document #: 38-07668 Rev. *D Description Page 9 of 22 CY28439 PRELIMINARY Byte 15: Control Register 15 (continued) Bit @Pup Name Description 2 0 Recovery N2 Watchdog Recovery Bit 1 0 Recovery N1 Watchdog Recovery Bit 0 0 Recovery N0 Watchdog Recovery Bit Byte 16: Control Register 16 Bit @Pup Name 7 1 REF1 REF1 Output Enable 0 = Disable, 1 = Enable Description 6 1 USB48 USB48 Output Enable 0 = Disable, 1 = Enable 5 0 SRC_FREQ_SEL 4 0 RESERVED RESERVED 3 0 SRC_SATA SATA PLL Spread Spectrum Enable 0 = Spread off, 1 = Spread on 2 0 Prog_SRC_EN Programmable SRC frequency enable 0 = disabled, 1 = enabled. 1 0 Prog_CPU_EN Programmable CPU frequency enable 0 = disabled, 1 = enabled. 0 0 SRC Frequency selection 0: SRC frequency is selected via the FS_E pin 1: SRC frequency is initially set to 167 MHz. Watchdog Autorecovery Watchdog Autorecovery Mode 0 = Disable (Manual), 1= Enable (Auto) The CY28439 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28439 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 2 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the Figure 2. Crystal Capacitive Clarification Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm Document #: 38-07668 Rev. *D 20 pF Page 10 of 22 PRELIMINARY CY28439 Calculating Load Capacitors Dial-A-Frequency (CPU and SRC) In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. This feature allows the user to overclock their system by slowly stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation Clock Chip Pin 3 to 6p X2 X1 Cs1 Associated Register Bits Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 CPU_DAF Enable—This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note: the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF) CPU_DAF_N—There will be nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000) The allowable values for N are detailed in the frequency select table in Figure 1 Figure 3. Crystal Loading Example CLe “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Figure 1 for the Gear Constant for each Frequency selection. The PCI Express only allows user control of the N register, the M value is fixed and documented in Figure 1 In this mode, the user writes the desired N and M value into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value if required. Ci2 Ci1 Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors CPU DAF M—There will be 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, the allowable values for M are detailed in the frequency select table in Figure 1. SRC_DAF Enable—This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note: the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF) SRC_DAF_N—There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000) The allowable values for N are detailed in the frequency select table in Figure 1. Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) Recovery—The recovery mechanism during CPU DAF when the system locks up and the Watchdog timer is enabled is determined by the “Watchdog Recovery Mode” and “Watchdog Autorecovery Enable” bits. The possible recovery methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW, and (D) No recovery, just send reset signal. CL ................................................... Crystal load capacitance There is no recovery mode for SRC Dial-a-Frequency. CLe .........................................Actual loading seen by crystal using standard value trim capacitors Software Frequency Select Ce .....................................................External trim capacitors This mode allows the user to select the CPU output frequencies using the Software Frequency select bits in the SMBUS register. Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) Document #: 38-07668 Rev. *D FSEL—There will be four bits (for 16 combinations) to select predetermined CPU frequencies from a table. The table selections are detailed in section Figure 1. Page 11 of 22 PRELIMINARY FS_Override—This bit allows the CPU frequency to be selected from HW or FSEL settings. By default, this bit is not set and the CPU frequency is selected by HW. When this bit is set, the CPU frequency is selected by the FSEL bits. Default = 0. Recovery—The recovery mechanism during FSEL when the system locks up is determined by the “Watchdog Recovery Mode” and “Watchdog Autorecovery Enable” bits. The only possible recovery method is to (?) Hardware Settings. Auto recovery or manual recovery can cause a wrong output frequency because the output divider may have changed with the selected CPU frequency and these recovery methods will not recover the original output divider setting. Smooth Switching The device contains one smooth switch circuit which is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the output frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 µs. The frequency overshoot and undershoot will be less than 2%. The Smooth Switch circuit can be assigned to either PLL via register byte 14 bit 4. By default the smooth switch circuit is assigned to the CPU PLL. Either PLL can still be overclocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. It is not recommended to enable overclocking and change the N values of both PLLs in the same SMBUS block write. Watchdog Timer The Watchdog timer is used in the system in conjunction with overclocking. It is used to provide a reset to a system that has hung up due to overclocking the CPU and the Front side bus. The Watchdog is enabled by the user and if the system completes its checkpoints, the system will clear the timer. However, when the timer runs out, there will be a reset pulse generated on the SRESET# pin for 20 ms that is used to reset the system. When the Watchdog is enabled (WD_EN = 1) the Watchdog timer will start counting down from a value of Watchdog_timer * time scale. If the Watchdog timer reaches 0 before the WD_EN bit is cleared then it will assert the SRESET# signal and set the Watchdog Alarm bit to 1. To use the Watchdog the SRESET# pin must be enabled by SRESET_EN pin being sampled low by VTTPWRGD# assertion during system boot-up. At any point if during the Watchdog timer countdown, if the time stamp or Watchdog timer bits are changed the timer will reset and start counting down from the new value. After the Reset pulse, the Watchdog will stay inactive until either: 1. A new time stamp or Watchdog timer value is loaded. 2. The WD_EN bit is cleared and then set again. Document #: 38-07668 Rev. *D CY28439 Watchdog Register Bits The following register bits are associated with the Watchdog timer: Watchdog Enable—This bit (by default) is not set, which disables the Watchdog. When set, the Watchdog is enabled. Also, when there is a transition from LOW to HIGH, the timer reloads. Default = 0, disable Watchdog Timer—There will be three bits (for seven combinations) to select the timer value. Default = 000—the Value '000' is a reserved test mode. Watchdog Alarm—This bit is a flag and when it is set, it indicates that the timer has expired. This bit is not set by default. When the bit is set, the user is allowed to clear. Default = 0. Watchdog Time Scale—This bit selects the multiplier. When this bit is not set, the multiplier will be 250 ms. When set (by default), the multiplier will be 3s. Default = 1. Watchdog Reset Mode—This selects the Watchdog reset mode. When this bit is not set (by default), the Watchdog will send a reset pulse and reload the recovery frequency, which depends on Watchdog Recovery Mode setting. When set, it just sends a reset pulse. Default = 0, Reset & Recover Frequency. Watchdog Recovery Mode—This bit selects the location to recover from. One option is to recover from the HW settings (already stored in SMBUS registers for readback capability) and the second is to recover from a register called “Recovery N”. Default = 0 (Recover from the HW setting) Watchdog Autorecovery Enable—This bit by default is set and the recovered values are automatically written into the “Watchdog Recovery Register” and reloaded by the Watchdog function. When this bit is not set, the user is allowed to write to the “Watchdog Recovery Register”. The value stored in the “Watchdog Recovery Register” will be used for recovery. Default = 1, Autorecovery. Watchdog Recovery Register—This is a nine-bit register to store the Watchdog N recovery value. This value can be written by the Autorecovery or User depending on the state of the “Watchdog Autorecovery Enable bit”. Watchdog Recovery Modes There are two operating modes that requires Watchdog recovery. The modes are Dial-A-Frequency (DAF) or Frequency Select. There are four different recovery modes: The following diagram lists the operating mode and the recovery mode associated with it. Recover to Hardware M,N, O When this recovery mode is selected, in the event of a Watchdog timeout, the original M, N, and O values that were latched by the HW FSEL pins at Chip boot-up should be reloaded. Autorecovery When this recovery mode is selected, in the event of a Watchdog timeout, the M and N values stored in the Recovery M and N registers should be reloaded. The current values of M and N will be latched into the internal recovery M and N registers by the WD_EN bit being set. Page 12 of 22 PRELIMINARY CY28439 Manual Recovery PD (Power-down)—Assertion When this recovery mode is selected, in the event of a Watchdog timeout, the N value as programmed by the user in the N recovery register, and the M value that is stored in the Recovery M register (not accessible by the user) should be restored. The current M value should be latched into the M recovery register by the WD_EN bit being set. When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output is held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tri-state. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, 200, 266, 333, and 400 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 µs after asserting Vtt_PwrGd#. No Recovery If no recovery mode is selected, in the event of a Watchdog time out, the device should just assert the SRESET# and keep the current values of M and N. Software Reset Software reset is a reset function which is used to send out a pulse from SRESET# pin. It is controlled by the SW_RESET enable register bit. Upon completion of the byte/word/block write in which the SW_RESET bit was set, the device will send a RESET pulse on the SRESET# pin. The duration of the SRESET# pulse should be the same as the duration of the SRESET# pulse after a Watchdog timer time out. After the SRESET# pulse is asserted the SW_RESET bit should be automatically cleared by the device. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 µs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform Document #: 38-07668 Rev. *D Page 13 of 22 CY28439 PRELIMINARY Tstable <1.8 ms PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz Tdrive_PWRDN# <300µs >200mV REF Figure 5. Power-down Deassertion Timing Waveform FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen State 0 Clock State W ait for VTT_PW RGD# State 1 State 2 Off Clock Outputs State 3 On On Off Clock VCO Device is not affected, VTT_PW RGD# is ignored Sample Sels Figure 6. VTT_PWRGD# Timing Diagram S2 S1 Delay >0.25 ms VTT_PW RGD# = Low Sample Inputs straps VDD_A = 2.0V W ait for <1.8ms S0 Power Off S3 VDD_A = off Normal Operation Enable Outputs VTT_PW RGD# = toggle Figure 7. Clock Generator Power-up/Run State Diagram Document #: 38-07668 Rev. *D Page 14 of 22 CY28439 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 – V UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 2000 V–0 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V – 1.0 V All VDDs 3.3V Operating Voltage 3.3 ± 5% VILI2C Input Low Voltage SDATA, SCLK VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VIL_FS FS_[A:B,D:E] Input Low Voltage VSS – 0.3 0.35 V 0.7 VDD + 0.5 V 0 0.35 V VIH_FS FS_[A:B,D:E] Input High Voltage VILFS_C FS_C Low Range VIMFS_C FS_C Mid Range 0.7 1.7 V VIH FS_C FS_C High Range 2.1 VDD V VIL 3.3V Input Low Voltage VSS – 0.3 0.8 V VIH 3.3V Input High Voltage 2.0 VDD + 0.3 V IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – µA IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – 5 µA VOL 3.3V Output Low Voltage IOL = 1 mA VOH 3.3V Output High Voltage IOH = –1 mA – 0.4 V 2.4 – V –10 10 µA 3 5 pF IOZ High-impedance Output Current CIN Input Pin Capacitance COUT Output Pin Capacitance 3 5 pF LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD3.3V Dynamic Supply Current At max. load and freq. per Figure 10 – 500 mA IPD3.3V Power-down Supply Current PD asserted, Outputs Driven – 70 mA IPT3.3V Power-down Supply Current PD asserted, Outputs Tri-state – 2 mA Document #: 38-07668 Rev. *D Page 15 of 22 CY28439 PRELIMINARY AC Electrical Specifications Parameter Description Condition Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN Period When XIN is driven from an external clock source TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps LACC Long-term Accuracy Over 150 ms – 300 ppm CPU at 0.7V (SSC refers to –0.5% spread spectrum) TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 ns TPERIOD 166-MHz CPUT and CPUC Period Measured at crossing point VOX 5.998201 6.001801 ns TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.998500 5.001500 ns TPERIOD 266-MHz CPUT and CPUC Period Measured at crossing point VOX 3.748875 3.751125 ns TPERIOD 333-MHz CPUT and CPUC Period Measured at crossing point VOX 2.999100 3.000900 ns TPERIOD 400-MHz CPUT and CPUC Period Measured at crossing point VOX 2.499250 2.500750 ns TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 5.998201 6.031960 ns TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.998500 5.026634 ns TPERIODSS 266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 3.748875 3.769975 ns TPERIODSS 333-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 2.999100 3.015980 ns TPERIODSS 400-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 2.499250 2.513317 ns TPERIODAbs 100-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 9.912001 10.08800 ns TPERIODAbs 133-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 7.412751 7.587251 ns TPERIODAbs 166-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 5.913201 6.086801 ns TPERIODAbs 200-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 4.913500 5.086500 ns TPERIODAbs 266-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 3.663875 3.836125 ns TPERIODAbs 333-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 2.914100 3.085900 ns TPERIODAbs 400-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 2.414250 2.585750 ns TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 9.912001 10.13827 ns TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 7.412751 7.624950 ns TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 5.913201 6.116960 ns TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 4.913500 5.111634 ns TPERIODSSAbs 266-MHz CPUT and CPU C Absolute period, SSC Measured at crossing point VOX 3.663875 3.854975 ns TPERIODSSAbs 333-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 2.914100 3.100980 ns TPERIODSSAbs 400-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 2.414250 2.598317 ns Measured at crossing point VOX – 100 ps TSKEW CPU0 to CPU1 Document #: 38-07668 Rev. *D Page 16 of 22 CY28439 PRELIMINARY AC Electrical Specifications (continued) Min. Max. Unit TCCJ Parameter CPUT/C Cycle to Cycle Jitter Description Measured at crossing point VOX Condition – 80 ps LACC Long Term accuracy Measured using frequency counter over 0.15 seconds. – 300 ppm TR / TF CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 130 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % ∆TR Rise Time Variation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 10 660 850 mV VLOW Voltage Low Math averages Figure 10 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 10. Measure SE – 0.2 V SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODAbs 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX 9.872001 10.12800 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX – 250 ps TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 65 ps LACC SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm TR / TF SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 130 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % ∆TR Rise TimeVariation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 10 660 850 mV VLOW Voltage Low Math averages Figure 10 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage – 0.2 V See Figure 10. Measure SE PCI/PCIF TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V THIGH PCIF and PCI high time 29.49100 30.65980 ns Measurement at 2.4V 12.0 – ns TLOW PCIF and PCI low time Measurement at 0.4V 12.0 – ns Edge Rate Rising edge rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns Edge Rate Falling edge rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns Document #: 38-07668 Rev. *D Page 17 of 22 CY28439 PRELIMINARY AC Electrical Specifications (continued) Min. Max. Unit TSKEW Parameter Any PCI clock to Any PCI clock Skew Description Measurement at 1.5V Condition – 500 ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps DOT TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX – 250 ps LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX – 100 ppm TLTJ Long Term jitter Measurement taken from cross point VOX @1 µs – 700 ps Measurement taken from cross point VOX @10 µs – 700 ps 130 700 ps – 20 % – 125 ps TR / TF DOT96T and DOT96C Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching ∆TR Rise Time Variation ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 10 660 850 mV VLOW Voltage Low Math averages Figure 10 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage – 0.2 V USB48, 24_48M TDC USB Duty Cycle Determined as a fraction of 2*(TR – TF)/(TR + TF) See Figure 10. Measure SE 45 55 % TPERIOD USB Period, Measurement at 1.5V, mean value over 1 µs Measurement at 1.5V 20.83125 20.83542 ns TPERIODabs USB Period Measurement at 1.5V, max. and min. values over 1 µs 20.48125 21.18542 ns TPERIOD24 24M Period Measurement at 1.5V, mean value over 1 µs 41.67083 41.66250 ns TPERIOD24abs 24M Period Measurement at 1.5V, max. and min. values over 1 µs 41.57083 41.76250 ns LACC Long Accuracy Measured at 1.5V using frequency counter over 0.15s – 100 ppm THIGH USB high time (High drive) Measurement at 2.0V 8.094 10.9 ns TLOW USB low time (High drive) Measurement at 0.8V 7.694 11.5 ns THIGH24 24M high time (High drive) Measurement at 2.0V 16.188 22.7 ns TLOW24 24M low time (High drive) Measurement at 0.8V 15.388 22.6 ns Edge rate Rising edge rate (High drive) Measured between 0.8V and 2.0V 1.0 3.0 V/ns Edge rate Falling edge rate (High drive) Measured between 0.8V and 2.0V 1.0 3.0 V/ns TCCJ USB Cycle to Cycle Jitter (High drive) Measurement [email protected] waveform – 300 ps 24_48M Cycle to Cycle Jitter (High drive) Measurement [email protected] waveform – 350 ps Long Term jitter – 700 ps TLTJ Document #: 38-07668 Rev. *D Measurement taken from cross point VOX @ 1 µs Page 18 of 22 CY28439 PRELIMINARY AC Electrical Specifications (continued) Min. Max. Unit TLTJ Parameter Long Term jitter Description Measurement taken from cross point VOX @ 10 µs Condition – 700 ps TLTJ Long Term jitter Measurement taken from cross point VOX @ 125 µs – 700 ps REF TDC REF Duty Cycle Measurement at 1.5V 45 55 ns TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns Edge Rate Rising edge rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns Edge Rate Falling edge rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps – 1.8 ms ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagrams show the test load configurations for the single-ended PCI, USB, and REF output signals. P C I/ USB M e a s u re m e n t P o in t 33Ω 60Ω 5pF M e a s u re m e n t P o in t 12Ω 60Ω REF 5pF M e a s u re m e n t P o in t 12Ω 60Ω 5pF Figure 8. Single-ended Load Configuration 12 Ω 6 0Ω P C I/ USB 1 2Ω 60 Ω 12 Ω 6 0Ω REF 12 Ω 6 0Ω 12 Ω 6 0Ω M e asurem ent P oint 5pF M easu rem ent P oint 5pF M easu rem ent P oint 5pF M easu rem ent P oint 5pF M easu rem ent P oint 5pF Figure 9. Single-ended Load Configuration HIGH DRIVE OPTION Document #: 38-07668 Rev. *D Page 19 of 22 CY28439 PRELIMINARY For Differential CPU, SRC and DOT96 Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs. CPUT SRCT D O T96T CPUC SRCC D O T96C IR E F M e a s u re m e n t P o in t 33Ω 4 9 .9 Ω 2pF 1 0 0 Ω D iff e r e n tia l M e a s u re m e n t P o in t 33Ω 2pF 4 9 .9 Ω 475Ω Figure 10. 0.7V Single-ended Load Configuration 3 .3 V s ig n a l s T DC - - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V TF TR Figure 11. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Package Type Product Flow Lead-free Commercial, 0° to 85°C CY28439OXC 56-pin SSOP CY28439OXCT 56-pin SSOP – Tape and Reel Commercial, 0° to 85°C CY28439ZXC 56-pin TSSOP Commercial, 0° to 85°C CY28439ZXCT 56-pin TSSOP – Tape and Reel Commercial, 0° to 85°C Document #: 38-07668 Rev. *D Page 20 of 22 PRELIMINARY CY28439 Package Diagrams 56-Lead Shrunk Small Outline Package O56 .020 1 28 0.395 0.420 0.292 0.299 29 DIMENSIONS IN INCHES MIN. MAX. 56 0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110 0.005 0.010 .010 GAUGE PLANE 0.110 0.025 BSC 0.008 0.0135 0.024 0.040 0°-8° 0.008 0.016 51-85062-*C 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56 0.249[0.009] 28 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.42gms 5.994[0.236] 6.198[0.244] PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 29 56 13.894[0.547] 14.097[0.555] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° SEATING PLANE 0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] 51-85060-*C Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. Dial-A-Frequency is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07668 Rev. *D Page 21 of 22 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28439 PRELIMINARY Document History Page Document Title: CY28439 Clock Generator for Intel Grantsdale Chipset Document Number: 38-07668 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 214024 See ECN RGL New data sheet *A 268615 See ECN RGL Changed the tri-state mode from 12mA to 2mA Fixed single-ended loading diagram *B 314353 See ECN RGL Swapped pins 19 and 20 swapped pins 50 and 51 *C 321473 See ECN RGL Minor Change: Fixed the line around the block diagram *D 378834 See ECN RGL Changed CPU Cycle-cycle jitter max from 50 to 80 ps Changed CPU Rise/Fall Time min. from 175 to 130 ps Changed SRC Rise/Fall Time min. from 175 to 130 ps Changed DOT Rise/Fall Time min. from 175 to 130 ps Changed DOT Cycle-cycle Jitter max from 150 to 250 ps Changed USB,24_48M Rising/Falling Edge Rate max from 2 to 3 V/ns Changed USB Cycle-cycle Jitter max from 200 to 350 ps Changed USB High Time max from 10.04 to 10.9 ns Changed USB Low Time max from 9.836 to 11.5 ns Changed 24M High Time max from 20.07 to 22.7 ns Changed 24M Low Time max from 19.67 to 22.6 ns Revised the Frequency Select table Document #: 38-07668 Rev. *D Page 22 of 22