CY28443-2 PRELIMINARY Clock Generator for Intel® Calistoga Chipset Features • 33-MHz PCI clock • Low-voltage frequency select input • Supports Intel® Pentium® M CPU • I2C support with readback capabilities • Selectable CPU frequencies • Differential CPU clock pairs • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 100-MHz differential SRC clocks • 3.3V power supply • 48-MHz USB clock • 56-pin package • 96-MHz differential dot clock • Selectable 100-MHz LVDS clock • SRC clocks independently stoppable through CLKREQ#[A:B] CPU SRC PCI REF DOT96 48M SRC/LVDS100M x2 / x3 x5/6/7 x6 x2 x1 x1 x1 Block Diagram XIN XOUT Pin Configuration 14.318MHz Crystal SEL_CLKREQ PCI_STP# CPU PLL CPU_STP# CLKREQ[A:B]# VDD REF[0:1] PLL Reference IREF VDD CPUT[0:1] CPUC[0:1] Divider VDD CPUT2_ITP/SRCT11 CPUC2_ITP/SRCC11 ITP_SEL VDD SRCT([2:5],[8:9]) SRCC([2:5],[8:9]) FS[C:A] VDD PCI[3:5] VDD_PCI LVDS PLL PCIF[0:1] VDD SRCT0/100MT_SST SRCC0/100MC_SST VDD48 Divider 27MSpread FCTSEL1 Fixed PLL VDD48 DOT96T DOT96C Divider VDD48 48M 27M PLL Divider VDD48 27MNon-spread VTT_PWRGD#/PD SDATA SCLK I2C Logic Cypress Semiconductor Corporation Document #: 38-07718 Rev. *B • VDD VSS PCI3 PCI4 PCI5/FCTSEL1 VSS VDD ITP_SEL/PCIF0 PCIF1 VTT_PWRGD#/PD VDD FSA /48M VSS DOT96T/27M non Spread DOT96C/27M Spread FSB SRCT0/100MT_SST SRCC0/100MC_SST SRCT2 SRCC2 VDD SRCT3 SRCC3 SRCT4 SRCC4 SRCT5 _SATA SRCC5_SATA VDD 198 Champion Court • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2/SEL_CLKREQ PCI_STP# CPU_STP# REF0/FSC REF1/FCTSEL0 VSS XIN XOUT VDD SDATA SCLK VSS CPUT0 CPUC0 VDD CPUT1 CPUC1 IREF VSSA VDDA SRCT11/CPUT2_itp SRCC11/CPUC2_itp VDD SRCT9/CLKREQA SRCC9/CLKREQB SRCT8 SRCC8 VSS San Jose, CA 95134-1709 • 408-943-2600 Revised October 17, 2005 CY28443-2 PRELIMINARY Pin Descriptions Pin No. Name Type Description 1, 7, 11, 21, VDD 28, 34, 42, 48 PWR 3.3V power supply 2, 6, 13, 29, 45, 51 VSS GND Ground 33,32 SRCT9/CLKREQA#, SRCC9/CLKREQB# 3,4 PCI[3:4] O, SE 33-MHz clock 5 PCI5/FCTSEL1 O, SE 33-MHz clock/3.3 LVTTL input for selecting SRC[T/C]0 or LVDS100M[T/C] (sampled on the VTT_PWRGD# assertion). 8 ITP_EN/PCIF0 I/O, SE 3.3V LVTTL input to enable SRC[T/C]7 or CPU[T/C]2_ITP/33-MHz clock output. (sampled on the VTT_PWRGD# assertion). 9 PCIF1 I/O, SE 33-MHz clock 10 VTT_PWRGD#/PD 12 FSA/48M 14, 15 DOT96T/27M non Spread DOT96C/27M Spread 16 FSB 17,18 SRC[T/C]0/ LCD100M[T/C] I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz serial reference clock. Default function is SRC9 I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_[C:A], ITP_EN, FCTSEL[1:0], SEL_CLKREQ. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). I/O 3.3V-tolerant input for CPU frequency selection/Fixed 48-MHz clock output. O, DIF Fixed 96-MHz Differential clock/Single-ended 27-MHz clocks. When configured for 27 MHz, only the clock on pin 15 contains spread. I 3.3V-tolerant input for CPU frequency selection. O,DIF 100-MHz Differential Serial Reference clock/100-MHz LVDS Differential clock 19,20,22,23, SRCT/C 24,25,30,31 O, DIF 100-MHz Differential Serial Reference clocks. 26,27 SRC[T/C]5_SATA O, DIF Differential serial reference clock. Recommended output for SATA. 36,35 CPUT2_ITP/SRCT11, O, DIF Selectable differential CPU or SRC clock output. CPUC2_ITP/SRCC11 37 VDDA PWR 3.3V power supply for PLL. 38 VSSA GND Ground for PLL. 39 IREF I 44,43,41,40 CPU[T/C][0:1] 46 SCLK I 47 SDATA I/O 49 XOUT 50 XIN 52 53 A precision resistor is attached to this pin, which is connected to the internal current reference. O, DIF Differential CPU clock outputs. SMBus-compatible SCLOCK. SMBus-compatible SDATA. O, SE 14.318-MHz crystal output. I 14.318-MHz crystal input. REF1 O Fixed 14.318-MHz clock output REF0/FSC I/O 3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output. 54 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active LOW. 55 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active LOW. 56 PCI2/SEL_CLKREQ Document #: 38-07718 Rev. *B I/O, PD Fixed 33-MHz clock output/3.3V-tolerant input for CLKREQ pin selection (sampled on the VTT_PWRGD# assertion). 0 = CLKREQ[A:B]# functionality 1 = SRC[T/C]9 functionality Page 2 of 24 CY28443-2 PRELIMINARY Table 1. Frequency Select Table FSA, FSB and FSC FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF0 DOT96 USB 1 0 1 100 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 1 1 166 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz Frequency Select Pins (FSA, FSB, and FSC) Host clock frequency selection is achieved by applying the appropriate logic levels to FSA, FSB, FSC inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FSA, FSB, and FSC input values. For all logic levels of FSA, FSB, and FSC, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FSA, FSB, and FSC transitions will be ignored, except in test mode. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave Document #: 38-07718 Rev. *B 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Page 3 of 24 CY28443-2 PRELIMINARY Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit .... Description Stop Block Read Protocol Bit Description 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeated start 19 27:20 28 Acknowledge from slave 29 Stop Document #: 38-07718 Rev. *B 9 Description Start 27:21 Write Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Page 4 of 24 CY28443-2 PRELIMINARY Control Registers Byte 0: Control Register 0 Bit 7 6 5 @Pup 1 1 1 Name RESERVED RESERVED SRC[T/C]5 4 1 SRC[T/C]4 3 1 SRC[T/C]3 2 1 SRC[T/C]2 1 0 1 1 RESERVED SRC[T/C]0 /100M[T/C]_SST Description RESERVED RESERVED SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable RESERVED, Set = 1 SRC[T/C]0 /100M[T/C]_SST Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name 7 1 PCIF0 6 1 5 1 USB_48MHz 4 1 REF0 REF0 Output Enable 0 = Disabled, 1 = Enabled 3 1 REF1 REF1 Output Enable 0 = Disabled, 1 = Enabled 2 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled 1 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled 0 0 CPU, SRC, PCI, PCIF spread enable 27M_nss_DOT_96[T/C] Description PCIF0 Output Enable 0 = Disabled, 1 = Enabled 27M nonspread and DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_48M MHz Output Enable 0 = Disabled, 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup Name 7 1 PCI5 PCI5 Output Enable 0 = Disabled, 1 = Enabled 6 1 PCI4 PCI4 Output Enable 0 = Disabled, 1 = Enabled 5 1 PCI3 PCI3 Output Enable 0 = Disabled, 1 = Enabled 4 1 PCI2 PCI2 Output Enable 0 = Disabled, 1 = Enabled 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 CPU[T/C]2 0 1 PCIF1 Document #: 38-07718 Rev. *B Description CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z), 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled Page 5 of 24 CY28443-2 PRELIMINARY Byte 3: Control Register 3 Bit @Pup Name Description 7 0 RESERVED RESERVED, Set = 0 6 0 RESERVED RESERVED, Set = 0 5 0 SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 4 0 SRC4 Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 SRC3 Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC2 Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 RESERVED 0 0 SRC0 RESERVED, Set = 0 Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit @Pup Name 7 0 100M[T/C]_SST Description 6 0 DOT96[T/C] 5 1 SRC[T/C] 4 0 PCIF1 Allow control of PCIF1 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 3 0 PCIF0 Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# 100M[T/C]_SST PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state SRC[T/C] Stop Drive Mode when CLKREQ# asserted 0 = Driven, 1 = Tri-state Byte 5: Control Register 5 Bit @Pup Name 7 0 SRC[T/C] SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted, 1 = Tri-state when PCI_STP# asserted 6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted 5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted 4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted 3 0 SRC[T/C] SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted Document #: 38-07718 Rev. *B Description Page 6 of 24 CY28443-2 PRELIMINARY Byte 5: Control Register 5 (continued) Bit @Pup Name Description 1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL 6 0 TEST_MODE 5 1 REF1 REF0 Output Drive Strength 0 = Low, 1 = High 4 1 REF0 REF0 Output Drive Strength 0 = Low, 1 = High 3 1 2 HW FSC FSC Reflects the value of the FSC pin sampled on power-up 0 = FSC was low during VTT_PWRGD# assertion 1 HW FSB FSB Reflects the value of the FSB pin sampled on power-up 0 = FSB was low during VTT_PWRGD# assertion 0 HW FSA FSA Reflects the value of the FSA pin sampled on power-up 0 = FSA was low during VTT_PWRGD# assertion REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, PCI, PCIF and SRC clock SW PCI_STP Function outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF, and SRC outputs will to free running be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF, and SRC outputs will resume in a synchronous manner with no short pulses. Byte 7: Vendor ID Bit @Pup Name Description 7 0 Revision Code Bit 3 Revision Code Bit 3 6 0 Revision Code Bit 2 Revision Code Bit 2 5 0 Revision Code Bit 1 Revision Code Bit 1 4 1 Revision Code Bit 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 Vendor ID Bit 3 2 0 Vendor ID Bit 2 Vendor ID Bit 2 1 0 Vendor ID Bit 1 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name Description 7 0 CPU_SS 0:–0.5% (Peak to peak) 1: –1.0% (Peak to peak) 6 0 CPU-DWN_SS 0: Down Spread 1: Center Spread 5 0 RESERVED RESERVED, Set = 0 4 0 RESERVED RESERVED, Set = 0 3 0 RESERVED RESERVED, Set = 0 2 1 48M 48-MHz Output Drive Strength 0 = Low, 1 = High Document #: 38-07718 Rev. *B Page 7 of 24 CY28443-2 PRELIMINARY Byte 8: Control Register 8 (continued) Bit @Pup Name Description 1 1 RESERVED RESERVED, Set = 1 0 1 PCIF0 33-MHz Output Drive Strength 0 = Low, 1 = High Byte 9: Control Register 9 Bit @Pup Name Description 7 0 S3 6 0 S2 27_96_100_SSC Spread Spectrum Selection table: S[3:0] SS% 5 0 S1 ‘0000’ = –0.5%(Default value) 4 0 S0 ‘0001’ = –1.0% ‘0010’ = –1.5% ‘0011’ = –2.0% ‘0100’ = ±0.25% ‘0101’ = ±0.5% ‘0110’ = ±0.75% ‘0111’ = ±1.0% ‘1000’ = –0.35% ‘1001’ = –0.68% ‘1010’ = –1.09% ‘1011’ = –1.425% ‘1100’ = ±0.17% ‘1101’ = ±0.34% ‘1110’ = ±0.545% ‘1111’ = ±0.712% 3 1 RESERVED RESERVED, Set = 1 2 1 27M Spread 27-MHz Spread Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 27M_SS/LCD100M Spread Enable 0 1 PCIF1 27M_SS/LCD100M Spread spectrum enable. 0 = Disable, 1 = Enable. 33-MHz Output Drive Strength 0 = Low, 1 = High Byte 10: Control Register 10 Bit @Pup Name Description 7 1 SRC[T/C]11 SRC[T/C]11 Output Enable 0 = Disable (Hi-Z), 1 = Enable 6 1 SRC[T/C]9 SRC[T/C]9 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 RESERVED RESERVED, Set = 1 4 1 SRC[T/C]8 SRC[T/C]8 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 0 SRC[T/C]9 Allow control of SRC[T/C]9 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 2 0 SRC[T/C]11 Allow control of SRC[T/C]11 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# 1 0 RESERVED RESERVED, Set = 0 0 0 SRC[T/C]8 Allow control of SRC[T/C]8 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Document #: 38-07718 Rev. *B Page 8 of 24 CY28443-2 PRELIMINARY Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED Set = 0 6 HW RESERVED RESERVED 5 HW RESERVED RESERVED 4 HW RESERVED RESERVED 3 0 27MHz 27 MHz (spread and non-spread) Output Drive Strength 0 = Low, 1 = High 2 0 RESERVED RESERVED Set = 0 1 0 RESERVED RESERVED Set = 0 0 HW RESERVED RESERVED Byte 12: Control Register 12 Bit @Pup Name Description 7 0 CLKREQ#A CLKREQ#A Enable 0 = Disable 1 = Enable 6 1 CLKREQ#B CLKREQ#B Enable 0 = Disable 1 = Enable 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 13: Control Register 13 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 96/100M Clock Speed 96/100 SRC Clock Speed 0 = 96 MHz 1 = 100 MHz 5 1 RESERVED RESERVED, Set = 1 4 1 RESERVED RESERVED, Set = 1 3 1 PCI5 PCI5 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 2 1 PCI4 PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 1 1 PCI3 PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High 0 1 PCI2 PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High Byte 14: Control Register 14 Bit @Pup Name Description 7 1 RESERVED RESEREVD 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 CLKREQ#A SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#A 1 = SRC[T/C]5 stoppable by CLKREQ#A Document #: 38-07718 Rev. *B Page 9 of 24 CY28443-2 PRELIMINARY Byte 14: Control Register 14 (continued) Bit @Pup Name Description 3 0 CLKREQ#A SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#A 1 = SRC[T/C]4 stoppable by CLKREQ#A 2 0 CLKREQ#A SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#A 1 = SRC[T/C]3 stoppable by CLKREQ#A 1 0 CLKREQ#A SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#A 1 = SRC[T/C]2 stoppable by CLKREQ#A 0 0 CLKREQ#A SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#A 1 = SRC[T/C]1 stoppable by CLKREQ#A Byte 15: Control Register 15 Bit @Pup Name Description 7 1 CLKREQ#B SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#B 1 = SRC[T/C]8 stoppable by CLKREQ#B 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 CLKREQ#B SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#B 1= SRC[T/C]5 stoppable by CLKREQ#B 3 0 CLKREQ#B SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#B 1= SRC[T/C]4 stoppable by CLKREQ#B 2 0 CLKREQ#B SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#B 1= SRC[T/C]3 stoppable by CLKREQ#B 1 0 CLKREQ#B SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#B 1= SRC[T/C]2 stoppable by CLKREQ#B 0 0 CLKREQ#B SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#B 1= SRC[T/C]1 stoppable by CLKREQ#B Table 5. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF The CY28443-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28443-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance Document #: 38-07718 Rev. *B the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Page 10 of 24 CY28443-2 PRELIMINARY Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe Figure 1. Crystal Capacitive Clarification 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ....................................................Crystal load capacitance Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. C lock C hip Ci2 C i1 = Pin 3 to 6p CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CLK_REQ[0:1]# Description The CLKREQ#[A:B] signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ#[A:B] are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) Cs1 X2 X1 Cs2 Trace 2.8 pF XTAL Ce1 C e2 Trim 33 pF Figure 2. Crystal Loading Example All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater than 200 mV. CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ#[A:B] pins is all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ#[A:B] are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform Document #: 38-07718 Rev. *B Page 11 of 24 PRELIMINARY PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding CY28443-2 to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 µs after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 µs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform Tstable <1.8 ms PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF Tdrive_PWRDN# <300 µs, >200 mV Figure 5. Power-down Deassertion Timing Waveform Document #: 38-07718 Rev. *B Page 12 of 24 PRELIMINARY CY28443-2 CPU_STP# Assertion CPU_STP# Deassertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two–six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to 6 x (Iref), and the CPUC signal will be tri-stated. The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CPU_STP# CPUT CPUC Figure 6. CPU_STP# Assertion Waveform CPU_STP# CPUT CPUC CPUT Internal CPUC Internal Tdrive_CPU_STP#,10 ns > 200 mV Figure 7. CPU_STP# Deassertion Waveform 1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven Document #: 38-07718 Rev. *B Page 13 of 24 PRELIMINARY CY28443-2 1.8 ms CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion PCI_STP# Deassertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level. Tsu PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI_STP# Assertion Waveform Tsu Tdrive_SRC PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform Document #: 38-07718 Rev. *B Page 14 of 24 CY28443-2 PRELIMINARY FS_A, FS_B,FS_C VTT_PWRGD# PWRGD_VRM 0.2-0.3 ms Delay VDD Clock Gen Clock State State 0 Wait for VTT_PWRGD# State 1 State 2 Off Clock Outputs State 3 On On Off Clock VCO Device is not affected, VTT_PWRGD# is ignored Sample Sels Figure 12. VTT_PWRGD# Timing Diagram S2 S1 VTT_PWRGD# = Low Delay >0.25 ms Sample Inputs straps VDD_A = 2.0V Wait for <1.8ms S0 Power Off S3 VDD_A = off Normal Operation Enable Outputs VTT_PWRGD# = toggle Figure 13. Clock Generator Power-up/Run State Diagram Document #: 38-07718 Rev. *B Page 15 of 24 CY28443-2 PRELIMINARY 1 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 0 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 – V UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 2000 V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description Condition All VDD’s 3.3V Operating Voltage 3.3 ± 5% VILI2C Input Low Voltage SDATA, SCLK VIHI2C Input High Voltage SDATA, SCLK VIL_FS FS_[A,B] Input Low Voltage Min. Max. Unit 3.135 3.465 V – 1.0 V 2.2 – V VSS – 0.3 0.35 V 0.7 VDD + 0.5 V VSS – 0.3 0.35 V VIH_FS FS_[A,B] Input High Voltage VILFS_C FS_C Input Low Voltage VIMFS_C FS_C Input Middle Voltage Typical 0.7 1.7 V VIHFS_C FS_C Input High Voltage Typical 2.0 VDD + 0.5 V VIL 3.3V Input Low Voltage VSS – 0.3 0.8 V VIH 3.3V Input High Voltage 2.0 VDD + 0.3 V IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 5 µA IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – 5 µA VOL 3.3V Output Low Voltage IOL = 1 mA VOH 3.3V Output High Voltage IOH = –1 mA IOZ High-impedance Output Current CIN COUT LIN Pin Inductance VXIH Xin High Voltage VXIL Xin Low Voltage IDD3.3V Dynamic Supply Current At max. load and freq. per Figure 16 IPD3.3V Power-down Supply Current IPD3.3V Power-down Supply Current – 0.4 V 2.4 – V –10 10 µA Input Pin Capacitance 3 5 pF Output Pin Capacitance 3 6 pF Document #: 38-07718 Rev. *B – 7 nH 0.7VDD VDD V 0 0.3VDD V – 300 mA PD asserted, Outputs Driven – 70 mA PD asserted, Outputs Tri-state – 5 mA Page 16 of 24 CY28443-2 PRELIMINARY AC Electrical Specifications Parameter Description Condition Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns ns Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification TPERIOD XIN Period When XIN is driven from an external clock source TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps LACC Long-term Accuracy Measured at crossing point VOX – 300 ppm TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 % CPU at 0.7V TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 ns TPERIOD 166-MHz CPUT and CPUC Period Measured at crossing point VOX 5.998201 6.001801 ns TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.998500 5.001500 ns TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 5.998201 6.031960 ns TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.998500 5.026634 ns TPERIODAbs 100-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 9.912001 10.08800 ns TPERIODAbs 133-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 7.412751 7.587251 ns TPERIODAbs 166-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 5.913201 6.086801 ns TPERIODAbs 200-MHz CPUT and CPUC Absolute period Measured at crossing point VOX 4.913500 5.086500 ns TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 9.912001 10.13827 ns TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 7.412751 7.624950 ns TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 5.913201 6.116960 ns TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC Measured at crossing point VOX 4.913500 5.111634 ns TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 85[1] ps TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX – 125[1] ps LACC Long-term Accuracy Measured at crossing point VOX – 300 ppm TSKEW CPU1 to CPU0 Clock Skew Measured at crossing point VOX – 100 ps TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX TR / TF CPUT and CPUC Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ∆TR ∆TF – 150 ps 175 700 ps – 20 % Rise Time Variation – 125 ps Fall Time Variation – 125 ps Note: 1. Measured with one REF on. Document #: 38-07718 Rev. *B Page 17 of 24 CY28443-2 PRELIMINARY AC Electrical Specifications (continued) Condition Min. Max. Unit VHIGH Parameter Voltage High Description Math averages Figure 16 660 850 mV VLOW Voltage Low Math averages Figure 16 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 16. Measure SE – 0.2 V TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 % SRC at 0.7V TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODAbs 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX 9.872001 10.12800 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX – 250 ps TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125[1] ps LACC SRCT/C Long Term Accuracy Measured at crossing point VOX TR / TF SRCT and SRCC Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ∆TR Rise TimeVariation ∆TF Fall Time Variation VHIGH Voltage High Math averages Figure 16 VLOW Voltage Low Math averages Figure 16 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage VRB Ring Back Voltage – 300 ppm 175 700 ps – 20 % – 125 ps – 125 ps 660 850 mV –0.3 – V See Figure 16. Measure SE – 0.2 V 96_100_SSC/SRC0 at 0.7V TDC SSCT and SSCC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD 100-MHz SSCT and SSCC Period Measured at crossing point VOX 9.997001 10.00300 ns TPERIODSS 100-MHz SSCT and SSCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODAbs 100-MHz SSCT and SSCC Absolute Period Measured at crossing point VOX 9.872001 10.12800 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns TPERIOD 96-MHz SSCT and SSCC Period Measured at crossing point VOX 10.41354 10.41979 ns TPERIODSS 96-MHz SSCT and SSCC Period, SSC Measured at crossing point VOX 10.41354 10.47215 ns TPERIODAbs 96-MHz SSCT and SSCC Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns TPERIODSSAbs 96-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 10.16354 10.72266 ns TCCJ SSCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 140 ps LACC SSCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm Document #: 38-07718 Rev. *B Page 18 of 24 CY28443-2 PRELIMINARY AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 175 700 ps – 20 % – 125 ps – 125 ps 660 850 mV TR / TF SSCT and SSCC Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ∆TR Rise TimeVariation ∆TF Fall Time Variation VHIGH Voltage High Math averages Figure 16 VLOW Voltage Low Math averages Figure 16 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage VRB Ring Back Voltage –0.3 – V See Figure 16. Measure SE – 0.2 V PCI/PCIF at 3.3V TDC PCI Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns THIGH PCIF and PCI high time Measurement at 2.4V 12.0 – ns TLOW PCIF and PCI low time Measurement at 0.4V 12.0 – ns TR / TF PCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps ps TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500[2] LACC PCIF/PCI Long Term Accuracy Measured at crossing point VOX – 300 ppm TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 % DOT96 at 0.7V TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX – 250 ps LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX – 300 ppm TR / TF DOT96T and DOT96C Rise and Fall Time Measured from VOL = 0.175 to VOH = 0.525V 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % ∆TR Rise Time Variation – 125 ps ∆TF Fall Time Variation – 125 ps VHIGH Voltage High Math averages Figure 16 660 850 mV VLOW Voltage Low Math averages Figure 16 –150 – mV VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage – 0.2 V See Figure 16. Measure SE Note: 2. Measured in Low drive mode. Document #: 38-07718 Rev. *B Page 19 of 24 CY28443-2 PRELIMINARY AC Electrical Specifications (continued) Parameter Description Condition Min. Max. Unit 48_M at 3.3V TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns THIGH 48_M High time Measurement at 2.4V 8.094 11.200 ns TLOW 48_M Low time Measurement at 0.4V 7.694 11.500 ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 2.0 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps LACC 48M Long Term Accuracy Measured at crossing point VOX – 100 ppm TDC Duty Cycle Measurement at 1.5V 45 55 % TPERIOD Spread Disabled 27M Period Measurement at 1.5V 27.000 27.0547 ns Spread Enabled 27M Period Measurement at 1.5V 27.000 27.0547 27_M at 3.3V THIGH 27_M High time Measurement at 2.0V 10.5 – ns TLOW 27_M Low time Measurement at 0.8V 10.5 – ns TR / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.4 V/ns TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 520 ps LACC 27_M Long Term Accuracy Measured at crossing point VOX – 0 ppm TDC REF Duty Cycle Measurement at 1.5V 45 55 % TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns TR / TF REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns TSKEW REF Clock to REF Clock Measurement at 1.5V – 500 ps TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps LACC Long Term Accuracy Measurement at 1.5V – 300 ppm – 1.8 ms 10.0 – ns REF at 3.3V ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS Stopclock Set-up Time Document #: 38-07718 Rev. *B Page 20 of 24 CY28443-2 PRELIMINARY Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows test load configurations for the single-ended PCI, USB, and REF output signals. Measurement Point 33Ω PCI/ USB 60Ω 5 pF Measurement Point 12Ω 60Ω REF 5 pF Measurement Point 12Ω 60Ω 5 pF Figure 14.Single-ended Load Configuration Low Drive Option M easurem ent P oint 12Ω 60Ω PCI/ USB 5 pF M easurem ent P oint 12Ω 60Ω 5 pF M easurem ent P oint 12Ω 60Ω R EF 5 pF M easurem ent P oint 12Ω 60Ω 5 pF M easurem ent P oint 12Ω 60Ω 5 pF Figure 15. Single-ended Load Configuration High Drive Option The following diagram shows the test load configuration for the differential CPU and SRC outputs. CPUT SRCT D O T96T 96_100_SSC T CPUC SRCC D O T96C 96_100_SSC C M e a s u re m e n t P o in t 33Ω 4 9 .9 Ω 2 pF 1 0 0 Ω D if f e r e n t ia l M e a s u re m e n t P o in t 33Ω 4 9 .9 Ω 2 pF IR E F 475Ω Figure 16. 0.7V Differential Load Configuration Document #: 38-07718 Rev. *B Page 21 of 24 CY28443-2 PRELIMINARY 3 .3 V s ig n a l s T DC - - 3 .3 V 2 .4 V 1 .5 V 0 .4 V 0V TF TR Figure 17. Single-ended Output Signals (for AC Parameters Measurement) Ordering Information Part Number Package Type Product Flow Lead-free CY28443OXC-2 56-pin SSOP Commercial, 0° to 85°C CY28443OXC-2T 56-pin SSOP – Tape and Reel Commercial, 0° to 85°C CY28443ZXC-2 56-pin TSSOP Commercial, 0° to 85°C CY28443ZXC-2T 56-pin TSSOP – Tape and Reel Commercial, 0° to 85°C Document #: 38-07718 Rev. *B Page 22 of 24 CY28443-2 PRELIMINARY Package Diagrams 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56 0.249[0.009] 28 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.42gms 5.994[0.236] 6.198[0.244] PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 29 56 13.894[0.547] 14.097[0.555] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] 0.170[0.006] 0.279[0.011] 0.508[0.020] 0.762[0.030] 0°-8° 0.100[0.003] 0.200[0.008] SEATING PLANE 51-85060-*C 56-Lead Shrunk Small Outline Package O56 .020 1 28 0.395 0.420 0.292 0.299 DIMENSIONS IN INCHES MIN. MAX. 29 56 0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110 0.005 0.010 .010 GAUGE PLANE 0.110 0.025 BSC 0.008 0.0135 0.008 0.016 0°-8° 0.024 0.040 51-85062-*C Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07718 Rev. *B Page 23 of 24 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28443-2 PRELIMINARY Document History Page Document Title: CY28443-2 Clock Generator for Intel® Calistoga Chipset Document Number: 38-07718 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 285670 See ECN RGL New data sheet *A 318716 See ECN RGL Corrected the register mappings to reflect the changes in EROS *B 402316 See ECN Document #: 38-07718 Rev. *B RGL/XLZ Change the document status to Preliminary Update register table Add Figure 15 and 16 for single-ended load configuration Update DC Electrical Specification table Update AC Electrical Specification table Page 24 of 24