CY62158E MoBL® 8-Mbit (1 M × 8) Static RAM 8-Mbit (1 M × 8) Static RAM Features ■ Very high speed: 45 ns ❐ Wide voltage range: 4.5 V–5.5 V applications. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). ■ Ultra low active power ❐ Typical active current:1.8 mA at f = 1 MHz ❐ Typical active current: 18 mA at f = fmax To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). ■ Ultra low standby power ❐ Typical standby current: 2 A ❐ Maximum standby current: 8 A ■ Easy memory expansion with CE1, CE2 and OE features To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Offered in Pb-free 44-pin TSOP II package The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table on page 11 for a complete description of read and write modes. Functional Description The CY62158E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. The CY62158E MoBL® is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable Logic Block Diagram SENSE AMPS ROW DECODER I/O11 IO 1024K x 8 ARRAY I/O22 IO I/O33 IO I/O44 IO I/O55 IO I/O66 IO A15 A16 A17 A13 A14 OE • POWER DOWN I/O77 IO A19 COLUMN DECODER WE Cypress Semiconductor Corporation Document Number: 38-05684 Rev. *I I/O00 IO DATA IN DRIVERS A18 CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 10, 2013 CY62158E MoBL® Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document Number: 38-05684 Rev. *I Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Page 2 of 16 CY62158E MoBL® Pin Configuration Figure 1. 44-pin TSOP II pinout (Top View) [1] A4 A3 A2 A1 A0 CE1 NC NC I/O0 I/O1 VCC VSS I/O2 I/O3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 A5 A6 A7 OE CE2 A8 NC NC I/O7 I/O6 VSS 33 32 31 30 29 28 27 26 25 24 23 VCC I/O5 I/O4 NC NC A9 A10 A11 A12 A13 A14 Product Portfolio Power Dissipation Product VCC Range (V) Speed (ns) Operating ICC (mA) f = 1 MHz CY62158ELL Min Typ [2] Max 4.5 5.0 5.5 45 Standby ISB2 (A) f = fmax Typ [2] Max Typ [2] Max Typ [2] Max 1.8 3 18 25 2 8 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 38-05684 Rev. *I Page 3 of 16 CY62158E MoBL® DC Input Voltage [3, 4] ..................–0.5 V to VCC(max) + 0.5 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied ......................................... –55 °C to +125 °C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch up Current .................................................... > 200 mA Operating Range Supply Voltage to Ground Potential .......................... –0.5 V to VCC(max) + 0.5 V DC Voltage Applied to Outputs in High Z State [3, 4] ......................–0.5 V to VCC(max) + 0.5 V Device Range CY62158ELL Industrial Ambient Temperature VCC [5] –40 °C to +85 °C 4.5 V–5.5 V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions -45 Min Typ [6] Max Unit V VCC = 4.5 V IOH = –1 mA 2.4 – – VCC = 5.5 V IOH = –0.1mA – – 3.4 [7] VOL Output LOW Voltage IOL = 2.1 mA – – 0.4 V VIH Input HIGH Voltage VCC = 4.5 V to 5.5 V 2.2 – VCC + 0.5 V V VIIL Input LOW Voltage VCC = 4.5 V to 5.5 V –0.5 – 0.8 V IIX Input Leakage Current GND < VI < VCC –1 – +1 A IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 – +1 A ICC VCC Operating Supply Current f = fMAX = 1/tRC VCC = VCC(max) IOUT = 0 mA CMOS levels – 18 25 mA 1.8 3 mA f = 1 MHz ISB1 Automatic CE Power down Current — CMOS Inputs CE1 > VCC0.2 V, CE2 < 0.2 V VIN > VCC – 0.2 V, VIN < 0.2 V f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = VCCmax – 2 8 A ISB2 [8] Automatic CE Power-down Current — CMOS Inputs CE1 > VCC – 0.2 V or CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCCmax – 2 8 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Please note that the maximum VOH limit doesnot exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider. 8. Chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05684 Rev. *I Page 4 of 16 CY62158E MoBL® Capacitance Parameter [9] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [9] Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions 44-pin TSOP II Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 75.13 C/W 8.95 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 3V R2 100 pF GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 5.0 V Unit R1 1838 R2 994 RTH 645 VTH 1.75 V Note 9. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05684 Rev. *I Page 5 of 16 CY62158E MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for Data Retention [11] Data Retention Current VCC = VDR CE1 > VCC 0.2 V, CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Min Typ [10] Max Unit 2 – – V – – 8 A tCDR [12] Chip Deselect to Data Retention Time 0 – – ns tR [13] Operation Recovery Time 45 – – ns Data Retention Waveform Figure 3. Data Retention Waveform VCC VCC(min) tCDR DATA RETENTION MODE VDR > 2.0 V VCC(min) tR CE1 or CE2 Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document Number: 38-05684 Rev. *I Page 6 of 16 CY62158E MoBL® Switching Characteristics Over the Operating Range Parameter [14] Description 45 ns Unit Min Max Read Cycle Time 45 – ns tAA Address to Data Valid – 45 ns tOHA Data Hold from Address Change 10 – ns tACE CE1 LOW and CE2 HIGH to Data Valid – 45 ns tDOE OE LOW to Data Valid – 22 ns 5 – ns – 18 ns 10 – ns – 18 ns ns Read Cycle tRC [15] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z [15, 16] tLZCE CE1 LOW and CE2 HIGH to Low Z [15] tHZCE CE1 HIGH or CE2 LOW to High Z [15, 16] tPU CE1 LOW and CE2 HIGH to Power Up 0 – tPD CE1 HIGH or CE2 LOW to Power Down – 45 ns Write Cycle Time 45 – ns ns Write Cycle [17] tWC tSCE CE1 LOW and CE2 HIGH to Write End 35 – tAW Address Setup to Write End 35 – ns tHA Address Hold from Write End 0 – ns tSA Address Setup to Write Start 0 – ns ns tPWE WE Pulse Width 35 – tSD Data Setup to Write End 25 – ns tHD Data Hold from Write End 0 – ns WE LOW to High Z [15, 16] – 18 ns WE HIGH to Low Z [15] 10 – ns tHZWE tLZWE Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Figure 2 on page 5. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document Number: 38-05684 Rev. *I Page 7 of 16 CY62158E MoBL® Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [18, 19] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [19, 20] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 18. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document Number: 38-05684 Rev. *I Page 8 of 16 CY62158E MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled) [21, 22, 23] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE OE tSD DATA I/O tHD VALID DATA NOTE 24 tHZOE Figure 7. Write Cycle No. 2 (CE1 or CE2 Controlled) [21, 22, 23] tWC ADDRESS tSCE CE1 tSA CE2 tAW tHA tPWE WE OE tSD DATA I/O tHD VALID DATA Notes 21. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 22. Data I/O is high impedance if OE = VIH. 23. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 24. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05684 Rev. *I Page 9 of 16 CY62158E MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [25] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD DATA I/O NOTE 26 tHD VALID DATA tHZWE tLZWE Notes 25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 26. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05684 Rev. *I Page 10 of 16 CY62158E MoBL® Truth Table CE1 WE OE [27] X X High Z Deselect/Power Down Standby (ISB) [27] L X X High Z Deselect/Power Down Standby (ISB) L H H L Data Out Read Active (ICC) L H H H High Z Output Disabled Active (ICC) L H L X Data in Write Active (ICC) H X CE2 X Inputs/Outputs Mode Power Note 27. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 38-05684 Rev. *I Page 11 of 16 CY62158E MoBL® Ordering Information Speed (ns) 45 Package Diagram Ordering Code CY62158ELL-45ZSXI Package Type 51-85087 44-pin TSOP II (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of this part. Ordering Code Definitions CY 621 5 8 E LL - 45 ZS X I Temperature Grade: I = Industrial Pb-free Package Type: ZS = 44-pin TSOP II Speed Grade: 45 ns LL = Low Power Process Technology: 90 nm Bus width = × 8 Density = 8-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05684 Rev. *I Page 12 of 16 CY62158E MoBL® Package Diagrams Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05684 Rev. *I Page 13 of 16 CY62158E MoBL® Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable A microampere SRAM Static Random Access Memory s microsecond TSOP Thin Small Outline Package mA milliampere WE Write Enable ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 38-05684 Rev. *I Symbol Unit of Measure Page 14 of 16 CY62158E MoBL® Document History Page Document Title: CY62158E MoBL®, 8-Mbit (1 M × 8) Static RAM Document Number: 38-05684 Rev. ECN No. Issue Date Orig. of Change ** 270350 See ECN PCI New data sheet. *A 291271 See ECN SYT Converted from Advance Information to Preliminary Changed input pulse level from VCC to 3V in the AC Test Loads and Waveforms Modified footnote #9 to include timing reference level of 1.5V and input pulse level of 3V *B 1462592 See ECN VKN / AESA Converted from preliminary to final Removed 35 ns speed bin Removed “L” parts Removed 48-Ball VFBGA package Changed ICC(max) spec from 2.3 mA to 3 mA at f=1 MHz Changed ICC(typ) spec from 16 mA to 18 mA at f=fMAX Changed ICC(max) spec from 28 mA to 25 mA at f=fMAX Changed ISB1(typ) and ISB2(typ) spec from 0.9 A to 2 A Changed ISB1(max) and ISB2(max) spec from 4.5 A to 8 A Changed ICCDR(max) spec from 4.5 A to 8 A Changed tLZOE spec from 3 ns to 5 ns Changed tLZCE spec from 6 ns to 10 ns Changed tHZCE spec from 22 ns to 18 ns Changed tPWE spec from 30 ns to 35 ns Changed tSD spec from 22 ns to 25 ns Changed tLZWE spec from 6 ns to 10 ns Added footnote# 6 related to ISB2 and ICCDR Updated Ordering information table *C 2428708 See ECN VKN / PYRS Corrected typo in the Ordering Information table *D 2516494 See ECN PYRS *E 2934396 06/03/10 VKN *F 3110202 12/14/2010 PRAS Updated Logic Block Diagram. Added Ordering Code Definitions. *G 3121955 12/28/2010 SRIH Updated the missing header and footer in Pg 12. *H 3279426 06/10/2011 RAME Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines”). Updated Data Retention Characteristics. Added Acronyms and Units of Measure. Updated in new template. *I 4024759 06/10/2013 MEMJ Updated Functional Description. Description of Change Corrected ECN number Added footnote #19 related to chip enable Updated package diagram Updated template Updated Electrical Characteristics: Added one more Test Condition “VCC = 5.5 V, IOH = –0.1 mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 7 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “VCC = 5.5 V, IOH = –0.1 mA”. Updated Package Diagrams: spec 51-85087 – Changed revision from *C to *E. Document Number: 38-05684 Rev. *I Page 15 of 16 CY62158E MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. 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Document Number: 38-05684 Rev. *I Revised June 10, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16