CY62256N 256 K (32 K × 8) Static RAM 256K (32K × 8) Static RAM Features Functional Description ■ Temperature ranges ❐ Commercial: 0 °C to +70 °C ❐ Industrial: –40 °C to +85 °C ❐ Automotive-A: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ High speed: 55 ns ■ Voltage range: 4.5 V to 5.5 V operation ■ Low active power ❐ 275 mW (max) ■ Low standby power (LL version) ❐ 82.5 μW (max) ■ Easy memory expansion with CE and OE Features ■ TTL-compatible inputs and outputs ■ Automatic power-down when deselected ■ CMOS for optimum speed and power The CY62256N is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9 percent when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. ■ Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) narrow SOIC, 28-pin TSOP-I, and 28-pin reverse TSOP-I packages Logic Block Diagram I/O0 INPUTBUFFER I/O1 32K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 I/O3 I/O4 I/O5 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 Cypress Semiconductor Corporation Document Number: 001-06511 Rev. *F • A12 A11 A1 A0 A13 A14 OE 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 9, 2011 CY62256N Contents Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 6 Typical DC and AC Characteristics ................................ 9 Truth Table ...................................................................... 10 Document Number: 001-06511 Rev. *F Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Reference Information ................................................... 14 Acronyms .................................................................. 14 Document Conventions ............................................. 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Page 2 of 16 CY62256N Product Portfolio VCC Range (V) Product CY62256NLL CY62256NLL CY62256NLL CY62256NLL Commercial Industrial Automotive-A Automotive-E Min 4.5 Typ[1] 5.0 Speed (ns) Max 5.5 70 55/70 55/70 55 Power Dissipation Operating, ICC Standby, ISB2 (μA) (mA) [1] Typ Max Typ[1] Max 25 50 0.1 5 25 50 0.1 10 25 50 0.1 10 25 50 0.1 15 Pin Configurations Figure 1. 28-pin DIP and Narrow SOIC Figure 2. 28-pin TSOP I and Reverse TSOP I Table 1. Pin Definitions Pin Number 1–10, 21, 23–26 11–13, 15–19, 27 Type Input Input/Output Input/Control 20 22 Input/Control Input/Control 14 28 Ground Power Supply Description A0–A14. Address Inputs I/O0–I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins GND. Ground for the device VCC. Power supply for the device Note 1. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document Number: 001-06511 Rev. *F Page 3 of 16 CY62256N Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, method 3015) Storage temperature ................................ –65 °C to +150 °C Latch-up current .................................................... > 200 mA Ambient temperature with power applied ........................................... –55 °C to +125 °C Operating Range Supply voltage to ground potential (pin 28 to pin 14)...........................................–0.5 V to +7.0 V DC voltage applied to outputs in high Z State[2] .................................. –0.5 V to VCC + 0.5 V DC input voltage[2] ............................... –0.5 V to VCC + 0.5 V Range Ambient Temperature (TA)[3] VCC 0 °C to +70 °C 5 V ± 10% –40 °C to +85 °C 5 V ± 10% Automotive-A –40 °C to +85 °C 5 V ± 10% Automotive-E –40 °C to +125 °C 5 V ± 10% Commercial Industrial Output current into outputs (LOW) .............................. 20 mA Electrical Characteristics Over the Operating Range Parameter Description –55 Test Conditions VOH Output HIGH voltage VCC = Min, IOH = −1.0 mA VCC = Min, IOL = 2.1 mA –70 Unit Min Typ[4] Max Min Typ[4] Max 2.4 – – 2.4 – – V VOL Output LOW voltage – – 0.4 – – 0.4 V VIH Input HIGH voltage 2.2 – VCC + 0.5 V 2.2 – VCC + 0.5 V V VIL Input LOW voltage –0.5 – 0.8 –0.5 – 0.8 V –0.5 – +0.5 –0.5 – +0.5 μA –0.5 – +0.5 –0.5 – +0.5 μA GND ≤ VI ≤ VCC IIX Input leakage current IOZ Output leakage current GND ≤ VO ≤ VCC, output disabled ICC VCC operating supply current ISB1 ISB2 Automatic CE power-down current— TTL inputs Automatic CE power-down current— CMOS inputs VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC LL-Commercial – – – – 25 50 mA LL - Industrial – 25 50 – 25 50 mA LL - Automotive-A – 25 50 – 25 50 mA LL - Automotive-E – 25 50 – – – mA Max. VCC, CE ≥ VIH, LL-Commercial VIN ≥ VIH or VIN ≤ VIL, LL - Industrial f = fMAX LL - Automotive-A – – – – 0.3 0.5 mA – 0.3 0.5 – 0.3 0.5 mA – 0.3 0.5 – 0.3 0.5 mA LL - Automotive-E – 0.3 0.5 – – – mA Max. VCC, LL - Commercial CE ≥ VCC − 0.3 V LL - Industrial VIN ≥ VCC − 0.3 V, or LL - Automotive-A VIN ≤ 0.3 V, f = 0 LL - Automotive-E – – – – 0.1 5 μA – 0.1 10 – 0.1 10 μA – 0.1 10 – 0.1 10 μA – 0.1 15 – – – μA Capacitance Parameter[5] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 5.0 V Max Unit 6 pF 8 pF Notes 2. VIL (min) = −2.0 V for pulse durations of less than 20 ns. 3. TA is the “Instant-On” case temperature. 4. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. 5. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-06511 Rev. *F Page 4 of 16 CY62256N Thermal Resistance Parameter[6] Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) Test Conditions DIP SOIC TSOP RTSOP Unit Still air, soldered on a 4.25 × 1.125 inch, 4-layer printed circuit board 75.61 76.56 93.89 93.89 °C/W 43.12 36.07 24.64 24.64 °C/W Figure 3. AC Test Loads and Waveforms R1 1800 Ω R1 1800 Ω 5V 5V OUTPUT OUTPUT R2 990Ω 100 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0 V INCLUDING JIG AND SCOPE (a) R2 990Ω 5 pF 90% 10% 90% 10% GND ≤ 5 ns < 5 ns (b) Equivalent to: THÉVENIN EQUIVALENT 639Ω OUTPUT 1.77 V Data Retention Characteristics Parameter Conditions[7] Description VDR VCC for data retention ICCDR Data retention current LL – Commercial LL – Industrial/ Automotive-A VCC = 2.0 V, CE ≥ VCC − 0.3 V, VIN ≥ VCC − 0.3 V, or VIN ≤ 0.3 V LL – Automotive-E tCDR [7] Chip deselect to data retention time tR[7] Operation recovery time Min Typ[8] Max Unit 2.0 – – V – 0.1 5 μA – 0.1 10 μA – 0.1 10 μA 0 – – ns CY62256NLL-55 55 – – ns CY62256NLL-70 70 – – Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR ≥ 2 V 3.0 V tR CE Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. No input may exceed VCC + 0.5 V. 8. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25 °C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document Number: 001-06511 Rev. *F Page 5 of 16 CY62256N Switching Characteristics Over the Operating Range Parameter[9] CY62256N-55 Description Min CY62256N-70 Max Min Max Unit Read Cycle tRC Read cycle time 55 – 70 – ns tAA Address to data valid – 55 – 70 ns tOHA Data hold from address change 5 – 5 – ns tACE CE LOW to data valid – 55 – 70 ns tDOE OE LOW to data valid – 25 – 35 ns tLZOE OE LOW to low Z[10] 5 – 5 – ns – 20 – 25 ns 5 – 5 – ns [10, 11] OE HIGH to high Z tHZOE CE LOW to low tLZCE Z[10] Z[10, 11] tHZCE CE HIGH to high – 20 – 25 ns tPU CE LOW to power-up 0 – 0 – ns CE HIGH to power-down – 55 – 70 ns tPD Write Cycle [12, 13] tWC Write cycle time 55 – 70 – ns tSCE CE LOW to write end 45 – 60 – ns tAW Address setup to write end 45 – 60 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 40 – 50 – ns tSD Data setup to write end 25 – 30 – ns tHD Data hold from write end 0 – 0 – ns Z[10, 11] – 20 – 25 ns 5 – 5 – ns tHZWE WE LOW to high tLZWE WE HIGH to low Z[10] Switching Waveforms Figure 5. Read Cycle No. 1[14, 15] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 11. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 12. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 13. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. Document Number: 001-06511 Rev. *F Page 6 of 16 CY62256N Switching Waveforms (continued) Figure 6. Read Cycle No. 2[16, 17] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Figure 7. Write Cycle No. 1 (WE Controlled)[18, 19, 20] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 21 tHD DATAIN VALID tHZOE Figure 8. Write Cycle No. 2 (CE Controlled)[18, 19, 20] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAIN VALID Notes 16. WE is HIGH for Read cycle. 17. Address valid prior to or coincident with CE transition LOW. 18. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 19. Data I/O is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 21. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 001-06511 Rev. *F Page 7 of 16 CY62256N Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)[22, 23] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O NOTE 24 tHD DATAIN VALID tHZWE tLZWE Notes 22. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 23. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 24. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 001-06511 Rev. *F Page 8 of 16 CY62256N Typical DC and AC Characteristics 1.4 1.0 0.8 0.6 VIN = 5.0V TA = 25°C 0.4 2.5 1.0 2.0 0.8 0.6 VCC = 5.0V VIN = 5.0V 0.4 4.5 5.0 5.5 25 SUPPLY VOLTAGE (V) 1.3 1.4 NORMALIZED tAA NORMALIZED tAA 1.6 1.2 1.1 TA = 25°C 1.0 0.9 5.5 6.0 1.2 1.0 VCC = 5.0V 0.6 −55 25 125 OUTPUT SOURCE CURRENT (mA) 105 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 VCC = 5.0V TA = 25°C 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 25 AMBIENT TEMPERATURE (°C) 0.8 5.0 –0.5 −55 125 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.4 4.5 VCC = 5.0V VIN = 5.0V AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 0.8 4.0 1.0 0.0 0.0 −55 6.0 ISB 1.5 0.5 0.2 ISB 0.0 4.0 1.2 OUTPUT SINK CURRENT (mA) 0.2 3.0 ICC ISB2 μA 1.2 NORMALIZED ICC NORMALIZED ICC, ISB 1.4 ICC STANDBY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 VCC = 5.0V TA = 25°C 60 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Document Number: 001-06511 Rev. *F Page 9 of 16 CY62256N Typical DC and AC Characteristics TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 2.0 1.5 1.0 0.5 0.0 0.0 1.25 20.0 15.0 VCC = 4.5 V TA = 25 °C 10.0 5.0 1.0 2.0 3.0 4.0 5.0 0.0 0 SUPPLY VOLTAGE (V) 200 400 600 800 1000 CAPACITANCE (pF) NORMALIZED ICC 3.0 DELTA tAA (ns) NORMALIZED IPO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE (continued) NORMALIZED ICC vs. CYCLE TIME 1.00 VCC = 5.0 V TA = 25 °C VIN = 5.0 V 0.75 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Truth Table CE WE OE H X X High Z Inputs/Outputs Deselect/power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Output Disabled Active (ICC) Document Number: 001-06511 Rev. *F Mode Power Page 10 of 16 CY62256N Ordering Information Speed (ns) 55 70 Ordering Code Package Diagram Package Type CY62256NLL−55SNXI 51-85092 28-pin (300-mil) narrow SOIC (Pb-free) CY62256NLL−55ZXI 51-85071 28-pin TSOP I (Pb-free) Operating Range Industrial CY62256NLL−55ZXA 51-85071 28-pin TSOP I (Pb-free) Automotive-A CY62256NLL−55SNXE 51-85092 28-pin (300-mil) narrow SOIC (Pb-free) Automotive-E CY62256NLL−55ZXE 51-85071 28-pin TSOP I (Pb-free) CY62256NLL−70PXC 51-85017 28-pin (600-mil) molded DIP (Pb-free) CY62256NLL−70SNXC 51-85092 28-pin (300-mil) narrow SOIC (Pb-free) CY62256NLL−70ZRXI 51-85074 28-pin reverse TSOP I (Pb-free) CY62256NLL−70SNXA 51-85092 28-pin (300-mil) narrow SOIC (Pb-free) Commercial Industrial Automotive-A Ordering Code Definitions CY 62 256 N LL - XX XXX X Temperature Grade: X = C or I or A or E C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C; A = Automotive-A = –40 °C to +85 °C; E = Automotive-E = –40 °C to +125 °C Package Type: XXX = SNX or ZX or PX or ZRX SNX = 28-pin Narrow SOIC (Pb-free) ZX= 28-pin TSOP I (Pb-free) PX = 28-pin Molded DIP (Pb-free) ZRX = 28-pin Reverse TSOP I (Pb-free) Speed Grade: XX = 55 ns or 70 ns Low Power Nitride Seal Mask fix Density: 256 kbit MoBL SRAM family Company ID: CY = Cypress Document Number: 001-06511 Rev. *F Page 11 of 16 CY62256N Package Diagrams Figure 10. 28-pin (600-mil) Molded DIP, 51-85017 51-85017 *E Figure 11. 28-pin (300-mil) SNC (Narrow Body), 51-85092 51-85092 *D Document Number: 001-06511 Rev. *F Page 12 of 16 CY62256N Figure 12. 28-pin TSOP I (8 × 13.4 mm), 51-85071 51-85071 *I Document Number: 001-06511 Rev. *F Page 13 of 16 CY62256N Figure 13. 28-pin TSOP I (8 × 13.4 mm), 51-85074 51-85074 *G Reference Information Acronyms Document Conventions Acronym Description Units of Measure CMOS complementary metal oxide semiconductor I/O input/output °C degrees Celsius SRAM static random access memory μA microampere VFBGA very fine ball grid array mA milliampere TSOP thin small outline package MHz megahertz Document Number: 001-06511 Rev. *F Symbol Unit of Measure ns nanosecond pF picofarad V volt Ω ohm W watt Page 14 of 16 CY62256N Document History Page Document Title: CY62256N 256 K (32 K × 8) Static RAM Document Number: 001-06511 Revision ECN Orig. of Change Submission Date Description of Change ** 426504 NXR See ECN New Datasheet *A 488954 NXR See ECN Added Automotive product Updated ordering Information table *B 2715270 VKN/AESA 06/05/2009 Updated POD of 28-Pin (600-Mil) Molded DIP package (Spec# 51-85017) *C 2891344 VKN 03/12/2010 Added Table of Contents Removed “L” product information Updated Ordering Information table Updated Package Diagrams (Figure 10, Figure 11, and Figure 12) Updated Sales, Solutions, and Legal Information *D 3119519 AJU 01/04/2011 Updated Ordering Information. Added Ordering Code Definitions. *E 3329873 RAME 07/27/11 Updated template and styles according to current Cypress standards. Added acronyms and units. Removed reference to AN1064 SRAM system guidelines. Updated operation recovery time parameter under Data Retention Characteristics on page 5. *F 3433878 TAVA 11/09/11 Updated package diagrams. Document Number: 001-06511 Rev. *F Page 15 of 16 CY62256N Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06511 Rev. *F Revised November 9, 2011 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16