CY7C1011CV33 2-Mbit (128 K × 16) Static RAM 2-Mbit (128 K × 16) Static RAM Features Functional Description ■ Temperature ranges ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C The CY7C1011CV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. ■ Pin and function compatible with CY7C1011BV33 ■ High speed ❐ tAA = 10 ns (Industrial and Automotive-A) ❐ tAA = 12 ns (Automotive-E) ■ Low active power ❐ 360 mW (max) (Industrial and Automotive-A) ■ 2.0 V data retention ■ Automatic power down when deselected ■ Independent control of upper and lower bits ■ Easy memory expansion with Chip Enable (CE) and Output Enable (OE) features ■ Available in Pb-free 44-pin thin small outline package (TSOP) II, 44-pin thin quad flat package (TQFP), and non Pb-free 48-ball very fine-pitch ball grid array (VFBGA) packages To write to the device, take CE and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take CE and OE LOW while forcing the Write Enable (WE) HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. For more information, see the Truth Table on page 11 for a complete description of Read and Write modes. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For a complete list of related documentation, click here. Logic Block Diagram SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER 128 K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 • BHE WE CE OE BLE A16 A14 A15 A12 A13 A9 Cypress Semiconductor Corporation Document Number: 38-05232 Rev. *P A10 A11 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 24, 2015 CY7C1011CV33 Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Document Number: 38-05232 Rev. *P Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC® Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY7C1011CV33 Pin Configuration Figure 1. 44-pin TSOP II pinout [1] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A11 A10 A9 OE BHE BLE 39 38 37 36 35 34 A12 40 A13 A14 A15 A16 Figure 2. 44-pin TQFP pinout 42 41 43 44 1 I/O4 8 I/O10 I/O5 9 25 I/O9 I/O6 10 24 I/O8 I/O7 11 23 NC 22 I/O11 26 A8 7 A7 VSS 21 VCC 27 20 6 A6 VCC 19 VSS 28 A5 29 18 5 17 4 I/O3 A4 I/O2 I/O12 NC I/O13 30 16 3 I/O1 A3 I/O14 31 14 32 15 2 A1 I/O0 A2 I/O15 13 33 12 1 WE A0 CE Note 1. NC pins are not connected on the die. Document Number: 38-05232 Rev. *P Page 3 of 18 CY7C1011CV33 Selection Guide Description -10 Maximum access time Maximum operating current Maximum CMOS standby current Document Number: 38-05232 Rev. *P -12 Unit 10 12 ns Industrial 100 95 mA Automotive-A 100 – mA Automotive-E – 120 mA Industrial 10 10 mA Automotive-A 10 – mA Automotive-E – 15 mA Page 4 of 18 CY7C1011CV33 Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Supply voltage on VCC relative to GND [2] ............................–0.5 V to +4.6 V DC voltage applied to outputs in High Z state [2] ................................. –0.5 V to VCC+ 0.5 V DC input voltage [2] .............................. –0.5 V to VCC+ 0.5 V Static discharge voltage (MIL-STD-883, method 3015) ................................. > 2001 V Latch up current ..................................................... > 200 mA Operating Range Range Ambient Temperature (TA) VCC Industrial –40 C to +85 C 3.3 V 10% Automotive-A –40 C to +85 C Automotive -E –40 C to +125 C Electrical Characteristics Over the Operating Range Parameter Description Test Conditions -10 -12 Unit Min Max Min Max 2.4 – 2.4 – V – 0.4 – 0.4 V VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Input LOW voltage[2] –0.3 0.8 –0.3 0.8 V IIX Input leakage current Industrial –1 +1 –1 +1 A Automotive-A –1 +1 – – IOZ ICC ISB1 ISB2 GND < VI < VCC Output leakage current GND < VI < VCC, Output disabled VCC operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Automotive-E – – –20 +20 Industrial –1 +1 –1 +1 Automotive-A –1 +1 – – Automotive-E – – –20 +20 Industrial – 100 – 95 Automotive-A – 100 – – Automotive-E – – – 120 Automatic CE power down current – TTL Inputs Max VCC, CE > VIH, Industrial VIN > VIH or VIN < VIL, f = fMAX Automotive-A – 40 – 40 – 40 – – Automotive-E – – – 45 Automatic CE power down current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Industrial – 10 – 10 Automotive-A – 10 – – Automotive-E – – – 15 A mA mA mA Note 2. VIL (min) = –2.0 V for pulse durations of less than 20 ns. Document Number: 38-05232 Rev. *P Page 5 of 18 CY7C1011CV33 Capacitance Parameter [3] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions 44-pin TSOP II 44-pin TQFP Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Unit 44.56 42.66 C/W 10.75 14.64 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] 10-ns devices: 12-ns devices: Z = 50 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R 317 3.3 V OUTPUT 30 pF* OUTPUT R2 351 30 pF* 1.5 V (b) (a) High-Z characteristics: 3.0 V GND ALL INPUT PULSES 90% 90% 10% 10% Rise Time: 1 V/ns (c) R 317 3.3 V Fall Time: 1 V/ns OUTPUT R2 351 5 pF (d) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load shown in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d). Document Number: 38-05232 Rev. *P Page 6 of 18 CY7C1011CV33 Switching Characteristics Over the Operating Range Parameter [5] -10 Description -12 Min Max Min Max Unit Read Cycle tpower[6] VCC (typical) to the first access 1 – 1 – s tRC Read cycle time 10 – 12 – ns tAA Address to data valid – 10 – 12 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data valid – 10 – 12 ns tDOE OE LOW to data valid Industrial/Automotive-A – 5 – 6 ns Automotive-E – – – 8 0 – 0 – ns – 5 – 6 ns 3 – 3 – ns – 5 – 6 ns Z[7] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[7, 8] tLZCE CE LOW to Low Z[7] Z[7, 8] tHZCE CE HIGH to High tPU CE LOW to power up 0 – 0 – ns tPD CE HIGH to power down – 10 – 12 ns tDBE Byte enable to data valid Industrial/Automotive-A – 5 – 6 ns Automotive-E – – – 8 tLZBE Byte enable to Low Z 0 – 0 – ns tHZBE Byte disable to High Z – 5 – 6 ns 10 – 12 – ns Write Cycle [9, 10] tWC Write cycle time tSCE CE LOW to write end 7 – 8 – ns tAW Address setup to write end 7 – 8 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 8 – ns tSD Data setup to write end 5 – 6 – ns tHD Data hold from write end tLZWE 0 – 0 – ns [7] 3 – 3 – ns [7, 8] WE HIGH to Low Z tHZWE WE LOW to High Z – 5 – 6 ns tBW Byte enable to end of write 7 – 8 – ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 6. Transition is measured 500 mV from steady state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05232 Rev. *P Page 7 of 18 CY7C1011CV33 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE DATA VALID HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05232 Rev. *P Page 8 of 18 CY7C1011CV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA IO Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 14. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05232 Rev. *P Page 9 of 18 CY7C1011CV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Notes 16. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. Document Number: 38-05232 Rev. *P Page 10 of 18 CY7C1011CV33 Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power down Standby (ISB) L L H L L Data Out Data Out Read – all bits Active (ICC) L L H L H Data Out High Z Read – lower bits only Active (ICC) L L H H L High Z Data Out Read – upper bits only Active (ICC) L X L L L Data In Data In Write – all bits Active (ICC) L X L L H Data In High Z Write – lower bits only Active (ICC) L X L H L High Z Data In Write – upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) Document Number: 38-05232 Rev. *P I/O0–I/O7 I/O8–I/O15 Mode Power Page 11 of 18 CY7C1011CV33 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 10 CY7C1011CV33-10ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A 12 CY7C1011CV33-12ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive-E Ordering Code Definitions CY 7 C 1 01 1 C V33 - XX XX X X Temperature range: X = A or I or E A = Automotive-A; I = Industrial; E = Automotive-E Pb-free Package Type: XX = ZS or A or BV ZS = 44-pin TSOP II A = 44-pin TQFP Speed grade: XX = 10 ns or 12 ns V33 = 3.3 V Process Technology: 150 nm Bus Width: × 16 bits Density: 2-Mbit Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05232 Rev. *P Page 12 of 18 CY7C1011CV33 Package Diagrams Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05232 Rev. *P Page 13 of 18 CY7C1011CV33 Package Diagrams (continued) Figure 10. 44-pin TQFP (10 × 10 × 1.4 mm) A44S Package Outline, 51-85064 51-85064 *F Document Number: 38-05232 Rev. *P Page 14 of 18 CY7C1011CV33 Acronyms Acronym Document Conventions Description BHE Byte High Enable BLE Byte Low Enable Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere µs microsecond CMOS Complementary Metal Oxide Semiconductor CE Chip Enable I/O Input/Output mA milliampere OE Output Enable mm millimeter SRAM Static Random Access Memory ms millisecond TQFP Thin Quad Flat Pack mV millivolt TSOP Thin Small Outline Package mW milliwatt ns nanosecond % percent pF pico farad V volt W watt TTL Transistor-Transistor Logic VFBGA Very Fine-Pitch Ball Grid Array WE Write Enable Document Number: 38-05232 Rev. *P Page 15 of 18 CY7C1011CV33 Document History Page Document Title: CY7C1011CV33, 2-Mbit (128 K × 16) Static RAM Document Number: 38-05232 Revision ECN Orig. of Change Submission Date ** 117132 HGK 07/31/02 New data sheet. *A 118057 HGK 08/19/02 Updated Pin Configuration: Corrected 48-ball FBGA pinout. *B 119702 DFP 10/11/02 Replaced FBGA with VFBGA in all instances across the document. Updated Selection Guide: Changed value of CMOS standby current from 8 mA to 10 mA. Updated Pin Configuration: Updated address pinouts to “A0 to A16”. Updated Ordering Information: No change in part numbers. Updated package code to BV48A. *C 386106 PCI See ECN Updated Ordering Information (Added lead-free parts). *D 498501 NXR See ECN Updated Logic Block Diagram: Corrected typo. Updated Maximum Ratings: Included Static Discharge Voltage. Included Latch up Current. Updated Electrical Characteristics: Changed the description of IIX parameter from “Input Load Current” to “Input Leakage Current”. Updated Ordering Information. Description of Change *E 522620 VKN See ECN Added Thermal Resistance. *F 1891366 VKN / AESA See ECN Updated Ordering Information (Added -10ZSXA part). *G 2428606 VKN / PYRS See ECN Removed 15 ns speed bin related information in all instances across the document. Removed Commercial Temperature Range related information in all instances across the document. Updated Pin Configuration: Corrected typo in the 44-pin TSOP and 48-ball FBGA pinout. Updated Ordering Information (Removed inactive parts). *H 2664421 VKN / AESA 02/25/09 Added Automotive-E Temperature Range related information (corresponding to 12 ns speed bin) in all instances across the document. Updated Ordering Information. *I 2898399 KAO / AJU 03/24/2010 Updated Package Diagrams. *J 2950666 VKN 06/11/2010 Added Contents. Updated Ordering Information: Included MPN “CY7C1011CV33-12BVXE”. Added Ordering Code Definitions. Added Acronyms. Updated Sales, Solutions, and Legal Information. *K 3089939 PRAS 11/13/2010 Updated Ordering Information (Removed inactive parts). *L 3276463 KAO 06/07/2011 Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Added Units of Measure. Updated Package Diagrams. Updated to new template. Document Number: 38-05232 Rev. *P Page 16 of 18 CY7C1011CV33 Document History Page (continued) Document Title: CY7C1011CV33, 2-Mbit (128 K × 16) Static RAM Document Number: 38-05232 Revision ECN Orig. of Change Submission Date Description of Change *M 3591978 TAVA 04/19/2012 Removed 48-ball VFBGA package related information in all instances across the document. Updated Package Diagrams. *N 3861271 KAO 01/08/2013 Updated Ordering Information (Updated part numbers). Updated Package Diagrams: spec 51-85087 – Changed revision from *D to *E. *O 4578508 KAO 11/21/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Switching Waveforms: Added Note 16 and referred the same note in Figure 8. Updated Package Diagrams: spec 51-85064 – Changed revision from *E to *F. *P 4856402 VINI 07/24/2015 Updated to new template. Completing Sunset Review. Document Number: 38-05232 Rev. *P Page 17 of 18 CY7C1011CV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2015. The information contained herein is subject to change without notice. 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Document Number: 38-05232 Rev. *P Revised July 24, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18