fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the I/O pin — Independent (product term) set, reset, and clock inputs on all registers — Asynchronous bypass capability on all registers under product term control (r = s = 1) — Global or local output enable on three-state I/O • • • • • — Feedback from either register to the array 192 product terms with variable distribution to macrocells 13 inputs, 12 feedback I/O pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inputs High speed: 20 ns maximum tPD Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin PLCC — Programming and operation 100% testable Functional Description The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the product term allocation per flip-flop is variably distributed. I/O Resources Pins 1 through 7 and 9 through 14 serve as array inputs; pin 14 may also be used as a global output enable for the I/O macrocell three-state outputs. Pins 15 through 20 and 23 through 28 are connected to I/O macrocells and may be managed as inputs or outputs depending on the configuration and the macrocell OE terms. Logic Block Diagram OE/I12 I11 I10 I9 I8 I7 GND I6 I5 I4 I3 I2 I1 I0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PROGRAMMABLE AND ARRAY (192x62) 4 12 6 10 8 8 8 8 10 6 12 4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 GND VCC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Cypress Semiconductor Corporation • 3901 North First Street • C331–1 San Jose • CA 95134 • 408-943-2600 January 1989 – Revised December 1992 CY7C331 Selection Guide ICC1 (mA) Generic Part Number Com’l CY7C331–20 130 CY7C331–25 120 tPD (ns) Mil Com’l tS (ns) Mil Com’l 20 160 tCO (ns) Mil 12 25 25 Com’l Mil 20 12 15 25 25 CY7C331–30 150 30 15 30 CY7C331–40 150 40 20 40 I/O Resources (continued) Pin Configuration It should be noted that there are two ground connections (pins 8 and 21) which, together with VCC (pin 22) are located centrally on the package. The reason for this placement and dual-ground structure is to minimize the ground-loop noise when the outputs are driving simultaneously into a heavy capacitive load. I3 I2 I1 I0 I/O0 I/O1 I/O2 TopView 4 3 2 1 2827 26 121314 1516 1718 25 24 23 22 21 20 19 I I I/O8 5 6 7 8 9 10 11 10 11 OE/I12 I/O11 I/O10 I/O9 I4 I5 I6 GND I7 I8 I9 The CY7C331 has twelve I/O macrocells (see Figure 1). Each macrocell has two D-type flip-flops. One is fed from the array, and one from the I/O pin. For each flip-flop there are three dedicated product terms driving the R, S, and clock inputs, respectively. Each macrocell has one input to the array and for each pair of macrocells there is one shared input to the array. The macrocell input to the array may be configured to come from the ‘Q’ output of either flip-flop. I/O3 I/O4 I/O5 VCC GND I/O6 I/O7 C331–2 TO PIN 14 (INVERTED) OE PTERM 0 O 1 S OUT SET PTERM C0 OUTPUT FLIP–FLOP OUT CLK PTERM 1 S S D Q TO I/O PIN O 0 QB R OUT RESET PTERM IN CLK PTERM IN SET PTERM IN RESET PTERM XOR PTERM OR PTERMS TO INPUT BUFFER O 0 O S 1 C1 S 1 0 S Q D QB R INPUT FLIP–FLOP TO SHARED INPUT MUX C331–3 TO PIN 14 (INVERTED) Figure 1. I/O Macrocell 2 CY7C331 I/O Resources (continued) The D-type flip-flop that is fed from the array (i.e., the state flip-flop) has a logical XOR function on its input that combines a single product term with a sum(OR) of a number of product terms. The single product term is used to set the polarity of the output or to implement toggling (by including the current output in the product term). OUTPUT FROM LOGIC ARRAY INPUT TO LOGIC ARRAY Table 1. RS Truth Table Q 1 0 1 0 1 1 0 1 D MACRO– 0 CELL INPUT 1 MUX C3 OUTPUT FROM LOGIC ARRAY S I/O PIN FEEDBACK TO LOGIC ARRAY The R and S inputs to the flip-flops override the current setting of the ‘Q’ output. The S input sets ‘Q’ true and the R input resets ‘Q’ (sets it false). If both R and S are asserted (true) at once, then the output will follow the input (‘Q’ = ‘D’) (see Table 1). R MACROCELL A Q– OUTPUT FROM INPUT REGISTEROF I/O MACROCELLA Q– OUTPUT FROM INPUT REGISTEROF I/O MACROCELLB MACROCELL B I/O PIN FEEDBACK TO LOGIC ARRAY C331–4 Figure 2. Shared Input Multiplexer The CY7C331 is configured by three arrays of configuration bits (C0, C1, C2). For each macrocell, there is one C0 bit and one C1 bit. For each pair of macrocells there is one C2 bit. Shared Input Multiplexer The input associated with each pair of macrocells may be configured by the shared input multiplexer to come from either macrocell; the ‘Q’ output of the flip-flop coming from the I/O pin is used as the input signal source (see Figure 2). Product Term Distribution There are twelve C0 bits, one for each macrocell. If C0 is programmed for a macrocell, then the three-state enable (OE) will be controlled by pin 14 (the global OE). If C0 is not programmed, then the OE product term for that macrocell will be used. The product terms are distributed to the macrocells such that 32 product terms are distributed between two adjacent macrocells. There are twelve C1 bits, one for each macrocell. The C1 bit selects inputs for the product term (PT) array from either the state register (if the bit is unprogrammed) or the input register (if the bit is programmed). The pairing of macrocells is the same as it is for the shared inputs. Eight of the product terms are used in each macrocell for set, reset, clock, output enable, and the upper part of the XOR gate. This leaves 16 product terms per pair of macrocells to be divided between the sum-of-products inputs to the two state registers. The following table shows the I/O pin pairing for shared inputs, and the product term (PT) allocation to macrocells associated with the I/O pins (see Table 2). There are six C2 bits, providing one C2 bit for each pair of macrocells. The C2 bit controls the shared input multiplexer; if the C2 bit is not programmed, then the input to the product term array comes from the upper macrocell (A). If the C2 bit is programmed, then the input comes from the lower macrocell (B). The timing diagrams for the CY7C331 cover state register, input register, and various combinational delays. Since internal clocks are the outputs of product terms, all timing is from the transition of the inputs causing the clock transition. Table 2. . Product Term Distribution Macrocell Pin Number Product Terms 0 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 20 19 18 17 16 15 4 12 6 10 8 8 8 8 10 6 12 4 3 CY7C331 Maximum Ratings Static Discharge Voltage............................................>1500V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .....................................................>200 mA Storage Temperature .................................. –65°C to +150°C DC Programming Voltage ............................................ 13.0 V Ambient Temperature with Power Applied .............................................. –55°C to +125°C Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% –55°C to +125°C 5V ± 10% Supply Voltage to Ground Potential (Pin 28 to Pin 8 or 21) .................................... –0.5V to +7.0V DC Input Voltage............................................ –3.0V to +7.0V [1] Military Output Current into Outputs (LOW) .............................12 mA Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions Min. Max. Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –3.2 mA (Com’l), IOH = –2 mA (Mil) VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 12 mA (Com’l), IOL = 8 mA (Mil) VIH Input HIGH Voltage Guaranteed HIGH Input, all Inputs[3] VIL Input LOW Voltage Guaranteed LOW Input, all Inputs[3] 0.8 V IIX Input Leakage Current VSS < VIN < VCC, VCC = Max. –10 +10 µA IOZ Output Leakage Current VSS < VOUT < VCC, VCC = Max. –40 +40 µA –30 –90 mA Com’l –20 130 mA Com’l –25 120 Mil –25 160 Mil –30, –40 150 Com’l 180 Mil 200 Output Short Circuit Current[4] VCC = Max., VOUT ICC1 Standby Power Supply Current VCC = Max., VIN = GND, Outputs Open Power Supply Current at Frequency[4, 6] VCC = Max., Outputs Disabled (in High Z State) Device Operating at fMAX External (fMAX1) V 0.5 2.2 = 0.5V[5] ISC ICC2 2.4 Unit VOH V V mA mA Capacitance[4] Parameter CIN Description Input Capacitance Test Conditions VIN = 2.0V at f = 1 MHz COUT Max. Unit 10 pF Output Capacitance VOUT = 2.0V at f = 1 MHz 10 pF Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Because these input signals are controlled by product terms, active input polarity may be of either polarity. Internal active input polarity has been shown for clarity. 4 CY7C331 AC Test Loads and Waveforms R1 313 Ω (470Ω Mil) R1 313 Ω (470Ω Mil) 5V 5V OUTPUT OUTPUT R2 208 Ω (319Ω Mil) 50pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 3.0V 90% INCLUDING JIG AND SCOPE (a) 10% R2 208 Ω GND (319Ω Mil) ≤ 5 ns 5 pF (b) 90% 10% ≤ 5 ns C331–5 C331–6 Equivalent to: THÉVENIN EQUIVALENT (Military) 190Ω 2.02V=V thm OUTPUT to: THÉVENIN EQUIVALENT (Commercial) 125Ω Equivalent 2.00V=V thc OUTPUT C331–8 C331–7 Parameter t PXZ(– ) t PXZ(+) VX 1.5V Output Waveform—Measurement Level 0.5V V OH VX 2.6V 0.5V C331–9 VX V OL C331–10 t PZX(+) 0.5V V thc V OH VX t PZX(– ) V thc C331–11 VX 0.5V t ER(– ) 1.5V V OH 0.5V t ER(+) 2.6V 0.5V V OL C331–12 VX C331–13 VX V OL C331–14 t EA(+) V thc 0.5V V OH VX t EA(– ) V thc C331–15 VX V OL 0.5V C331–16 (c) Test Waveforms and Measurement Levels ) Switching Characteristics Over the Operating Range[2] Commercial –20 Parameter tPD tICO Description Min. Input to Output Propagation Delay[7] Input Register Clock to Output Delay[8] Clock[8] tIOH Output Data Stable Time from Input tIS Input or Feedback Set-Up Time to Input Register Clock[8] Clock[8] tIH Input Register Hold Time from Input tIAR Input to Input Register Asynchronous Reset Delay[8] –25 Max. Max. Unit 20 25 ns 35 40 ns 5 5 ns 2 2 ns 11 5 Min. 13 35 ns 40 ns CY7C331 Switching Characteristics Over the Operating Range[2] (continued) Commercial –20 Parameter Description Min. [4, 8] –25 Max. Min. Max. Unit tIRW Input Register Reset Width 35 40 ns tIRR Input Register Reset Recovery Time[4, 8] 35 40 ns tIAS [8] Input to Input Register Asynchronous Set Delay [4, 8] 35 40 ns tISW Input Register Set Width 35 40 ns tISR Input Register Set Recovery Time[4, 8] 35 40 ns 12 15 ns 12 15 ns [8, 9, 10] tWH Input and Output Clock Width HIGH tWL Input and Output Clock Width LOW[8, 9, 10] fMAX1 Maximum Frequency with Feedback in Input Registered Mode (1/(tICO + tIS))[11] 27.0 23.8 MHz fMAX2 Maximum Frequency Data Path in Input Registered Mode (Lowest of 1/tICO, 1/(tWH + tWL), or 1/(tIS + tIH)[8] 28.5 25.0 MHz tIOH–tIH33X Output Data Stable from Input Clock Minus Input Register Input Hold Time for 7C335[12, 13] 0 0 ns tCO Output Register Clock to Output Delay[9] tOH 25 ns 3 3 ns tS Output Register Input Set-Up Time to Output Clock[9] 12 12 ns tH Output Register Input Hold Time from Output Clock[9] 8 8 ns tOAR Output Data Stable Time from Output 20 Clock[9] Input to Output Register Asynchronous Reset Width[9] tORW Output Register Reset tORR Output Register Reset Recovery Time[9] tOAS Input to Output Register Asynchronous Set tOSW Output Register Set Width[9] tOSR Delay[9] Output Register Set Recovery 20 ns 20 25 ns 20 25 ns Delay[9] Time[9] 25 20 25 ns 20 25 ns 20 25 ns tEA Input to Output Enable Delay[14, 15] 25 25 ns tER Input to Output Disable Delay[14, 15] 25 25 ns 20 20 ns Pin 14 to Output Enable Delay[14, 15] tPXZ Pin 14 to Output Disable Delay[14, 15] fMAX3 Maximum Frequency with Feedback in Output Registered Mode (1/(tCO + tS))[16, 17] 31.2 27.0 MHz fMAX4 Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/tCO, 1/(tWH + tWL), or 1/(tS + tH))[9] 41.6 33.3 MHz tOH–tIH33X Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C335[13, 18] 0 0 ns fMAX5 Maximum Frequency Pipelined Mode[10, 17] 35.0 30.0 MHz tPZX 20 20 ns Notes: 7. Refer to Figure 3, configuration 1. 8. Refer to Figure 3, configuration 2. 9. Refer to Figure 3, configuration 3. 10. Refer to Figure 3, configuration 6. 11. Refer to Figure 3, configuration 7. 12. Refer to Figure 3, configuration 9. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C331. This specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product. 14. Part (a) of AC Test Loads and Waveforms used for all parameters except tPZXI, tPXZI, tPZX, and tPXZ, which use part (b). Part (c) shows the test waveforms and measurement levels. 15. Refer to Figure 3, configuration 4. 16. Refer to Figure 3, configuration 8. 17. This specification is intended to guarantee that a state machine configuration created with internal or external feedback can be operated with output register and input register clocks controlled by the same source. These parameters are tested by periodic sampling of production product. 6 CY7C331 Switching Characteristics Over the Operating Range[2] (continued) Military –25 Parameter Description Min. [7] –30 Max. Min. –40 Max. Min. Max. Unit tPD Input to Output Propagation Delay 25 30 40 ns tICO Input Register Clock to Output Delay[4, 8] 45 50 65 ns tIOH tIS [4, 8] Output Data Stable Time from Input Clock Input or Feedback Set-Up Time to Input Register Clock[8] [4, 8] tIH Input Register Hold Time from Input Clock tIAR Input to Input Register Asynchronous Reset Delay[4, 8] tIRW [8] Input Register Reset Width 5 ns 5 5 5 ns 15 45 45 Time[8] Input Register Reset Recovery tIAS Input to Input Register Asynchronous Set Delay[8] Input Register Set 5 13 tIRR tISW 5 50 45 Width[8] Time[8] 20 50 65 50 45 ns 65 ns 65 50 ns ns 65 ns 45 50 65 ns tISR Input Register Set Recovery 45 50 65 ns tWH Input and Output Clock Width High[8, 9, 10] 15 20 25 ns tWL Input and Output Clock Width Low[8, 9, 10] 15 20 25 ns fMAX1 Maximum frequency with Feedback in Input Registered Mode (1/(tICO + tIS))[11] 20.0 18.1 14.2 MHz fMAX2 Maximum frequency Data Path in Input Registered Mode (Lowest of 1/tICO, 1/(tWH + tWL), or 1/(tIS + tIH)[8] 22.2 20.0 15.3 MHz tIOH–tIH33X Output Data Stable from Input Clock Minus Input Register Input Hold Time for 7C335[12, 13] 0 0 0 ns tCO Output Register Clock to Output Delay[9] 25 Clock[9] 30 40 ns tOH Output Data Stable Time from Output 3 3 3 ns tS Output Register Input Set-Up Time to Output Clock[9] 15 15 20 ns tH Output Register Input Hold Time from Output Clock[9] 10 10 12 ns tOAR Input to Output Register Asynchronous Reset Delay[9] tORW Output Register Reset Width[9] tORR tOAS Output Register Reset Recovery Time[9] Input to Output Register Asynchronous Set Output Register Set tOSR Output Register Set Recovery Time[9] 30 40 ns 30 40 ns 25 30 40 ns Delay[9] Width[9] tOSW 25 25 25 30 40 ns 25 30 40 ns 25 30 40 ns Input to Output Enable Delay[14, 15] 25 30 40 ns tER Input to Output Disable Delay[14, 15] 25 30 40 ns tPZX Pin 14 to Output Enable Delay[14, 15] 20 25 35 ns tPXZ Pin 14 to Output Disable Delay[14, 15] 20 25 35 ns fMAX3 Maximum Frequency with Feedback in Output Registered Mode )1/(tCO + tS)[16, 17] 25.0 22.2 16.6 MHz fMAX4 Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/tCO, 1/(tWH + tWL), or 1/(tS + tH)[9] 33.3 25.0 20.0 MHz tOH–tIH33X Output Data Stable from Output Clock Minus Input Register Input Hold Time for 7C335[13, 18] 0 0 0 ns fMAX5 Maximum Frequency Pipelined Mode[10, 17] 28.0 23.5 18.5 MHz tEA Note: 18. Refer to Figure 3, configuration 10. 7 CY7C331 Switching Waveforms tS [20] INPUT OR I/O PIN tIS tH tIH I/O INPUT REGISTER CLOCK [6] tWH tWH OUTPUT REGISTER CLOCK[6] tWL tWL tIOH[19] tOH OUTPUT tICO[19] [21] tPD[21] SET AND RESET INPUTS[6] tCO tORR, tOSR[23] tORR, tOSR[21] tORR, tOSR[22] OE PRODUCT TERM INPUT [6, 15] C331–17 tEA PIN 14 AS OE[24] tPXZ tPZX OUTPUT OUTPUT REGISTER RESET INPUT [6,9] tOAR tER tORW OUTPUT REGISTER CLOCK [6,9] tORR tOAS OUTPUT REGISTER SET INPUT [6,9] tOSW tIAR I/O INPUT REGISTER RESET INPUT [6,8] tOSR tIRW I/O INPUT REGISTER CLOCK[6,8] tIRR tIAS I/O INPUT REGISTER SET INPUT [6,8] tISR tISW C331–18 Notes: 19. Output register is set in Transparent mode. Output register set and reset inputs are in a HIGH state. 20. Dedicated input or input register set in Transparent mode. Input register set and reset inputs are in a HIGH state. 21. Combinatorial Mode. Reset and set inputs of the input and output registers should remain in a HIGH state at least until the output responds at tPD. When returning set and reset inputs to a LOW state, one of these signals should go LOW a minimum of tOSR (set input) or tORR (reset input) prior to the other. This guarantees predictable register states upon exit from Combinatorial mode. 22. When entering the Combinatorial mode, input and output register set and reset inputs must be stable in a HIGH state a minimum of tISR or tIRR and tOSR or tORR respectively prior to application of logic input signals. 23. When returning to the input and/or output Registered mode, register set and reset inputs must be stable in a LOW state a minimum of tISR or tIRR and tOSR or tORR respectively prior to the application of the register clock input. 24. Refer to Figure 3, configuration 5. 8 CY7C331 CONFIGURATION 1 PRODUCT TERM ARRAY PIN PIN OE INPUT OR I/O PIN PIN CONFIGURATION 2 UNREGISTERED INPUT OR I/O PIN I/O PIN CLOCK/S/R INPUT INPUT REGISTER PIN PRODUCT TERM ARRAY PIN Q D I/O PIN ONLY OE RESET I/O PIN OUTPUT REGISTER PIN CONFIGURATION 3 D PRODUCT TERM ARRAY UNREGISTERED INPUT OR I/O PIN PIN Q OE SET I/O PIN RESET CLOCK/S/R PIN INPUT UNREGISTERED INPUT OR I/O PIN PIN CONFIGURATION 4 PRODUCT TERM ARRAY INPUT OR I/O PIN OUTPUT ENABLE PIN PIN INPUT OR I/O PIN I/O PIN PIN 14 CONFIGURATION 5 OUTPUT ENABLE INPUT OR I/O PIN PRODUCT TERM ARRAY PIN PIN INPUT OR I/O PIN I/O PIN OUTPUT REGISTER INPUT REGISTER I/O PIN I/O PIN ONLY PIN D PIN Q DATA INPUT CONFIGURATION 6 UNREGISTERED INPUT OR I/O PIN CLOCK PRODUCT TERM ARRAY OE CLOCK DATA OUTPUT PIN C331–19 CLOCK INPUT Figure 3. Timing Configurations . 9 CY7C331 INPUT REGISTER DATA INPUT PIN D PIN Q CLOCK CONFIGURATION 7 OE PRODUCT TERM ARRAY PIN Q PIN D INPUT REGISTER OE DATA OUTPUT CLOCK CLOCK INPUT OUTPUT REGISTER PIN DATA INPUT D PRODUCT TERM ARRAY OUTPUT REGISTER CONFIGURATION 8 PIN Q DATA OUTPUT PIN PIN Q Q OE CLOCK D OE CLOCK CLOCK INPUT C331–20 331 INPUT REGISTER D 330 OR 332 INPUT REGISTER PIN Q PIN D Q OE PRODUCT TERM ARRAY CONFIGURATION 9 CLOCK 331 OUTPUT REGISTER D 330 OR 332 INPUT REGISTER PIN Q PIN D Q OE CONFIGURATION 10 PRODUCT TERM ARRAY C331–21 CLOCK Figure 3. Timing Configurations (continued) 10 CY7C331 CY7C331 Logic Diagram (Upper Half) 11 CY7C331 CY7C331 Logic Diagram (Lower Half) 12 CY7C331 Ordering Information ICC1 (mA) tPD (ns) tS (ns) tCO (ns) 130 20 12 20 160 120 150 150 25 25 30 40 15 12 15 20 25 25 30 40 Ordering Code Package Name Package Type CY7C331–20HC H64 28-Pin Windowed Leaded Chip Carrier CY7C331–20JC J64 28-Lead Plastic Leaded Chip Carrier CY7C331–20PC P21 28-Lead (300-Mil) Molded DIP CY7C331–20WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C331–25DMB D22 28-Lead (300-Mil) CerDIP CY7C331–25HMB H64 28-Pin Windowed Leaded Chip Carrier CY7C331–25LMB L64 28-Square Leadless Chip Carrier CY7C331–25QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C331–25TMB T74 28-Lead Windowed Cerpack CY7C331–25WMB W22 28-Lead (300-Mil) Windowed CerDIP CY7C331–25HC H64 28-Pin Windowed Leaded Chip Carrier CY7C331–25JC J64 28-Lead Plastic Leaded Chip Carrier CY7C331–25PC P21 28-Lead (300-Mil) Molded DIP CY7C331–25WC W22 28-Lead (300-Mil) Windowed CerDIP CY7C331–30DMB D22 28-Lead (300-Mil) CerDIP CY7C331–30HMB H64 28-Pin Windowed Leaded Chip Carrier CY7C331–30LMB L64 28-Square Leadless Chip Carrier CY7C331–30QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C331–30TMB T74 28-Lead Windowed Cerpack CY7C331–30WMB W22 28-Lead (300-Mil) Windowed CerDIP CY7C331–40DMB D22 28-Lead (300-Mil) CerDIP CY7C331–40HMB H64 28-Pin Windowed Leaded Chip Carrier CY7C331–40LMB L64 28-Square Leadless Chip Carrier CY7C331–40QMB Q64 28-Pin Windowed Leadless Chip Carrier CY7C331–40TMB T74 28-Lead Windowed Cerpack CY7C331–40WMB W22 28-Lead (300-Mil) Windowed CerDIP 13 Operating Range Commercial Military Commercial Military Military CY7C331 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Switching Characteristics Subgroups Parameter Subgroups VOH 1, 2, 3 tIS 9, 10, 11 VOL 1, 2, 3 tIH 9, 10, 11 VIH 1, 2, 3 tWH 9, 10, 11 VIL 1, 2, 3 tWL 9, 10, 11 IIX 1, 2, 3 tCO 9, 10, 11 IOZ 1, 2, 3 tPD 9, 10, 11 ICC1 1, 2, 3 tIAR 9, 10, 11 tIAS 9, 10, 11 tPXZ 9, 10, 11 tPZX 9, 10, 11 tER 9, 10, 11 tEA 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11 Document #: 38–00066–D 14 CY7C331 Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 28-Lead Plastic Leaded Chip Carrier J64 D– 15Config.A 28-Square Leadless Chip Carrier L64 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C–4 MIL-STD-1835 C–4 15 CY7C331 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier 16 CY7C331 Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead Windowed Cerpack T74 17 CY7C331 Package Diagrams (continued) 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D– 15Config.A © Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.