Revised August 2000 74AC648 Octal Transceiver/Register with 3-STATE Outputs General Description Features The AC648 consists of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data transfers ■ 3-STATE outputs ■ 300 mil slim dual-in-line package ■ Outputs source/sink 24 mA ■ Inverted data to output Ordering Code: Order Number Package Number 74AC648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Description 74AC648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names A0–A7 Description Data Register A Inputs, Data Register A 3-STATE Outputs B0 – B7 Data Register B Inputs, CPAB, CPBA Clock Pulse Inputs Data Register B 3-STATE Outputs SAB, SBA Transmit/Receive Inputs DIR, G Output Enable Inputs FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010133 www.fairchildsemi.com 74AC648 Octal Transceiver/Register with 3-STATE Outputs November 1988 74AC648 Function Table Inputs Data I/O (Note 1) G DIR CPAB CPBA SAB SBA H X H or L H or L X X H X X X X A0–A7 B0–B7 Input Input Function Isolation Clock An Data into A Register H X X X X Clock Bn Data into B Register L H X L X An to Bn—Real Time (Transparent Mode) L H L H L H L L X X L X H or L X H X X H X Clock An Data into A Register and Output to Bn X X X L Bn to An —Real Time (Transparent Mode) L L X L L X L L X H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition H or L Input Output Clock An Data into A Register A Register to Bn (Stored Mode) X L X H Output Input B Register to An (Stored Mode) Clock Bn Data into B Register X H Clock Bn Data into B Register and Output to An Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. Real Time Transfer A-Bus to B-Bus Real Time Transfer B-Bus to A-Bus FIGURE 1. FIGURE 2. Storage from Bus to Register Transfer from Register to Bus FIGURE 3. FIGURE 4. www.fairchildsemi.com 2 74AC648 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74AC648 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V 125 mV/ns VIN from 30% to 70% of VCC +20 mA DC Output Voltage (VO) 2.0V to 6.0V Input Voltage (VI) VCC @ 3.3V, 4.5V, 5.5V −0.5V to VCC + 0.5V DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol Parameter (V) VIH VIL VOH TA = +25°C VCC Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 3.0 0.002 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 IOH= −12 mA V IOH= −24 mA IOH= −24 mA (Note 3) V IOUT = 50 µA VIN = VIL or VIH IOL= 12 mA V IOL = 24 mA IOL = 24 mA (Note 3) IIN Maximum Input (Note 5) Leakage Current IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 4) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent (Note 5) Supply Current IOZT Maximum I/O Leakage Current µA 5.5 8.0 80.0 µA 5.5 ±0.6 ±6.0 µA VI = VCC, GND VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 4 Symbol tPLH tPHL tPLH tPHL tPLH Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 6) Min Typ Max Min Max Propagation Delay 3.3 1.5 10.0 15.5 1.5 17.0 Clock to Bus 5.0 1.5 7.0 11.0 1.5 12.0 Propagation Delay 3.3 1.5 8.5 13.5 1.5 14.5 Clock to Bus 5.0 1.5 6.0 10.5 1.5 11.5 Propagation Delay 3.3 1.5 6.0 10.0 1.5 11.0 Bus to Bus 5.0 1.5 4.0 7.0 1.0 7.5 Propagation Delay 3.3 1.5 5.5 9.0 1.5 10.0 Bus to Bus 5.0 1.5 3.5 7.5 1.0 8.0 Propagation Delay 3.3 1.5 7.5 12.5 1.5 14.0 SBA or SAB to An or Bn 5.0 1.5 5.5 9.0 1.5 10.0 Propagation Delay 3.3 1.5 7.5 12.5 1.5 14.0 SBA or SAB to An or B n 5.0 1.5 5.5 9.5 1.5 10.5 Enable Time 3.3 1.5 6.5 11.0 1.0 11.5 G to An or Bn 5.0 1.5 5.0 8.0 1.0 9.0 Enable Time 3.3 1.5 7.0 11.0 1.0 12.5 G to An or Bn 5.0 1.5 5.0 8.0 1.0 9.0 Disable Time 3.3 1.5 7.5 12.0 1.0 13.0 G to An or Bn 5.0 1.5 6.0 10.0 1.0 11.0 Disable Time 3.3 1.5 7.0 11.5 1.0 12.5 G to An or Bn 5.0 1.5 5.5 9.0 1.0 10.0 Enable Time 3.3 1.5 6.0 12.5 1.0 14.0 DIR to An or Bn 5.0 1.5 4.5 9.5 1.0 10.5 Enable Time 3.3 1.5 6.5 13.0 1.5 14.5 DIR to An or Bn 5.0 1.5 4.5 9.0 1.0 10.5 Disable Time 3.3 1.5 7.0 11.5 1.0 13.5 DIR to An or Bn 5.0 1.5 5.5 9.0 1.0 10.0 Disable Time 3.3 1.5 7.0 13.5 1.5 15.0 DIR to An or Bn 5.0 1.5 5.0 9.5 1.0 10.0 ns ns ns ns ns (with An or Bn HIGH or LOW) tPHL ns (with An or Bn HIGH or LOW) tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ ns ns ns ns ns ns ns ns Note 6: Voltage Range 3.3 is 3.3V ± 0.3V; Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS tH tW Parameter V CC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Typ Setup Time, HIGH or LOW, 3.3 2.0 3.0 3.5 Bus to Clock 5.0 1.5 2.0 2.0 Units Guaranteed Minimum Hold Time, HIGH or LOW, 3.3 −1.5 0 0 Bus to Clock 5.0 −0.5 1.0 1.0 Clock Pulse Width 3.3 2.0 3.5 4.0 HIGH or LOW 5.0 2.0 3.0 3.0 ns ns ns Note 7: Voltage Range 3.3 is 3.3V ± 0.3V; Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 65.0 pF VCC = 5.0V CI/O Input/Output Capacitance 15.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC648 AC Electrical Characteristics 74AC648 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74AC648 Octal Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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