CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 64 x 18 (CY7C4425V) • 256 x 18 (CY7C4205V) • 512 x 18 (CY7C4215V) The CY7C42X5V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C42X5V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and a Write Enable pin (WEN). • 1K x 18 (CY7C4225V) • 2K x 18 (CY7C4235V) • 4K x 18 (CY7C4245V) • 0.65µ CMOS • High-speed 67-MHz operation (15-ns read/write cycle times) • Low power — ICC = 30 mA • 5V tolerant inputs (VIH MAX = 5V) • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL-compatible • Retransmit function • Output Enable (OE) pin • Independent read and write enable pins • Supports free-running 50% duty cycle clock inputs • Width-Expansion Capability • Depth-Expansion Capability • 64-pin 14 × 14 TQFP and 64-pin 10 × 10 STQFP • Pb-Free packages available When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C42X5V have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input (WXI, RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. The CY7C42X5V provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the Read Clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65µ P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Cypress Semiconductor Corporation Document #: 38-06029 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 7, 2005 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V D0–17 Logic Block Diagram INPUT REGISTER WCLK WEN FLAG PROGRAM REGISTER WRITE CONTROL RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 WRITE POINTER RS FF EF FLAG LOGIC PAE PAF SMODE READ POINTER RESET LOGIC FL/RT WXI WXO/HF RXI RXO THREE–STATE OUTPUT REGISTER EXPANSION LOGIC READ CONTROL OE Q0–17 RCLK REN Pin Configuration Document #: 38-06029 Rev. *C REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC/SMODE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC Q3 Q0 Q1 GND Q2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CY7C4425V CY7C4205V CY7C4215V CY7C4225V CY7C4235V CY7C4245V PAE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FL/RT WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 D16 D17 GND RCLK STQFP/TQFP Top View Page 2 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Selection Guide Maximum Frequency CY7C42X5V-15 CY7C42X5V-25 CY7C42X5V-35 Unit 66.7 40 28.6 MHz Maximum Access Time 11 15 20 ns Minimum Cycle Time 15 25 35 ns Minimum Data or Enable Set-up 4 6 7 ns Minimum Data or Enable Hold 1 1 2 ns Maximum Flag Delay 11 15 20 ns 30 30 30 mA Operating Current CY7C4425V CY7C4205V CY7C4215V CY7C4225V CY7C4235V CY7C4245V 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18 64-pin 14x14 TQFP 64-pin 10x10 STQFP 64-pin 14x14 TQFP 64-pin 10x10 STQFP 64-pin 14x14 TQFP 64-pin 10x10 STQFP 64-pin 14x14 TQFP 64-pin 10x10 STQFP 64-pin 14x14 TQFP 64-pin 10x10 STQFP 64-pin 14x14 TQFP 64-pin 10x10 STQFP Density Packages Commercial Pin Definitions Signal Name Description I/O Function D0−17 Data Inputs I Data inputs for an 18-bit bus. Q0−17 Data Outputs O Data outputs for an 18-bit bus. WEN Write Enable I Enables the WCLK input. REN Read Enable I Enables the RCLK input. WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. WXO/HF Write Expansion Out/Half Full Flag O Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded – Write Expansion Out signal, connected to WXI of next device. EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK. PAE Programmable Almost Empty O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS. PAF Programmable Almost Full O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS. LD Load I When LD is LOW, D0−17 (O0−17) are written (read) into (from) the programmable-flag-offset register. FL/RT First Load/ Retransmit I Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to VSS; all other devices will have FL tied to VCC. In standard mode of width expansion, FL is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also available in standalone mode by strobing RT. WXI Write Expansion Input I Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to VSS. RXI Read Expansion Input I Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to VSS. Document #: 38-06029 Rev. *C Page 3 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Pin Definitions (continued) Signal Name Description I/O Function RXO Read Expansion Output O Cascaded – Connected to RXI of next device. RS Reset I Resets device to empty condition. A reset is required before an initial read or write operation after power-up. OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. VCC/SMODE Synchronous Almost Empty/ Almost Full Flags I Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to VCC. Synchronous Almost Empty/Almost Full flags – tied to VSS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Architecture Programming The CY7C42X5V consists of an array of 64 to 4K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5V also includes the control signals WXI, RXI, WXO, RXO for depth expansion. The CY7C42X5V devices contain two 12-bit offset registers. Data present on D0–11 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO’s flags, the default offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0–11 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the Write Clock (WCLK). The third transition of the Write Clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. Resetting the FIFO Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. FIFO Operation When the WEN signal is active (LOW), data present on the D0-17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0−17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An Output Enable (OE) pin is provided to three-state the Q0–17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Q0−17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0−17 outputs even after additional reads occur. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the Read Clock (RCLK). Table 1. Write Offset Register WCLK[1] LD WEN 0 0 Writing to offset registers: Empty Offset Full Offset Selection 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation Note: 1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Document #: 38-06029 Rev. *C Page 4 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Flag Operation that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. The CY7C42X5V devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock. Full Flag Retransmit The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programmable Almost Empty/Almost Full Flag The CY7C42X5V features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Table 2. Flag Truth Table Number of Words in FIFO 7C4425V - 64 x 18 7C4205V - 256 x 18 7C4215V - 512 x 18 FF PAF HF PAE EF 0 0 0 H H H L L 1 to n[2] 1 to n[2] 1 to n[2] H H H L H (n + 1) to 32 (n + 1) to 128 (n + 1) to 256 H H H H H 33 to (64 − (m + 1)) 129 to (256 − (m + 1)) 257 to (512 − (m + 1)) H H L H H (64 − m)[3] to 63 (256 − m)[3] to 255 (512 − m)[3] to 511 H L L H H 64 256 512 L L L H H FF PAF HF PAE EF Number of Words in FIFO 7C4225V - 1K x 18 7C4235V - 2K x 18 7C4245V - 4K x 18 0 0 0 H H H L L 1 to n[2] 1 to n[2] 1 to n[2] H H H L H (n + 1) to 512 (n + 1) to 1024 (n + 1) to 2048 H H H H H 513 to (1024 − (m + 1)) 1025 to (2048 − (m + 1)) 2049 to (4096 − (m + 1)) H H L H H (1024 − m)[3] to 1023 (2048 − m)[3] to 2047 (4096 − m)[3] to 4095 H L L H H 1024 2048 4096 L L L H H Note: 2. n = Empty Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127). 3. m = Full Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127). Document #: 38-06029 Rev. *C Page 5 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Width Expansion Configuration ANDing the Empty (Full) flags of every FIFO. This technique will avoid ready data from the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 2 demonstrates a 36-word width by using two CY7C42X5V. The CY7C42X5V can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by RESET (RS) DATA IN (D) 36 RESET (RS) 18 18 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE(OE) LOAD (LD) PROGRAMMABLE(PAE) HALF FULL FLAG (HF) FF 7C4425V 7C4205V 7C4215V 7C4225V 7C4235V 7C4245V 7C4425V 7C4205V 7C4215V 7C4225V 7C4235V 7C4245V FF EF PROGRAMMABLE(PAF) EMPTYFLAG (EF) EF 18 FULL FLAG (FF) DATA OUT (Q) 36 18 FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI) Figure 1. Block Diagram of Low-Voltage Synchronous FIFO Memories Used in a Width Expansion Configuration Depth Expansion Configuration (with Programmable Flags) The CY7C42X5V can easily be adapted to applications requiring more than 64/256/512/1024/2048/4096 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5Vs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. Document #: 38-06029 Rev. *C Page 6 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V WXO RXO FIRSTLOAD (FL) 7C4425V 7C4205V 7C4215V 7C4225V 7C4235V 7C4245V VCC FF EF PAE PAF WXI RXI WXO RXO 7C4425V 7C4205V 7C4215V 7C4225V 7C4235V 7C4245V DATAIN (D) FIRSTLOAD (FL) VCC DATAOUT (Q) FF EF PAE PAF WXI RXI WRITECLOCK (WCLK) WXO RXO WRITE ENABLE (WEN) READ ENABLE (REN) 7C4425V 7C4205V 7C4215V 7C4225V 7C4235V 7C4245V RESET(RS) LOAD (LD) FF FF PAF READ CLOCK (RCLK) OUTPUT ENABLE (OE) EF EF PAFWXI RXIPAE PAE 42X5V–23 FIRSTLOAD (FL) Figure 2. Block Diagram of Low-Voltage Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration Document #: 38-06029 Rev. *C Page 7 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V DC Input Voltage .................................................... −0.5V to +5V Maximum Ratings[4] Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................−65°C to +150° C Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied.................................................−55°C to +125° C Operating Range Supply Voltage to Ground Potential .................−0.5V to +5.0V Range DC Voltage Applied to Outputs in High-Z State ............................................. −0.5V to VCC+0.5V Commercial Ambient Temperature VCC 0° C to +70° C 3.3V ± 300 mV Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C42X5V-15 7C42X5V-25 7C42X5V-35 Min. Min. Min. Max. 2.4 Max. VOH Output HIGH Voltage VCC = Min., IOH = −2.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Low = 2.0V High = VCC +0.5V 2.0 5.0 2.0 5.0 VIL[5] Input LOW Voltage Low = −3.0V High = 0.8 V −0.5 0.8 −0.5 IIX Input Leakage Current VCC = Max. −10 10 IOZL IOZH Output OFF, High Z Current OE > VIH, VSS < VO < VCC −10 +10 ICC[6] Operating Current VCC = Max., IOUT = 0 mA Com’l 30 ISB[7] Standby Current VCC = Max., IOUT = 0 mA Com’l 6 0.4 Max. 2.4 0.4 Unit V 0.4 V 2.0 5.0 V 0.8 −0.5 0.8 V −10 10 −10 10 µA −10 +10 −10 +10 µA 30 30 mA 6 6 mA Capacitance[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25° C, f = 1 MHz, VCC = 5.0V Max. Unit 5 pF 7 pF Notes: 4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up 5. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or VSS. 6. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 7. All inputs = VCC − 0.2V, except WCLK and RCLK, which are switching at 20 MHz. 8. Tested initially and after any design or process changes that may affect these parameters Document #: 38-06029 Rev. *C Page 8 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V AC Test Loads and Waveforms[9, 10] R1 = 330Ω ALL INPUT PULSES 3.3V OUTPUT 3.0V R2 = 510Ω CL INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT Rth = 200Ω OUTPUT 90% 10% 90% 10% GND ≤ 3 ns ≤ 3 ns Vth = 2.0V Switching Characteristics Over the Operating Range Parameter Description 7C42X5V-15 7C42X5V-25 7C42X5V-35 Min. Min. Min. Max. 66.7 Max. Unit 28.6 MHz 20 ns Clock Cycle Frequency tA Data Access Time 2 tCLK Clock Cycle Time 15 25 35 ns tCLKH Clock HIGH Time 6 10 14 ns tCLKL Clock LOW Time. 6 10 14 ns tDS Data Set-up Time 4 6 7 ns tDH Data Hold Time 1 2 2 ns tENS Enable Set-up Time 4 6 7 ns tENH Enable Hold Time 1 2 2 ns tRS Reset Pulse Width[11] 15 25 35 ns tRSR Reset Recovery Time 10 15 20 ns tRSF Reset to Flag and Output Time tPRT Retransmit Pulse Width 15 25 35 ns tRTR Retransmit Recovery Time 15 25 35 ns tOLZ Output Enable to Output in Low Z[12] 0 0 0 ns tOE Output Enable to Output Valid 3 8 3 12 3 15 ns tOHZ Output Enable to Output in High Z[12] 3 8 3 12 3 15 ns tWFF Write Clock to Full Flag 11 15 20 ns tREF Read Clock to Empty Flag 11 15 20 ns 11 40 Max. tS 2 18 Flag[13] 15 2 25 35 ns tPAFasynch Clock to Programmable Almost-Full (Asynchronous mode, VCC/SMODE tied to VCC) 18 22 25 ns tPAFsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 11 15 20 ns tPAEasynch Clock to Programmable Almost-Empty Flag[13] (Asynchronous mode, VCC/SMODE tied to VCC) 18 22 25 ns tPAEsynch Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) 11 15 20 ns tHF Clock to Half-Full Flag 16 20 25 ns Notes: 9. CL = 30 pF for all AC parameters except for t OHZ. 10. CL = 5 pF for t OHZ. 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. 13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). Document #: 38-06029 Rev. *C Page 9 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Characteristics Over the Operating Range (continued) Parameter Description 7C42X5V-15 7C42X5V-25 7C42X5V-35 Min. Min. Min. Max. 10 Max. 15 Max. Unit 20 ns tXO Clock to Expansion Out tXI Expansion in Pulse Width 6.5 10 14 ns tXIS Expansion in Set-up Time 5 10 15 ns tSKEW1 Skew Time between Read Clock and Write Clock for Full Flag 6 10 12 ns tSKEW2 Skew Time between Read Clock and Write Clock for Empty Flag 6 10 12 ns tSKEW3 Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags. 15 18 20 ns Switching Waveforms Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0–D17 tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1[14] RCLK REN Note: 14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Document #: 38-06029 Rev. *C Page 10 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) Read Cycle Timing tCLK tCLKH tCLKL RCLK tENS tENH REN NO OPERATION tREF tREF EF tA Q0–Q17 VALID DATA tOLZ tOHZ tOE OE tSKEW2[15] WCLK WEN Reset Timing[16] RS tRS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF Q0–Q17 [17] OE = 1 OE = 0 Notes: 15. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. 16. The clocks (RCLK, WCLK) can be free-running during reset. 17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1. Document #: 38-06029 Rev. *C Page 11 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK tDS D0–D17 D0 (FIRSTVALID WRITE) D1 D2 D3 D4 tENS tFRL[18] WEN tSKEW2 RCLK tREF EF REN tA [19] tA Q0–Q17 D0 tOLZ D1 tOE OE Empty Flag Timing WCLK tDS tDS D0 D0–D17 tENS D1 tENH tENS tENH WEN tFRL[18] tFRL[18] RCLK tSKEW2 tREF tREF tREF tSKEW2 EF REN OE tA Q0–Q17 D0 Notes: 18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 19. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06029 Rev. *C Page 12 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) Full Flag Timing NO WRITE NO WRITE WCLK tSKEW1 [14] tSKEW1 [14] tDS DATA WRITE DATA WRITE D0–D17 tWFF tWFF tWFF FF WEN RCLK tENS tENH tENH tENS REN OE LOW tA Q0–q17 tA DATAREAD DATA IN OUTPUT REGISTER NEXT DATA READ Half-Full Flag TimingtCLKH tCLKL WCLK tENS tENH WEN tHF HF HALF FULL+1 OR MORE HALF FULL OR LESS HALF FULL OR LESS tHF RCLK tENS REN Document #: 38-06029 Rev. *C Page 13 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) Programmable Almost Empty Flag Timing tCLKL tCLKH WCLK tENS tENH WEN tPAE PAE [20] n+1 WORDS IN FIFO tPAE n WORDS IN FIFO RCLK tENS REN Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW) tCLKL tCLKH WCLK tENS tENH WEN Note 21 PAE tSKEW3 [22] N + 1 WORDS INFIFO tPAEsynch Note 23 tPAEsynch RCLK tENS tENS tENH REN Notes: 20. PAE offset − n. Number of data words into FIFO already = n. 21. PAE offset − n. 22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. Document #: 38-06029 Rev. *C Page 14 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) Programmable Almost Full Flag Timing tCLKL tCLKH Note 24 WCLK tENS tENH WEN tPAF FULL − M WORDS IN FIFO [26] [25] PAF tPAF FULL − (M + 1) WORDS IN FIFO [27] RCLK tENS REN Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW)) tCLKL tCLKH Note 28 WCLK tENS tENH WEN Note 29 PAF tPAF FULL − M WORDS IN FIFO [26] FULL – (M + 1) WORDS IN FIFO tSKEW3[30] tPAFsynch RCLK tENS tENS tENH REN Notes: 24. PAF offset = m. Number of data words written into FIFO already = 64 − m + 1 for the CY7C4425V, 256 − m + 1 for the CY7C4205V, 512 − m + 1 for the CY7C4215V. 1024 − m + 1 for the CY7C4225V, 2048 − m + 1 for the CY7C4235V, and 4096 − m + 1 for the CY7C4245V. 25. PAF is offset = m. 26. 64 − m words in CY7C4425V, 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V, and 4096 – m words in CY7C4245V. 27. 64 − m + 1 words in CY7C4425V, 256 − m + 1 words in CY7C4205V, 512 − m +1 words in CY7C4215V, 1024 − m + 1 CY7C4225V, 2048 − m + 1 in CY74235V, and 4096 − m + 1 words in CY7C4245V. 28. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW. 29. PAF offset = m. 30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge. Document #: 38-06029 Rev. *C Page 15 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) Write Programmable Registers tCLK tCLKL tCLKH WCLK tENS tENH LD tENS WEN tDS tDH PAE OFFSET D0–D17 PAE OFFSET PAF OFFSET D0–D11 Read Programmable Registers tCLK tCLKL tCLKH RCLK tENS tENH LD tENS REN tA Q0–Q17 UNKNOWN PAE OFFSET PAF OFFSET PAE OFFSET Write Expansion Out Timing tCLKH WCLK Note 31 tXO WXO tENS tXO WEN Note: 31. Write to Last Physical Location. Document #: 38-06029 Rev. *C Page 16 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Switching Waveforms (continued) Read Expansion Out Timing tCLKH RCLK Note 32 tXO RXO tXO tENS REN Write Expansion In Timing tXI WXI WCLK tXIS Read Expansion In Timing tXI RXI tXIS RCLK Retransmit Timing[33, 34, 35] FL/RT tPRT tRTR REN/WEN EF/FF and/all async flags HF/PAE/PAF Notes: 32. Read from Last Physical Location. 33. Clocks are free running in this case. 34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. Document #: 38-06029 Rev. *C Page 17 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Ordering Information 64 x 18 Low-Voltage Synchronous FIFO Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C4425V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 25 CY7C4425V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 35 CY7C4425V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 256 x 18 Low-Voltage Synchronous FIFO Speed (ns) 15 Ordering Code Package Name Package Type Operating Range CY7C4205V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial CY7C4205V-15AC A65 64-Lead 14x14 Thin Quad Flatpack CY7C4205V-15ASXC A64 64-Lead Pb-Free 10x10 Thin Quad Flatpack 25 CY7C4205V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 35 CY7C4205V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 512 x 18 Low-Voltage Synchronous FIFO Speed (ns) 15 Ordering Code Package Name Package Type CY7C4215V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial CY7C4215V-15ASXC A64 64-Lead Pb-Free 10x10 Thin Quad Flatpack 25 CY7C4215V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 35 CY7C4215V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 1K x 18 Low-Voltage Synchronous FIFO Speed (ns) 15 Ordering Code Package Name Package Type Operating Range CY7C4225V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial CY7C4225V-15ASXC A64 64-Lead Pb-Free 10x10 Thin Quad Flatpack CY7C4225V-15AC A65 64-Lead 14x14 Thin Quad Flatpack 25 CY7C4225V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 35 CY7C4225V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 2K x 18 Low-Voltage Synchronous FIFO Speed (ns) 15 Ordering Code Package Name Package Type CY7C4235V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial CY7C4235V-15ASXC A64 64-Lead Pb-Free 10x10 Thin Quad Flatpack 25 CY7C4235V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 35 CY7C4235V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Commercial 4K x 18 Low-Voltage Synchronous FIFO Speed (ns) 15 25 35 Ordering Code Package Name Package Type CY7C4245V-15ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245V-15ASXC A64 64-Lead Pb-Free 10x10 Thin Quad Flatpack CY7C4245V-25ASC A64 64-Lead 10x10 Thin Quad Flatpack CY7C4245V-25ASXC A64 64-Lead Pb-Free 10x10 Thin Quad Flatpack CY7C4245V-35ASC A64 64-Lead 10x10 Thin Quad Flatpack Document #: 38-06029 Rev. *C Operating Range Commercial Commercial Commercial Page 18 of 20 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Package Diagrams 64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64 64-Pin Pb-Free Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64 51-85051-*A 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 51-85046-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06029 Rev. *C Page 19 of 20 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V Document History Page Document Title: CY7C4425V/4205V/4215V CY7C4225V/4235V/4245V 64/256/512/1K/2K/4K x 18 Low-Voltage Synchronous FIFOs Document Number: 38-06029 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109961 12/17/01 SZV Change from Spec number: 38-00609 to 38-06029 *A 122281 12/26/02 RBI Power up requirements added to Maximum Ratings Information *B 127856 08/22/03 FSG Fixed read cycle timing diagram Corrected switching waveform diagram typos Page 12: WEN changed to REN (typo) Page 13: WCLK changed to RCLK (typo) *C 393636 See ECN YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C4205V-15ASXC, CY7C4215V-15ASXC, CY7C4225V-15ASXC, CY7C4235V-15ASXC, CY7C4245V-15ASXC, CY7C4245V-25ASXC Document #: 38-06029 Rev. *C Page 20 of 20