DAC0800/DAC0802 8-Bit Digital-to-Analog Converters General Description The DAC0800 series are monolithic 8-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying DAC, monotonic performance over a 40 to 1 reference current range is possible. The DAC0800 series also features high compliance complementary current outputs to allow differential output voltages of 20 Vp-p with simple resistor loads as shown in Figure 1. The reference-to-full-scale current matching of better than ± 1 LSB eliminates the need for full-scale trims in most applications while the nonlinearities of better than ± 0.1% over temperature minimizes system error accumulations. The noise immune inputs of the DAC0800 series will accept TTL levels with the logic threshold pin, VLC, grounded. Changing the VLC potential will allow direct interface to other logic families. The performance and characteristics of the device are essentially unchanged over the full ± 4.5V to ± 18V power supply range; power dissipation is only 33 mW with ± 5V supplies and is independent of the logic input states. The DAC0800, DAC0802, DAC0800C and DAC0802C are a direct replacement for the DAC-08, DAC-08A, DAC-08C, and DAC-08H, respectively. Features n n n n n n n n n n n Fast settling output current: 100 ns Full scale error: ± 1 LSB Nonlinearity over temperature: ± 0.1% Full scale current drift: ± 10 ppm/˚C High output compliance: −10V to +18V Complementary current outputs Interface directly with TTL, CMOS, PMOS and others 2 quadrant wide range multiplying capability Wide power supply range: ± 4.5V to ± 18V Low power consumption: 33 mW at ± 5V Low cost Typical Applications DS005686-1 FIGURE 1. ± 20 VP-P Output Digital-to-Analog Converter (Note 5) Ordering Information Non-Linearity ± 0.1% FS ± 0.19% FS ± 0.19% FS Temperature Order Numbers Range J Package (J16A) (Note 1) N Package (N16E) (Note 1) SO Package (M16A) 0˚C ≤ TA ≤ +70˚C DAC0802LCJ −55˚C ≤ TA ≤ +125˚C DAC0800LJ 0˚C ≤ TA ≤ +70˚C DAC0800LCJ DAC-08HQ DAC0802LCN DAC-08HP DAC0802LCM DAC-08EP DAC0800LCM DAC-08Q DAC-08EQ DAC0800LCN Note 1: Devices may be ordered by using either order number. © 1999 National Semiconductor Corporation DS005686 www.national.com DAC0800/DAC0802 8-Bit Digital-to-Analog Converters June 1999 Absolute Maximum Ratings (Note 2) Storage Temperature Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic) Surface Mount Package Vapor Phase (60 seconds) Infrared (15 seconds) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ − V−) Power Dissipation (Note 3) Reference Input Differential Voltage (V14 to V15) Reference Input Common-Mode Range (V14, V15) Reference Input Current Logic Inputs Analog Current Outputs (VS− = −15V) ESD Susceptibility (Note 4) ± 18V or 36V 500 mW V− to V+ Operating Conditions V− to V+ 5 mA V− to V− plus 36V Temperature (TA) DAC0800L DAC0800LC DAC0802LC 4.25 mA TBD V −65˚C to +150˚C 260˚C 300˚C 215˚C 220˚C (Note 2) Min Max Units −55 0 0 +125 +70 +70 ˚C ˚C ˚C Electrical Characteristics The following specifications apply for VS = ± 15V, IREF = 2 mA and TMIN ≤ TA ≤ TMAX unless otherwise specified. Output characteristics refer to both IOUT and IOUT. DAC0802LC Symbol Parameter DAC0800LC Min Typ Max Min Typ Units Max Resolution 8 8 8 8 8 8 Bits Monotonicity 8 8 8 8 8 8 Bits ± 0.19 %FS ± 0.1 Nonlinearity Settling Time ts DAC0800L/ Conditions To ± 1⁄2 LSB, All Bits Switched 100 135 ns “ON” or “OFF”, TA = 25˚C tPLH, tPHL Propagation Delay DAC0800L 100 135 ns DAC0800LC 100 150 ns ns TA = 25˚C Each Bit 35 60 35 60 All Bits Switched 35 60 35 60 ns ± 10 ± 50 ± 10 ± 50 ppm/˚C 18 V 1.99 2.04 mA µA TCIFS Full Scale Tempco VOC Output Voltage Compliance Full Scale Current Change −10 18 −10 1.992 2.000 1.94 ± 0.5 ± 4.0 ±1 ± 8.0 0.1 1.0 0.2 2.0 µA < 1⁄2 LSB, ROUT > 20 MΩ Typ IFS4 Full Scale Current VREF = 10.000V, R14 = 5.000 kΩ 1.984 R15 = 5.000 kΩ, TA = 25˚C IFSS Full Scale Symmetry IZS Zero Scale Current IFSR Output Current Range IFS4−IFS2 V− = −5V 0 2.0 2.1 0 2.0 2.1 mA V− = −8V to −18V 0 2.0 4.2 0 2.0 4.2 mA 0.8 V Logic Input Levels VIL Logic “0” VIH Logic “1” Logic Input Current VLC = 0V 0.8 2.0 2.0 V VLC = 0V IIL Logic “0” −10V≤VIN≤+0.8V −2.0 −10 −2.0 −10 µA IIH Logic “1” 2V≤VIN≤+18V 0.002 10 0.002 10 µA VIS Logic Input Swing V− = −15V −10 18 −10 18 V VTHR Logic Threshold Range VS = ± 15V −10 13.5 −10 13.5 V I15 Reference Bias Current dl/dt Reference Input Slew Rate (Figure 11) 4.0 PSSIFS+ Power Supply Sensitivity 4.5V≤V+≤18V 0.0001 0.01 0.0001 0.01 %/% −4.5V≤V−≤18V 0.0001 0.01 0.0001 0.01 %/% PSSIFS− −1.0 IREF = 1mA www.national.com 2 −3.0 8.0 −1.0 4.0 −3.0 8.0 µA mA/µs Electrical Characteristics (Continued) The following specifications apply for VS = ± 15V, IREF = 2 mA and TMIN ≤ TA ≤ TMAX unless otherwise specified. Output characteristics refer to both IOUT and IOUT. DAC0802LC Symbol Parameter DAC0800LC Min Power Supply Current DAC0800L/ Conditions Typ Max Min Typ Units Max VS = ± 5V, IREF = 1 mA I+ 2.3 3.8 2.3 3.8 mA I− −4.3 −5.8 −4.3 −5.8 mA VS = 5V, −15V, IREF = 2 mA I+ 2.4 3.8 2.4 3.8 mA I− −6.4 −7.8 −6.4 −7.8 mA VS = ± 15V, IREF = 2 mA I+ 2.5 3.8 2.5 3.8 mA I− −6.5 −7.8 −6.5 −7.8 mA PD Power Dissipation ± 5V, IREF = 1 mA 33 48 33 48 mW 5V,−15V, IREF = 2 mA 108 136 108 136 mW ± 15V, IREF = 2 mA 135 174 135 174 mW Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 3: The maximum junction temperature of the DAC0800 and DAC0802 is 125˚C. For operating at elevated temperatures, devices in the Dual-In-Line J package must be derated based on a thermal resistance of 100˚C/W, junction-to-ambient, 175˚C/W for the molded Dual-In-Line N package and 100˚C/W for the Small Outline M package. Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 5: Pin-out numbers for the DAC080X represent the Dual-In-Line package. The Small Outline package pin-out differs from the Dual-In-Line package. Connection Diagrams Dual-In-Line Package Small Outline Package DS005686-14 Top View DS005686-13 Top View See Ordering Information 3 www.national.com Block Diagram (Note 5) DS005686-2 Typical Performance Characteristics Full Scale Current vs Reference Current LSB Propagation Delay vs IFS Reference Input Frequency Response DS005686-23 DS005686-24 DS005686-22 Curve 1: CC = 15 pF, VIN = 2 Vp-p centered at 1V. Curve 2: CC = 15 pF, VIN = 50 mVp-p centered at 200 mV. Curve 3: CC = 0 pF, VIN = 100 mVp-p centered at 0V and applied through 50Ω connected to pin 14.2V applied to R14. Reference Amp Common-Mode Range Logic Input Current vs Input Voltage VTH — VLC vs Temperature DS005686-27 DS005686-25 DS005686-26 Note. Positive common-mode range is always (V+) − 1.5V. www.national.com 4 Typical Performance Characteristics Output Current vs Output Voltage (Output Voltage Compliance) (Continued) Output Voltage Compliance vs Temperature Bit Transfer Characteristics DS005686-29 DS005686-28 Power Supply Current vs +V DS005686-30 Note. B1–B8 have identical transfer characteristics. Bits are fully switched with less than 1⁄2 LSB error, at less than ± 100 mV from actual threshold. These switching points are guaranteed to lie between 0.8 and 2V over the operating temperature range (VLC = 0V). Power Supply Current vs −V DS005686-31 Power Supply Current vs Temperature DS005686-32 DS005686-33 Equivalent Circuit DS005686-15 FIGURE 2. 5 www.national.com Typical Applications DS005686-5 IO + IO = IFS for all logic states For fixed reference, TTL operation, typical values are: VREF = 10.000V RREF = 5.000k R15 ≈ RREF CC = 0.01 µF VLC = 0V (Ground) FIGURE 3. Basic Positive Reference Operation (Note 5) DS005686-16 DS005686-21 FIGURE 4. Recommended Full Scale Adjustment Circuit (Note 5) Note. RREF sets IFS; R15 is for bias current cancellation FIGURE 5. Basic Negative Reference Operation (Note 5) DS005686-17 IO mA IOmA EO EO Full Scale B1 B2 B3 B4 B5 B6 B7 B8 1 1 1 1 1 1 1 1 1.992 0.000 −9.960 0.000 Full Scale−LSB 1 1 1 1 1 1 1 0 1.984 0.008 −9.920 −0.040 Half Scale+LSB 1 0 0 0 0 0 0 1 1.008 0.984 −5.040 −4.920 Half Scale 1 0 0 0 0 0 0 0 1.000 0.992 −5.000 −4.960 Half Scale−LSB 0 1 1 1 1 1 1 1 0.992 1.000 −4.960 −5.000 Zero Scale+LSB 0 0 0 0 0 0 0 1 0.008 1.984 −0.040 −9.920 Zero Scale 0 0 0 0 0 0 0 0 0.000 1.992 0.000 −9.960 FIGURE 6. Basic Unipolar Negative Operation (Note 5) www.national.com 6 Typical Applications (Continued) DS005686-6 B1 B2 B3 B4 B5 B6 B7 B8 EO EO Pos. Full Scale 1 1 1 1 1 1 1 1 −9.920 +10.000 Pos. Full Scale−LSB 1 1 1 1 1 1 1 0 −9.840 +9.920 Zero Scale+LSB 1 0 0 0 0 0 0 1 −0.080 +0.160 Zero Scale 1 0 0 0 0 0 0 0 0.000 +0.080 Zero Scale−LSB 0 1 1 1 1 1 1 1 +0.080 0.000 Neg. Full Scale+LSB 0 0 0 0 0 0 0 1 +9.920 −9.840 Neg. Full Scale 0 0 0 0 0 0 0 0 +10.000 −9.920 FIGURE 7. Basic Bipolar Output Operation (Note 5) DS005686-18 If RL = RL within ± 0.05%, output is symmetrical about ground B1 B2 B3 B4 B5 B6 B7 B8 EO Pos. Full Scale 1 1 1 1 1 1 1 1 +9.960 Pos. Full Scale−LSB 1 1 1 1 1 1 1 0 +9.880 (+)Zero Scale 1 0 0 0 0 0 0 0 +0.040 (−)Zero Scale 0 1 1 1 1 1 1 1 −0.040 Neg. Full Scale+LSB 0 0 0 0 0 0 0 1 −9.880 Neg. Full Scale 0 0 0 0 0 0 0 0 −9.960 FIGURE 8. Symmetrical Offset Binary Operation (Note 5) DS005686-19 For complementary output (operation as negative logic DAC), connect inverting input of op amp to IO (pin 2), connect IO (pin 4) to ground. FIGURE 9. Positive Low Impedance Output Operation (Note 5) 7 www.national.com Typical Applications (Continued) DS005686-20 For complementary output (operation as a negative logic DAC) connect non-inverting input of op am to IO (pin 2); connect IO (pin 4) to ground. FIGURE 10. Negative Low Impedance Output Operation (Note 5) DS005686-10 Typical values: RIN = 5k,+VIN = 10V FIGURE 11. Pulsed Reference Operation (Note 5) DS005686-9 VTH = VLC + 1.4V 15V CMOS, HTL, HNIL VTH = 7.6V Note. Do not exceed negative logic input range of DAC. FIGURE 12. Interfacing with Various Logic Families DS005686-12 (b) +VREF must be above peak positive swing of VIN DS005686-11 (a) IREF ≥ peak negative swing of IIN FIGURE 13. Accommodating Bipolar References (Note 5) www.national.com 8 Typical Applications (Continued) DS005686-7 FIGURE 14. Settling Time Measurement (Note 5) DS005686-8 Note. For 1 µs conversion time with 8-bit resolution and 7-bit accuracy, an LM361 comparator replaces the LM319 and the reference current is doubled by reducing R1, R2 and R3 to 2.5 kΩ and R4 to 2 MΩ. FIGURE 15. A Complete 2 µs Conversion Time, 8-Bit A/D Converter (Note 5) 9 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Outline Package (SO) Order Numbers DAC0800LCM, or DAC0802LCM NS Package Number M16A Molded Small Outline Package (SO) Order Numbers DAC0800LCM, or DAC0802LCM NS Package Number M16A www.national.com 10 DAC0800/DAC0802 8-Bit Digital-to-Analog Converters Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package Order Numbers DAC0800, DAC0802 NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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