4 Megabit High Speed CMOS SRAM DPS256X16Cn3/DPS256X16Bn3 DESCRIPTION: The DPS256X16Cn3/DPS256X16Bn3 High Speed SRAM ‘’STACK’’ modules are a revolutionary new memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC). Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages, or mounted on a 50-pin PGA co-fired ceramic substrate. The module packs 4-Megabits of low-power CMOS static RAM in an area as small as 0.463 in2, while maintaining a total height as low as 0.349 inches. The DPS256X16Cn3/DPS256X16Bn3 STACK modules contain four individual 128K x 8 SRAMs, each packaged in a hermetically sealed SLCC, making the modules suitable for commercial, industrial and military applications. The DPS256X16Bn3 has one active low Chip Enable (CE) and while the DPS256X16Cn3 an active low Chip Enable (CE) and an active high Select Line (SEL). SLCC Stack Straight Leaded Stack By using SLCCs, the ‘’Stack’’ family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. FEATURES: • • • • • • • • Organizations Available: 256Kx16 or 512Kx8 Access Times: 20*, 25, 30, 35, 45ns Fully Static Operation - No clock or refresh required Single +5V Power Supply, ±10% Tolerance TTL Compatible Common Data Inputs and Outputs Low Data Retention Voltage: 2.0V min. Packages Available: 48 - Pin SLCC Stack 48 - Pin Straight Leaded Stack 48 - Pin ‘’J’’ Leaded Stack 48 - Pin Gullwing Leaded Stack 50 - Pin PGA Dense-Stack ‘’J’’ Leaded Stack * Commercial only. Gullwing Leaded Stack Dense-Stack 30A097-34 REV. G This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. FUNCTIONAL BLOCK DIAGRAM A0 - A16 I/O0 - I/O15 CE0 - CE3 SEL0, SEL1 WE OE VDD VSS N.C. PIN NAMES Address Inputs Data Input/Output Low Chip Enables High Chip Enables Write Enable Output Enable Power (+5V) Ground No Connect NOTE: SEL0 and SEL1 apply to DPS256X16Cn3 version only. PIN-OUT DIAGRAM 48 - PIN LEADLESS STACK 48 - PIN STRAIGHT LEADED STACK 48 - PIN ‘’J’’ LEADED STACK 48 - PIN GULLWING LEADED STACK 50 - PIN PGA DENSE-STACK NOTE: SEL0 and SEL1 apply to DPS256X16Cn3 version only, No Connect for DPS256X16Bn3 version. 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A097-34 REV. G DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. RECOMMENDED OPERATING RANGE 3 TRUTH TABLE Symbol Characteristic Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V VIH Input HIGH Voltage 2.2 VDD+0.3 V VIL Input LOW Voltage -0.52 0.8 V M/B -55 +25 +125 Operating o TA I -40 +25 +85 C Temperature C 0 +25 +70 Mode SEL CE WE Not Selected Not Selected DOUT Disable Read Write L X H H H X H L L L X X H H L H = HIGH Supply OE I/O Pin Current X High-Z Standby X High-Z Standby H High-Z Active L DOUT Active X DIN Active L = LOW X = Don’t Care NOTE: SEL applies to DPS256X16Cn3 version only. DC OUTPUT CHARACTERISTICS Symbol Parameter VOH HIGH Voltage VOL LOW Voltage Conditions Min. Max. Unit IOH= -4.0mA 2.4 V IOL=8.0mA 0.4 V ABSOLUTE MAXIMUM RATINGS Symbol TSTC TBIAS VDD VI/O 3 Parameter Value Storage Temperature -65 to +150 Temperature Under Bias -55 to +125 Supply Voltage 1 -0.5 to +7.0 Input/Output Voltage 1 -0.5 to VDD+0.5 Unit °C °C °C V CAPACITANCE 4: TA = 25°C, F = 1.0MHz Symbol Parameter CADR Address Input CCE Chip Enable CSEL Active High Chip Select CWE Write Enable COE Output Enable CI/O Data Input/Output Max. 40 15 25 40 40 25 Unit Condition pF VIN2 = 0V NOTE: CSEL applies to DPS256X16Cn3 version only. DC OPERATING CHARACTERISTICS: Over operating ranges Symbol IIN IOUT ICC ISB1 ISB2 IDR3 IDR2 VOL VOH Characteristics Input Leakage Current Output Leakage Current Operating Supply Current Full Standby Supply Current Standby Current (TTL) Data Retention Supply Current (3.0V) Data Retention Supply Current (2.0V) Output Low Voltage Output High Voltage Test Conditions VIN = 0V to VDD VI/O = 0V to VDD, CE or OE = VIH, or WE = VIL X8 Cycle=min., Duty=100% IOUT = 0mA X16 VIN ≥ VDD -0.2V or VIN ≤ VSS +0.2V CE = VIH VDR = 3.0V, CE ≥ VDR -0.2V, (or SEL ≤ 0.2V, VIN ≥ VDD -0.2V or VIN ≤ +0.2V) VDR = 2.0V, CE ≥ VDR -0.2V, (or SEL ≤ 0.2V, VIN ≥ VDD -0.2V or VIN ≤ +0.2V) IOUT = 8.0mA IOUT = -4.0mA C I M/B Typ. (†) Min. Max. Min. Max. Min. Max. - -20 +20 -20 +20 -20 +20 µA - -20 +20 -20 +20 -20 Unit +20 µA 175 250 230 340 245 350 265 390 mA 1.6 20 20 40 mA 100 120 140 140 mA 0.28 1.6 2.4 8.0 mA 0.14 1.0 1.6 7.2 mA 0.4 V V - 0.4 2.4 0.4 2.4 2.4 † Typical measurements made at +25oC, Cycle = min., VDD = 5.0V. NOTE: Test Conditions in parenthesis apply to DPS256X16Cn3 version only. 30A097-34 REV. G Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels 0V to 3.0V 5ns Figure 1. Output Load * Including Probe and Jig Capacitance. +5V 1.5V 480Ω OUTPUT LOAD Load CL 1 100pF 2 5pF DOUT Parameters Measured except tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ tLZ1, tLZ2, tHZ1, tHZ2, tOHZ, tOLZ, and tWHZ CL* 255Ω NOTE: tLZ2 and tHZ2 apply to DPS256X16Cn3 version only. Data Retention AC Characteristics Symbol VDR VCDR tR Parameter VDD for Data Retention Chip Disable to Data Retention Time Operation Recovery Time Test Conditions CE ≥ VDR -0.2V, (SEL ≥ VDR -0.2V, or VIN ≤ VDR -0.2V or VIN ≤ 0.2V) 8 Min. Typ. Max. Unit 2.0 - - V See Data Retention Waveform 0 - - ns See Data Retention Waveform 5 - - ms NOTE: Test Conditions in parenthesis apply to DPS256X16Cn3 version only. DATA RETENTION WAVEFORM: CE Controlled. VDD 4.5V 2.3V VDR1 CE ≥ VDD -0.2V CE 0V DATA RETENTION WAVEFORM: SEL Controlled. (Applies to DPS256X16Cn3 only) VDD 4.5V SEL VDR2 0.4V 0V 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 SEL ≤ -0.2V 30A097-34 REV. G DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 tRC tAA tCO1 tCO2 tOE tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ tOH 20ns* Parameter Min. Read Cycle Time Address Access Time CE to Output Valid SEL to Output Valid Output Enable to Output Valid CE to Output in LOW-Z 4, 5 SEL to Output in LOW-Z 4, 5 Output Enable to Output in LOW-Z 4, 5 CE to Output in HIGH-Z 4, 5 SEL to Output in HIGH-Z 4, 5 Output Enable to Output in HIGH-Z 4, 5 Output Hold from Address Change Max. 25ns Min. 20 Max. 25 20 20 20 8 30ns Min. 30 25 25 25 10 3 3 0 3 3 0 10 10 8 3 35ns Min. 3 3 0 45ns Min. 3 3 0 45 45 45 25 3 3 0 20 20 20 3 Max. 45 35 35 35 20 15 15 15 3 Max. 35 30 30 30 15 12 12 10 3 Max. 25 25 25 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns * Available in Commercial Only. NOTE: tCO2, tLZ2 and tHZ2 apply to DPS256X16Cn3 version only. READ CYCLE ADDRESS CE SEL OE DATA I/O NOTE: SEL, tCO2, tLZ2 and tHZ2 apply to DPS256X16Cn3 version only. WAVEFORM KEY Data Valid Transition from HIGH to LOW 30A097-34 REV. G Powered by ICminer.com Electronic-Library Service CopyRight 2003 Transition from LOW to HIGH Data Undefined or Don’t Care 5 DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges No. Symbol 13 14 15 16 17 18 19 20 21 22 tWC tAW tCW tAS tWP tWR tWHZ tDW tDH tOW 20ns* Parameter Min. Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-Up Time ** Write Pulse Width Write Recovery Time Write Enable to Output in HIGH-Z 4, 5 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write Max. 20 15 15 0 15 0 25ns Min. Max. 25 20 20 0 20 0 8 12 0 3 30ns Min. Max. 30 25 25 0 25 0 10 15 0 3 35ns Min. 35 30 30 0 30 0 12 15 0 3 Max. 45ns Min. 45 40 40 0 35 0 15 20 0 3 Max. 20 25 0 3 Unit ns ns ns ns ns ns ns ns ns ns * Available in Commercial Only. ** Valid for both Read and Write Cycles. WRITE CYCLE 1: CE Controlled. 8 ADDRESS CE WE DATA IN DATA OUT NOTES: 1. 2. 3. 4. All voltages are with respect to VSS. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level). Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This parameter is guaranteed and not 100% tested. 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 5. 6. 7. 8. 9. Transition is measured at the point of ±500mV from steady state voltage. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied. The outputs are in a high impedance state when WE is LOW. SEL timing is the same as CE timing (Valid for DPS256X16Cn3 only). The Waveform is inverted. Chip Enable and Write Enable can initiate and terminate WRITE Cycle. 30A097-34 REV. G Dense-Pac Microsystems, Inc. DPS256X16Cn3/DPS256X16Bn3 WRITE CYCLE 2: WE Controlled. OE is HIGH. 8, 9 ADDRESS CE WE DATA IN DATA OUT WRITE CYCLE 3: WE Controlled. OE is LOW. 8, 9 ADDRESS CE WE DATA IN DATA OUT 30A097-34 REV. G Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. (48 - PIN LEADLESS STACK) MECHANICAL DRAWING (48 - PIN STRAIGHT LEADED STACK) MECHANICAL DRAWING 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A097-34 REV. G Dense-Pac Microsystems, Inc. DPS256X16Cn3/DPS256X16Bn3 (48 - PIN ‘’J’’ LEADED STACK) MECHANICAL DRAWING (48 - PIN GULLWING LEADED STACK) MECHANICAL DRAWING 30A097-34 REV. G Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 DPS256X16Cn3/DPS256X16Bn3 Dense-Pac Microsystems, Inc. (50 - PIN PGA) MECHANICAL DRAWING ORDERING INFORMATION Dense-Pac Microsystems, Inc. 7321 Lincoln Way u Garden Grove, California 92841-1428 (714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 u http://www.dense-pac.com 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A097-34 REV. G