8 Megabit FLASH EEPROM DPZ512X16In3 DESCRIPTION: DPZ512X16IY3 The DPZ512X16In3 ‘’STACK’’ modules are a revolutionary new memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC). Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages, or mounted on a 50-pin PGA co-fired ceramic substrate. The module packs 8-Megabits of FLASH EEPROM in an area as small as 0.463 in2, while maintaining a total height as low as 0.349 inches. The DPZ512X16In3 STACK modules contain four individual SLCC packages each containing two 128K x 8 FLASH memory devices. Each SLCC is hermetically sealed making the module suitable for commercial, industrial and military applications. By using SLCCs, the ‘’Stack’’ family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. DPZ512X16II3 FEATURES: • Organization: 512K x 16 or 1 Meg x 8 Fast Access Times (max.): 120, 150, 170, 200, 250ns Fully Static Operation - No clock or refresh required • TTL Compatible Inputs and Outputs • Common Data Inputs and Outputs 10,000 Erase/Program Cycles (min.) Packages Available: 48 - Pin SLCC Stack 48 - Pin Straight Leaded Stack 48 - Pin ‘’J’’ Leaded Stack 48 - Pin Gullwing Leaded Stack 50 - Pin PGA Dense-Stack • • • • DPZ512X16IA3 30A071-11 REV. E DPZ512X16IJ3 DPZ512X16IH3 This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 DPZ512X16In3 Dense-Pac Microsystems, Inc. FUNCTIONAL BLOCK DIAGRAM PIN NAMES A0 - A16 I/O0 - I/O15 CE0 - CE7 WE OE VPP VDD VSS N.C. Address Inputs Data Input/Output Chip Enables * Write Enable Output Enable Programming Voltage (+12.0V) Power (+5V) Ground No Connect * CE0, CE2, CE4 and CE6 control I/O0 - I/O7, CE1, CE3, CE5 and CE7 control I/O8 - I/O15. PIN-OUT DIAGRAM 48 - PIN LEADLESS STACK 48 - PIN STRAIGHT LEADED STACK 48 - PIN ‘’J’’ LEADED STACK 48 - PIN GULLWING LEADED STACK 50 - PIN PGA DENSE-STACK 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A071-11 REV. E DPZ512X16In3 Dense-Pac Microsystems, Inc. DEVICE OPERATION: The FLASH devices are electrically erasable and programmable memories that function similarly to an EPROM device, but can be erased without being removed from the system and exposed to ultraviolet light. Each 128K x 8 device can be erased individually eliminating the need to re-program the entire module when partial code changes are required. READ: With VPP = 0V to VDD (VPPLO), the devices are read-only memories and can be read like a standard EPROM. By selecting the device to be read (see Truth Table and Functional Block Diagram), the data programmed into the device will appear on the appropriate I/O pins. When VPP = +12.0V ± 0.6V (VPPHI), reads can be accomplished in the same manner as described above but must be preceded by writing 00H1 to the command register prior to reading the device. When VPP is raised to VPPHI the contents of the command register default to 00H1 and remain that way until the command register is altered. STANDBY: When the appropriate CE‘s are raised to a logic-high level, the standby operation disables the FLASH devices reducing the power consumption substantially. The outputs are placed in a high- impedance state, independent of the OE input. If the module is deselected during programming or erase, the device upon which the operation was being performed will continue to draw active current until the operation is completed. PROGRAM: The programming and erasing functions are accessed via the command register when high voltage is applied to VPP. The contents of the command register control the functions of the memory device (see Command Definition Table). The command register is not an addressable memory location. The register stores the address, data, and command information required to execute the command. When VPP = VPPLO the command register is reset to 00H1 returning the device to the read-only mode. The command register is written by enabling the device upon which that the operation is to be performed (see Functional Block Diagram). While the device is enabled bring WE to a logic-low (VIL). The address is latched on the falling edge of WE and data is latched on the rising edge of WE. 1 Programming is initiated by writing 40H (program setup command) to the command register. On the next falling edge of WE the address to be programmed will be latched, followed by the data being latched on the rising edge of WE (see AC Operating and Characteristics Table). PROGRAM VERIFY: The FLASH devices are programmed one location at a time. Each location may be programmed sequentially or at random. Following each programming operation, the data written must be verified. 1 To initiate the program-verify mode, C0H must be written to the command register of the device just programmed. The programming operation is terminated on the rising edge of WE. The program-verify command is then written to the command register. After the program-verify command is written to the command register, the memory device applies an internally generated 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 margin voltage to the location just written. After waiting 6µs the data written can be verified by doing a read. If true data is read from the device, the location write was successful and the next location may be programmed. If the device fails to verify, the program/verify operation is repeated up to 25 times. ERASE: The erase function is a command-only operation and can only be executed while VPP = VPPHI. To setup the chip-erase, 20H1 must be written to the command register. The chip-erase is then executed by once again writing 20H1 to the command register (see AC Operating and Characteristics Table). To ensure a reliable erasure, all bits in the device to be erased should be programmed to their charged state (data = 00H) prior to starting the erase operation. With the algorithm provided, this operation should typically take 2 seconds. HIGH PERFORMANCE PARALLEL ERASURE: Dense-Pac recommends that all users implement the following Intel High Performance Parallel Erase algorithm in order to avoid the possibility of over erasing these parts. In applications containing more than one FLASH memory, you can erase each device serially or you can reduce total erase time by implementing a parallel erase algorithm. You may save time by erasing all devices at the same time. However, since FLASH memories may erase at different rates, you must verify each device separately. This can be done in a word-wise fashion with the Command Register Reset Command and a special masking algorithm. Take for example the case of two-device (parallel) erasure. The CPU first writes the data word erase command 2020H twice in succession. This starts erasure. After 10ms, the CPU writes the data word verify command A0A0H to stop erasure and setup erase verification. If both one or both bytes are not erased at the given address, the CPU implements the erase sequence again without incrementing the address. Suppose at the given address only the low byte verifies FFH data? Could the whole chip be erased? The answer is yes. Rather than check the rest of the low byte addresses independently of the high byte, simply use the reset command to mask the low byte from erasure and erase verification on the next erase loop. In this example the erase command would be 20FFH and the verify command would be A0FFH. Once the high byte verifies at the address, the CPU modifies the command back to the default 2020H and A0A0H, increments to the next address, and then writes the verify command. See Figure 4 for a conceptual view of the parallel erase flow chart and Figure 4 for the detailed version. These flow charts are for the 16-bit systems and can be expanded for 32-bit designs. ERASE VERIFY: The erase operation erases all locations in the device selected in parallel. Upon completion of the erase operation, each location must be verified. This operation is initiated by writing A0H1 to the command register. The address to be verified must be supplied in order to be latched on the falling edge of WE. The memory device internally generates a margin voltage and applies it to the addressed location. If FFH is read from the 3 DPZ512X16In3 Dense-Pac Microsystems, Inc. device, it indicates the location is erased. The erase/verify command is issued prior to each location verification to latch the address of the location to be verified. This continues until FFH is not read from the device or the last address for the device being erased is read. If FFH is not read from the location being verified, an additional erase operation is performed. Verification then resumes from the last location verified. Once all locations in the device being erased are verified, the erase operation is complete. The verify operation should now be terminated by writing a valid command such as program set-up to the command register. a read from address location 0000H outputs the manufacturer’s code (89H). A read from address location 0001H outputs the device code (B4H). To terminate the operation, it is necessary to write another valid command into the register. PRODUCT I.D. OPERATION: POWER SUPPLY DECOUPLING: POWER UP/DOWN PROTECTION: The FLASH devices are designed to protect against accidental erasure or programming during power transitions. It makes no difference as to which power supply, VPP or V DD, powers up first. Power supply sequencing is not required. Internal circuitry ensures that the command register is reset to the read mode upon power up. The product I.D. operation outputs the manufacturer code (89H) and the device code (B4H). This allows programming equipment to match the device with the proper erase and programming algorithms. With CE and OE at a logic low level, raising A9 to VID (see DC Operating Characteristics) will initiate the operation. The manufacturer’s code can then be read from address location 0000H and the device code can be read from address location 0001H. The I.D. codes can also be accessed via the command register. Following a write of 90H to the command register, VPP traces should use trace widths and layout considerations comparable to that of the VDD power bus. The VPP supply traces should also be decoupled to help decrease voltage spikes. While the memory module has high-frequency, low-inductance decoupling capacitors mounted on the substrate connected to V DD and VSS , it is recommended that a 4.7µF to 10µF electrolytic capacitor be placed near the memory module connected across V DD and VSS for bulk storage. Decoupling capacitors should also be placed near the module, connected across VPP and VSS. COMMAND DEFINITION TABLE Bus Cycles Req’d Command First Bus Cycle Operation Address Second Bus Cycle Data 1 Operation Address Data 1 Read Memory 1 Write X 00H - - - Setup Erase / Erase 2 Write X 20H Write X 20H Erase Verify 2 Write EA A0H Read X EVD Setup Program / Program 2 Write X 40H Write PA PD Program Verify 2 Write X C0H Read X PVD Reset 2 Write X FFH Write X FFH Read Product I.D. Codes 3 Write X 90H Read IA ID EA = EVD = IA = ID = Address to Verify Data Read from Location EA Address: 0000H for manufacturing code, 0001H for device code ID data read from IA during product ID operation (Manufacturer = 89H, Device = B4H) PA = Address to Program PD = Data to be Programmed at Location PA PVA = Data to be Read from Location PA at Program Verify TRUTH TABLE Mode READ ONLY COMMAND PROGRAM Description CEn WE OE A0 A9 VPP I/O Pins Supply Current Not Selected H X X X X VPPLO HIGH-Z Standby Output Disable L H H X X VPPLO HIGH-Z Active Read L H L A0 A9 VPPLO DOUT Active Active I.D. (Mfr.) L H L L VID VPPLO DOUT =89H I.D. (Device) L H L H VID VPPLO DOUT = B4H Active Not Selected H X X X X VPPHI HIGH-Z Standby Output Disable L H H X X VPPHI HIGH-Z Active Read L H L A0 A9 VPPHI DOUT Active Write L L H A0 A9 VPPHI DIN Active L = LOW, H = HIGH, X = Don’t Care 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A071-11 REV. E DPZ512X16In3 Dense-Pac Microsystems, Inc. RECOMMENDED OPERATING RANGE2 Symbol Characteristic ABSOLUTE MAXIMUM RATINGS 7 Value Unit 4.5 5.0 5.5 V TSTC Storage Temperature -65 to +150 °C Programming Voltage 11.4 12.0 12.6 V TBIAS Temperature Under Bias -55 to +125 °C VIL Input LOW Voltage -0.53 0.8 V VID Voltage on A9 2 -0.5 to +14.0 4, 5 V VIH Input HIGH Voltage 2.0 VDD+0.5 V IOUT Output Short Circuit Current TA Operating Temperature VDD Supply Voltage VPP VID Min. Typ. Max. Unit Symbol C 0 +25 I -40 +25 +85 M/B -55 +25 +125 A9 I.D. Input/Output +70 11.5 °C 13.0 V Parameter 100 2 VI/O Input/Output Voltage VPP VPP Supply Voltage 2 During Erase/Program VDD Supply Voltage 6 mA -0.5 to +7.0 3 V -0.5 to +14.0 4 V -0.6 to +7.0 4 V 2 CAPACITANCE 7: TA = 25°C, F = 1.0MHz Symbol CADR Parameter Max. Address Input 50 CCE Chip Enable 15 CWE Write Enable 50 COE Output Enable 50 CI/O Data Input/Output 50 Unit pF Condition DC OUTPUT CHARACTERISTICS Symbol Parameter Condition VOH HIGH Voltage IOH= -2.5mA VOL LOW Voltage IOL=5.8mA VIN3 = 0V Min. Max. Unit 2.4 V 0.45 V DC OPERATING CHARACTERISTICS: Over operating ranges Symbol Characteristics Test Conditions Limits Min. Max. Unit Input Leakage Current VIN = 0V to VDD -8 +8 µA IOUT Output Leakage Current VI/O = 0V to VDD, CE or OE = VIH, or WE = V IL -40 +40 µA ICC1 Operating Supply Current CE = VIL, VIN = VIL or VIH, IOUT = 0mA, f = 8MHz 70 mA ICC2 VDD Programming Current Programming in Progress 70 mA ICC3 VDD Erase Current Erasure in Progress 70 mA ISB1 Standby Current (TTL) CE = VIH 8 mA ISB2 Full Standby Supply Current (CMOS) CE = VDD -0.2V 0.8 mA IPPS VPP Leakage Current VPP = VPPLO 80 µA IPP1 VPP Read Current VPP = VPPHI 1.6 mA IIN IPP2 VPP Programming Current VPP = VPPHI, Programming in Progress 65 mA IPP3 VPP Erase Current VPP = VPPHI, Erasure in Progress 65 mA IID A9 I.D. Current A9 = VID, CE = OE = VIL, WE = VIH 1.0 mA 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 DPZ512X16In3 Dense-Pac Microsystems, Inc. AC TEST CONDITIONS Input Pulse Levels 0V to 3.0V Input Pulse Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Timing Reference Levels During Verify 0.8V and +2.4V Figure 1. Output Load * Including Probe and Jig Capacitance. 1N914 3.3KΩ DEVICE UNDER TEST OUTPUT LOAD Load CL 1 100 pF 2 30pF 1.3V DOUT CL* Parameters Measured except tDF, tLZ and tOLZ tDF, tLZ and tOLZ AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges No. Symbol Parameter 120ns 150ns 170ns 200ns 250ns Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 120 150 170 200 250 Unit 1 tRC Read Cycle Time 2 tCE Chip Enable Access Time 120 150 170 200 250 ns 3 tACC Address Access Time 120 150 170 200 250 ns 4 tOE Output Enable Access Time 50 55 60 60 65 5 tLZ Chip Enable to Output in LOW-Z 7, 8 0 6 tOLZ Output Enable to Output in LOW-Z 7, 8 0 7 tDF Output Disable to Output in HIGH-Z 7, 8 tOH Output Hold from Address, CE or OE Change (whichever occurs first) 8 0 0 0 30 0 0 0 35 0 0 0 40 0 0 ns ns 0 45 ns ns 60 0 ns ns AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE: Over operating ranges No. Symbol Parameter 120ns 150ns 170ns 200ns 250ns Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 120 150 170 200 250 Unit 9 tWC Write Cycle Time 10 tAS Address Setup Time 0 0 0 0 0 ns ns 11 tAH Address Hold Time 60 60 60 60 60 ns 12 tDS Data Setup Time 50 50 50 50 50 ns 13 tDH Data Hold Time 10 10 10 10 10 ns 14 tWR Write Recovery Time before Read 6 6 6 6 6 µs 15 tRR Read Recover Time before Write 0 0 0 0 0 ns 16 tCS Chip Enable Setup Time before Write 20 20 20 20 20 ns 17 tCH Chip Enable Hold Time 0 0 0 0 0 ns 18 tWP Write Pulse Width 9 80 80 80 80 80 ns 19 tWPH Write Pulse Width HIGH 9 20 20 20 20 20 ns 20 tDP Duration of Programming Operation 10 10 10 10 10 µs 21 tDE Duration of Erase Operation 9.5 22 tVPEL VPP Setup Time to Chip Enable LOW 4 1.0 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10.5 9.5 1.0 10.5 9.5 1.0 10.5 9.5 1.0 10.5 9.5 1.0 10.5 ms µs 30A071-11 REV. E DPZ512X16In3 Dense-Pac Microsystems, Inc. READ CYCLE ADDRESS CE OE WE DATA OUT VDD 5.0V 0V ERASE CYCLE ADDRESS CE OE WE DATA I/O VDD VPP 5.0V 0V VPPH VPPL 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 DPZ512X16In3 Dense-Pac Microsystems, Inc. PROGRAMMING CYCLE 9 ADDRESS CE OE WE DATA I/O VDD VPP 5.0V 0V VPPH VPPL Alternative Write Timing CE WE NOTES: 1. Each SLCC contains two FLASH memory devices enabled by separate chip enables. Typically this module would be used as a x16 device with CE0 and CE1 tied together. When writing commands to the Command Register under these conditions, the command shown in the Command Definition Table should be duplicated to each byte (I/O0 - I/O7, I/O8 - I/O15) of the module. If the command to be written is 40H like that for Setup Program/Program, 4040H would be written to the module followed by the 16 bit data. A single device can be programmed or erased by writing the appropriate command to the device the operation is to be performed on while 00H is written to the other devices that are enabled at the same time. Care must be taken when doing Program Verify on a single device. Make certain that no other devices are driving the data bus of the devices that are not being verified but are enabled along with the device that is being verified. Any device that is enabled during Program Verify will be driving the data bus with the data that is programmed at that address. 2. All voltages are with respect to V SS. 3. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level). 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4. Maximum DC voltage on VPP or A9 may over shoot to +14.0V for periods less than 20ns. 5. Output shorted for no more than 1 second. No more than one output shorted at a time. 6. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7. This parameter is guaranteed and not 100% tested. 8. Transition is measured at the point of ±500mV from steady state voltage. 9. Chip Enable Controlled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable. In systems where Chip Enable defines the write pulse width (within a longer Write Enable timing waveform) all Set-up, Hold, and inactive Write Enable times should be measured relative to the Chip Enable waveform. 30A071-11 REV. E DPZ512X16In3 Dense-Pac Microsystems, Inc. FIGURE 2: WRITE ALGORITHM 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 DPZ512X16In3 Dense-Pac Microsystems, Inc. FIGURE 3: ERASE ALGORITHM 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A071-11 REV. E Dense-Pac Microsystems, Inc. DPZ512X16In3 FIGURE 4: HIGH PERFORMANCE PARALLEL ERASURE (Conceptual Device) NOTE: [1] You mask the device by substituting a reset command for the erase and verify commands, that way the erased byte idles through the next erase loop. 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 DPZ512X16In3 Dense-Pac Microsystems, Inc. FIGURE 5: PARALLEL ERASE FLOW CHART NOTES: [1] Wait for VPP to stabilize. [2] Use Quick-Pulse Programming algorithm. [3] Initialize Variables: PLSCNT_HI = High Byte Pulse Counter PLSCNT_LO = Low Byte Pulse Counter FLAG = Erase Error Flag ADRS = Address E_COM = Erase Command V_COM = Verify Command [4] Erase Verify Command stops erasure. [5] See Figure 6 for subroutine. [6] When both devices at ADRS are erased, F_DATA = FFFFH. [7] Reset commands to default E_COM = 2020H, V_COM = A0A0H before verifying next ADRS. [8] Reset device for read operation. 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A071-11 REV. E Dense-Pac Microsystems, Inc. DPZ512X16In3 FIGURE 6: DEVICE ERASE VERIFY AND MASK SUBROUTINE NOTES: [1] This subroutine masks the High byte or Low Byte of the Erase and Verify commands from executing during the next operation. [2] Mask the High byte with 00H. [3] If the Low byte verifies erasure, then mask the next erase and verify commands with FFH (reset). [4] If the Low byte does not verify, increment its pulse counter. [5] Check for max. count. FLAG = 1 denotes a Low byte error. [6] Repeat sequence for High byte. [7] FLAG = 2 denotes a High byte error. FLAG = 3 denotes both High byte and Low byte errors. 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 13 DPZ512X16In3 Dense-Pac Microsystems, Inc. (48 - PIN LEADLESS STACK) MECHANICAL DRAWING (48 - PIN STRAIGHT LEADED STACK) MECHANICAL DRAWING 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A071-11 REV. E Dense-Pac Microsystems, Inc. DPZ512X16In3 (48 - PIN ‘’J’’ LEADED STACK) MECHANICAL DRAWING (48 - PIN GULLWING LEADED STACK) MECHANICAL DRAWING 30A071-11 REV. E Powered by ICminer.com Electronic-Library Service CopyRight 2003 15 DPZ512X16In3 Dense-Pac Microsystems, Inc. (50 - PIN PGA) MECHANICAL DRAWING ORDERING INFORMATION Dense-Pac Microsystems, Inc. 7321 Lincoln Way u Garden Grove, California 92841-1428 (714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 u http://www.dense-pac.com 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 30A071-11 REV. E