Freescale Semiconductor, Inc. Addendum DSP56303UMAD/D Rev. 1, 11/2002 DSP56303 User’s Manual Addendum Freescale Semiconductor, Inc... CONTENTS 1 Introduction ...............1 2 Modified Signal Definitions .................1 3 Operating Mode Register (OMR) Layout and Definition............2 4 Bus Control Register (BCR) Layout and Definition...................3 5 SCI Receive Register (SRX) Description .....3 6 Updated Programming Sheets.........................3 1 Introduction This document provides updated information for revision 1 of the DSP56303 User’s Manual (DSP56303UM/D). The updates include the following: • • • • • Modified signal definitions New Operating Mode Register (OMR) layout and bit definitions New Bus Control Register (BCR) layout and bit definitions Updated SCI Receive Register (SRX) Description Updated Programming sheets for the OMR, BCR, Address Attribute Registers (AAR[3–0]), and Timer Registers (TLR, TCPR, TCR) 2 Modified Signal Definitions Area to Change Change Description Table 2-1, p. 2-1 • For Notes 1–4, delete the last sentence in each note. All internal keepers are disabled and do not affect device operation. • Change Ground (GND) to Ground (GND)5. • Change Note 5 to read as follows: 5. The number of Ground signals listed are for the 144-pin TQFP package. For the 196-ball MAP-BGA package, there are 66 GND connections. Figure 2-1, p. 2-2 • In the figure, change Grounds: to Grounds4: • At the bottom of the figure, add the following: 4. The GND signals are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA package, all grounds except GNDP and GNDP1 are connected together and referenced as GND. There are 64 GND connections. Table 2-3, p. 2-4 • Change the note at the end of the table to the following: Note: The subsystem GND signals (GNDQ, GNDA, GNDD, GNDC, GNDH, and GNDS) are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA package, all grounds except GNDP and GNDP1 are connected together inside the package and referenced as GND. Table 2-8, pp. 2-7 to 2-8 • Change BR signal State During Reset, Stop, or Wait to: Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) • Change BB signal State During Reset, Stop, or Wait to Ignored input For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Operating Mode Register (OMR) Layout and Definition Freescale Semiconductor, Inc... Area to Change 3 Change Description Table 2-11, pp. 2-11 to 2-14 • Change the title of the third column to State During Reset1,2. • Add note 1 that states: Note: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. • Change the old note 1 to note 2. • Change State During Reset for all signals to Ignored input. • Change the signal description for PB14 to: Port B14—When the HI08 is configured as GPIO through the HPCR, this signal is individually programmed through the HDDR. Table 2-12, pp. 2-15 to 2-16 Table 2-13, pp. 2-17 to 2-18 Table 2-14, p. 2-19 Table 2-15, p. 2-20 • Delete the Stop column • Change the title for the third column to State During Reset 1,2 Change State During Reset for all signals to Ignored input. Note: 1. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, these lines are tri-stated. • Change the old note 1 to note 2. Operating Mode Register (OMR) Layout and Definition Area to Change Figure 4-2, p. 4-15 Change Description Replace with the following: Stack Control/Status (SCS) 23 22 21 20 19 18 17 Extended Operating Mode (EOM) 16 15 14 13 12 11 10 9 8 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] Chip Operating Mode (COM) 7 6 MS SD 0 0 5 4 3 2 1 0 EBD MD MC MB MA Reset: 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 * * * * After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA, respectively). Reserved bit. Read as zero; write to zero for future compatibility Figure 4-2. Operating Mode Register (OMR) Area to Change Table 4-3, p. 4-17 Change Description • For bit 7, change the third line in Note 1 to the following: Instruction Cache always uses the highest internal Program RAM 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Bus Control Register (BCR) Layout and Definition 4 Bus Control Register (BCR) Layout and Definition Area to Change Figure 4-6, p. 4-25 Change Description • Replace with the following: Change Figure 4-6 of the DSP56303 User’s Manual to the following figure: 23 22 Freescale Semiconductor, Inc... BRH 21 20 19 18 17 16 15 14 13 12 BBS BDFW4 BDFW3 BDFW2 BDFW1 BDFW0 BA3W2 BA3W1 BA3W0 BA2W2 11 10 9 8 7 6 5 4 3 2 1 0 BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1W0 BA0W4 BA0W3 BA0W2 BA0W1 BA0W0 Reserved bit. Read as zero; write to zero for future compatibility Figure 4-6. Bus Control Register (BCR) Area to Change Table 4-8, p. 4-26 • Change the row contents for bit 22 to the following: 0 22 5 Change Description Reserved. Write to 0 for future compatibility. SCI Receive Register (SRX) Description Area to Change Section 8.6.4.1, p. 8-23 6 Change Description • Change the beginning of the fourth paragraph from “In Synchronous mode” to “In Asynchronous mode”. Updated Programming Sheets In Table B-1, p. B-2 in the DSP56L307 User’s Manual, change the Timers rows to the following: Timers Figure B-20, Timer Prescaler Load Register (TPLR) B-31 Figure B-21, Timer Control/Status Register (TCSR) B-32 Figure B-22, Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) B-33 Use the following examples to replace Figure B-2 (p. B-13), Figure B-6 (p. B-17), Figure B-8 (p. B-19), and Figure B-22 (p. B-33). 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 2 of 2 Central Processor Asynchronous Bus Arbitration Enable, Bit 13 0 = Synchronization disabled 1 = Synchronization enabled External Bus Disable, Bit 4 0 = Enables external bus 1 = Disables external bus Freescale Semiconductor, Inc... Address Attribute Priority Disable, Bit 14 0 = Priority mechanism enabled 1 = Priority mechanism disabled Stop Delay Mode, Bit 6 0 = Delay is 128K clock cycles 1 = Delay is 16 clock cycles Address Trace Enable, Bit 15 0 = Address Trace mode disabled 1 = Address Trace mode enabled Memory Switch Mode, Bit 7 0 = Memory switching disabled 1 = Memory switching enabled Stack Extension X Y Select, Bit 16 0 = Mapped to X memory 1 = Mapped to Y memory Core-DMA Priority, Bits 9–8 CPD[1:0] Description 00 Compare SR[CP] to active DMA channel priority 01 DMA has higher priority than core 10 DMA has same priority as core 11 DMA has lower priority than core Stack Extension Underflow Flag, Bit 17 0 = No stack underflow 1 = Stack underflow Stack Extension Overflow Flag, Bit 18 0 = No stack overflow 1 = Stack overflow Stack Extension Wrap Flag, Bit 19 0 = No stack extension wrap 1 = Stack extension wrap (sticky bit) Stack Extension Enable, Bit 20 0 = Stack extension disabled 1 = Stack extension enabled Chip Operating Mode, Bits 3–0 Refer to the operating modes table in Chapter 4. Bus Release Timing, Bit 12 0 = Fast Bus Release mode 1 = Slow Bus Release mode Cache Burst Mode Enable, Bit 10 0 = Burst Mode disabled 1 = Burst Mode enabled TA Synchronize Select, Bit 11 0 = Not synchronized 1 = Synchronized 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 *0 *0 *0 8 7 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CPD1 CPD0 MS Operating Mode Register Reset = $00030X; X = latched from levels on Mode pins 6 5 SD *0 4 3 2 1 EBD MD MC MB 0 MA * = Reserved, Program as 0 Figure B-2. Operating Mode Register (OMR) 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 1 of 2 Bus Interface Unit Freescale Semiconductor, Inc... NOTE: All BCR bits are read/write control bits. Default Area Wait Control, Bits 20–16 Bus Request Hold, Bit 23 Area 3 Wait Control, Bits 15–13 0 = BR pin is asserted only for attempted or pending access Area 2 Wait Control, Bits 12–10 1 = BR pin is always asserted Area 1 Wait Control, Bits 9–5 Area 0 Wait Control, Bits 4– 0 These read/write control bits define the number of wait states inserted into each external SRAM access to the designated area. The value of these bits should not be programmed as zero. Bits Bit Name # of Wait States Bus State, Bit 21 20–16 BDFW[4–0] 0–31 0 = DSP is not bus master 15–13 BA3W[2–0] 0–7 1 = DSP is bus master 12–10 BA2W[2–0] 0–7 9–5 BA1W[4–0] 0–31 4–0 BA0W[4–0] 0–31 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BRH *0 BBS BDFW[4–0] Bus Control Register (BCR) Reset = $1FFFFF BA3W[2–0] BA2W[2–0] 8 7 6 BA1W[4–0] 5 4 3 2 1 0 BA0W[4–0] X:$FFFFFB Read/Write * = Reserved, Program as 0 Figure B-6. Bus Control Register (BCR) 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Bus Interface Unit Bus Packing Enable, Bit 7 0 = Disable internal packing/unpacking logic 1 = Enable internal packing/unpacking logic Freescale Semiconductor, Inc... Bus Y Data Memory Enable, Bit 5 0 = Disable AA pin and logic during external Y data space accesses 1 = Enable AA pin and logic during external Y data space accesses Bus Address to Compare, Bits 23–12 Bus X Data Memory Enable, Bit 4 0 = Disable AA pin and logic during external X data space accesses 1 = Enable AA pin and logic during external X data space accesses BAC[11–0] = address to compare to the external address in order to decide whether to assert the AA pin Bus Program Memory Enable, Bit 3 0 = Disable AA pin and logic during external program space accesses 1 = Enable AA pin and logic during external program space accesses Bus Number of Address Bits to Compare, Bits 11–8 BNC[3–0] = number of bits (from BAC bits) that are compared to the external address Bus Address Attribute Polarity, Bit 2 0 = AA/RAS signal is active low 1 = AA/RAS signal is active high (Combinations BNC[3–0] = 1111, 1110, 1101 are reserved.) Bus Access Type, Bits 1–0 BAT[1–0] 00 01 10 11 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC Address Attribute Registers 3 (AAR3) Address Attribute Registers 2 (AAR2) Address Attribute Registers 1 (AAR1) Address Attribute Registers 0 (AAR0) Reset = $000000 Encoding Reserved SRAM access DRAM access Reserved 6 *0 5 4 3 2 1 0 BYEN BXEN BPEN BAAP BAT1 BAT0 X:$FFFFF6 Read/Write X:$FFFFF7 Read/Write X:$FFFFF8 Read/Write X:$FFFFF9 Read/Write = Reserved, Program as 0 * Figure B-8. Address Attribute Registers (AAR[3–0]) 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Updated Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Freescale Semiconductor, Inc... Timer Reload Value Timer Load Register (TLR[0–2]) Reset = $xxxxxx, value is indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TLR0—X:$FFFF8E Write Only TLR1—X:$FFFF8A Write Only TLR2—X:$FFFF86 Write Only 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register (TCPR[0–2]) Reset = $xxxxxx, value is indeterminate after reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TCPR0—X:$FFFF8D Read/Write TCPR1—X:$FFFF89 Read/Write TCPR2—X:$FFFF85 Read/Write 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register (TCR[0–2]) Reset = $000000 TCR0—X:$FFFF8C Read Only TCR1—X:$FFFF88 Read Only TCR2—X:$FFFF84 Read Only Figure B-22. Timer Load, Compare, and Count Registers (TLR, TCPR, TCR) 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 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