EMC EM62100AGH

EM62100
Product
Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
September 2005
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes
no commitment to update, or to keep current the information and material contained in this specification. Such
information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other
inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for
direct, indirect, special incidental, or consequential damages arising from the use of such information or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be
used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN
Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY
MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, Taiwan, 30077
Tel: +886 3 563-9977
Fax: +886 3 563-9966
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information Technology
Group
Rm. 1005B, 10/F Empire Centre
68 Mody Road, Tsimshatsui
Kowloon , HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
[email protected]
1821 Saratoga Ave., Suite 250
Saratoga, CA 95070
USA
Tel: +1 408 366-8223
Fax: +1 408 366-8220
Europe:
Shenzhen:
Shanghai:
Elan Microelectronics Corp.
(Europe)
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai Corporation, Ltd.
Siewerdtstrasse 105
8050 Zurich, SWITZERLAND
Tel: +41 43 299-4060
Fax: +41 43 299-4079
http://www.elan-europe.com
SSMEC Bldg., 3F, Gaoxin S. Ave.
Shenzhen Hi-Tech Industrial Park
Shenzhen, Guandong, CHINA
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
23/Bldg. #115 Lane 572, Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA
Tel: +86 021 5080-3866
Fax: +86 021 5080-4600
Contents
1
2
3
4
5
6
General Description ..........................................................................................................1
Features.............................................................................................................................1
Pin Configuration ..............................................................................................................2
3.1
3.2
PIN DIMENSIONS......................................................................................................3
MARK DIMENSIONS .................................................................................................3
3.3
Alignment Key ............................................................................................................3
3.4 Pin Coordinate Table ..................................................................................................4
Pin Description..................................................................................................................7
Block Diagram.................................................................................................................10
Function Description ...................................................................................................... 11
6.1
MPU Interface .......................................................................................................... 11
6.1.1
6.1.2
6.1.3
6.1.4
Selecting the Interface Type ........................................................................................ 11
Parallel Interface.......................................................................................................... 11
Serial Interface ............................................................................................................ 12
Chip Select .................................................................................................................. 12
6.2
Access to Display Data RAM and Internal Registers ................................................13
6.3
6.4
Busy Flag .................................................................................................................14
Display Data RAM ....................................................................................................14
6.5
Page Address Circuit ................................................................................................14
6.6
Line Address Circuit..................................................................................................15
6.7
6.8
Column Addresses Circuit ........................................................................................15
Display Data Latch Circuit ........................................................................................17
6.9
Oscillator Circuit .......................................................................................................17
6.10 Display Timing Generator Circuit ..............................................................................17
6.11 Common Control (Shift Register)..............................................................................19
6.11.1 Common Number ........................................................................................................ 19
6.11.2 LCD Driver Circuits ...................................................................................................... 19
6.11.3 Configuration Setting ................................................................................................... 20
6.12 Power Supply Module...............................................................................................20
6.12.1
6.12.2
6.12.3
6.12.4
6.12.5
Step-up Voltage Circuit ................................................................................................ 21
Voltage Regulator Circuit............................................................................................. 21
Liquid Crystal Voltage Generator Circuit ..................................................................... 23
High Power Mode ........................................................................................................ 24
Reference Power Supply Circuit For Driving LCD Panel ............................................ 24
6.13 Reset Circuit.............................................................................................................25
6.13.1 Initial Value of Command Register .............................................................................. 25
7
Command Register & Decoder.......................................................................................26
7.1
7.2
Command Table .......................................................................................................27
Command Function ..................................................................................................29
Product Specification (V1.1) 09.13.2005
• iii
Contents
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.2.24
7.2.25
7.2.26
7.2.27
7.2.28
7.2.29
7.3
Chip Initial State and Power ON/OFF Flowchart : .....................................................43
7.3.1
8
9
10
Display ON/OFF .......................................................................................................... 29
Display Start Line Set .................................................................................................. 29
Page Address Set........................................................................................................ 30
Column Address Set.................................................................................................... 30
Read Status ................................................................................................................. 31
Write Display Data ....................................................................................................... 31
Read Display Data....................................................................................................... 32
ADC Select .................................................................................................................. 32
Normal/Reverse Display.............................................................................................. 32
Entire Display ON ........................................................................................................ 32
LCD Bias Set ............................................................................................................... 33
Read-Modify-Write....................................................................................................... 33
End .............................................................................................................................. 34
Reset ........................................................................................................................... 34
Output Status Select Register ..................................................................................... 34
Power Control Set ....................................................................................................... 35
V0 Voltage Regulator Internal Resistor Ratio Set ....................................................... 35
Electronic Volume (Double Byte Command) ............................................................... 35
Static Indicator (Double Byte Command) .................................................................... 36
Power Save (Compound Command) .......................................................................... 37
NOP ............................................................................................................................. 37
Test Command ............................................................................................................ 39
Oscillation Frequency Select....................................................................................... 39
Partial Display Mode Set ............................................................................................. 39
Partial Display Duty and Bias Set................................................................................ 39
Partial Start Line Set (Double Byte Command) ........................................................... 40
N-line Inversion (Double byte command) .................................................................... 41
Release N-line Inversion ............................................................................................. 42
DC/DC Clock Frequency (Double Byte Command) .................................................... 42
Initialization .................................................................................................................. 43
Absolute Maximum Ratings ...........................................................................................46
DC Characteristics ..........................................................................................................46
Timing Diagram ...............................................................................................................49
10.1 System Bus Read/Write Characteristics (8080-Series Microprocessor)....................49
10.2 System Bus Read/Write Characteristics (6800-Series Microprocessor)....................50
10.3 Serial Interface Characteristics.................................................................................51
10.4 Reset Timing ............................................................................................................52
10.5 Display Control Timing..............................................................................................52
10.6 Application Circuit.....................................................................................................53
10.6.1 8080-Series MPU ........................................................................................................ 53
10.6.2 6800-Series MPU ........................................................................................................ 54
10.6.3 Using the Serial Interface ............................................................................................ 54
iv •
Product Specification (V1.1) 09.13.2005
Contents
Specification Revision History
Doc. Version
0.1
0.2
Revision Description
Preliminary version
1.
2.
3.
4.
1.
2.
3.
4.
5.
6.
7.
8.
0.3
9.
10.
11.
12.
13.
14.
15.
16.
1.
2.
3.
1.0
4.
5.
Modified the interface type selection table (table2)
Modified the parallel interface table (table3)
Pins renamed: VDD2 VCI, RW R/WB, C86 M86,
P_S P/S, CLS CKS, CL CK, FR M, FRS FLM
Added Pin coordinate table in Pin configuration on
page 4 ~ 7
Modified the Pin Coordinate Table (pin 71 ~ pin 78 X
coordinate) on page 4
Added Alignment Key (A1, A2) to Pin Configuration
table on page 3
Deleted Part No. EM62100AU, EM62100BU from the
Package table on page 3
Modified VDD, VDD2, VSS, VSS2,VSS3 function in
Pin Description on page 7
Pins renamed: D0 to D7 D0, D1, D2, D3, D4, D5, D6
(SCL), D7 (SI), R/WB RW, on page 8, VCI
VEE
and modified the VEE pin function description on page
10
Deleted 6.12.4 voltage follower down control
Modified 6.13.1 item mark and Added 6.13 description
on page 25
Added section 7. Command Register & Decoder
description on page 26
Modified the Command Function Table E RDB
RDB , R/W WRB WRB
Modified section 7.2.5 Read status table: RDB=1,
WRB=0
RDB=0 , WRB=1 on page 31
Modified section 7.2.16 Power Control Set table: A2,
A1, A0
VB, VR, VF on page 35
Modified section 9 DC Characteristics: Hz
Hi-z on
page 38 , VOUT`1 ~VOUT4 MAX RATING
5XVDD2X0.99 ~ 2XVDD2X0.99
5XVDD2 ~
2XVDD2
Added No. of pins in Pin Description table on pages
7 ~ 10
Added Pin Configuration on page 2
Added sections 3.1 Pin Dimensions , 3.2 Mark
Dimensions, 3.3 Alignment Key on page 3
Modified Pin Description: swapped Pin names CAP1
; CAP2
Added Timing rating to AC Characteristics table on
page 49~52.
Added be take notice of item in serial mode on page 51
Added fFRM rating and Base Voltage rating to AC
Characteristics table on page 47~48.
Modified VREF pin input only and the function in Pin
Description on page 7
Added Current consumption to DC Characteristics
table on page 47
Product Specification (V1.1) 09.13.2005
Date
2005/05/05
2005/05/10
2005/06/15
2005/8/16
•v
Contents
1.1
vi •
1.
Modified ISB MAX. rating =10 uA
2005/09/13
Product Specification (V1.1) 09.13.2005
EM62100
65 COM/132 SEG STN LCD Driver
1
General Description
The EM62100 is a 65 Common 132 Segment dot matrix liquid crystal display (LCD)
driver LSI. It can be connected directly to a microprocessor bus, and selected as an
8-bit parallel or serial data input interface. The EM62100 IC device contains 65x132
bits of display data RAM and there is a one-to-one correspondence between the LCD
panel pixels and the internal RAM bits.
The EM62100 chip can drive a 65x132 dot display, so that a single chip of EM62100
can drive a maximum of 65x132 or 55x132 or 49x132 or 33x132 dots display with the
pad option (DUTY1, DUTY0). Moreover, the capacity of the display can be extended
by master/slave structures between chips. The chips can minimize power consumption
since no external operating clock is necessary for the RAM read/write operation.
Furthermore, each chip has a built-in low-power LCD driver power supply, on-chip
resistors for LCD driver power voltage adjustment and a built-in display clock CR
oscillator circuit, hence, the EM62100 chip can be used to create the lowest power
display system with the fewest components for high-performance portable devices.
2
Features
Direct display of RAM data through the display data RAM. RAM bit data:
“0”: non-illuminated “1”: illuminated (at normal display)
RAM capacity of 65*132 = 8,580 bits
Display driver circuits: 65 common output and 132 segment outputs
High-speed 8-bit MPU interface (80-series and 68-series) / Serial interfaces are
supported.
Multiple command functions: display data Read/Write, display ON/OFF, status
read, Normal/Reverse display mode, page address set, display start line set,
column address set, entire display ON/OFF, LCD bias set, electronic volume,
read-modify-write, segment driver direction select, power saving, static indicator,
common output status select, V0 voltage regulation internal resistor ratio set.
Other command functions: Partial display, partial start line set, N-Line inversion.
Built-in Static drive circuit for indicators
Built-in low-power LCD power supply circuit: Booster circuit (with Boost ratios of
two/three/four/five times, where the step-up voltage reference power supply can
be input externally), High-accuracy voltage adjustment circuit (external input),
built-in V0 voltage regulator resistors, built-in V1 to V4 voltage divider resistors,
built-in electronic volume function, and voltage follower.
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
•1
EM62100
65 COM/132 SEG STN LCD Driver
Internal RC oscillator circuit (external clock can also be input)
Extremely low power consumption
Power supply, operable on the low 1.8 voltage,
Logic power supply VDD – VSS = 1.8 to 3.6V,
Boost reference voltage: VEE= 1.8 to 3.6V,
LCD driver power supply: VLCD=V0 – VSS =4.0 to 14.2 V
These chips are not designed with resistance to light or resistance to radiation.
Package (Ordering information)
3
Part No.
Package Type
EM62100AGH
Gold Bump
Pin Configuration
312
296
1
295
Left Mark
62
63
78
79
Right Mark
122
140
123
2•
139
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
3.1 PIN DIMENSIONS
Item
Size
Pad No.
Chip size
1 ~ 62 , 79~122 ,
140 ~ 295
123 ~ 139 , 296 ~
312
63 ~78
Bump Size
Pad Pitch
Die thickness
(excluding bumps)
X
Y
8200
1000
35
80
80
35
50
58
50 (min.)
Unit
m
20 ±1 mil ( 525 ± 25 m)
Bump Height
17 ± 2
Minimum Bump Gap
Coordinate Origin
15
Chip center
3.2 MARK DIMENSIONS
Mark
Coordinate (X, Y)
Left
Right
-3763.05 ,125.15
3748.5 ,125.1
3.3 Alignment Key
40
40 20 40
100 um
20
100 um
40
100 um
100 um
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
•3
EM62100
65 COM/132 SEG STN LCD Driver
3.4 Pin Coordinate Table
4•
Pad No.
Pad Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC1
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
NC2
FLM
M
CK
DOFB
VSS
CS1B
CS2
VDD
RESB
RS
WRB (RW)
TEST1
RDB (E)
VDD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
DUTY0
VSS
DUTY1
VDD
VDD
VDD
VDD
VEE
Coordinate
X
Y
-3877.5
-3827.5
-3777.5
-3727.5
-3677.5
-3627.5
-3577.5
-3527.5
-3477.5
-3408.8
-3358.8
-3308.8
-325838
-3208.8
-3158.8
-3108.8
-3058.8
-3008.8
-2958.8
-2908.8
-2858.8
-2808.8
-2758.8
-2708.8
-2658.8
-2608.8
-2558.8
-2508.8
-2458.8
-2408.8
-2358.8
-2308.8
-2258.8
-2208.8
-2158.8
-2108.8
-2058.8
-2008.8
-1958.8
-1908.8
-1858.8
-1808.8
-1758.8
-1708.8
-1658.8
-1608.8
-1558.8
-1508.8
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
Pad No.
Pad Name
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
VEE
VEE
VEE
VEE
VEE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TEST2
VOUT
VOUT
VOUT
CAP4+
CAP4+
CAP3+
CAP3+
CAP1CAP1CAP1+
CAP1+
CAP2+
CAP2+
CAP2+
CAP2CAP2V1
V1
V1
V1
V2
V2
V2
V2
V3
V3
V3
V3
V4
V4
V4
V4
V0
V0
Coordinate
X
Y
-1458.8
-1408.8
-1358.8
-1308.8
-1258.8
-1208.8
-1158.8
-1108.8
-1058.8
-1008.8
-958.8
-908.8
-858.8
-808.8
-733.65
-506.65
-441.65
-376.65
-116.65
-51.65
198.35
263.35
523.4
588.4
845.4
910.4
1105.4
1170.4
1235.4
1495.4
1610.1
1660.1
1710.1
1760.1
1810.1
1860.1
1910.1
1960.1
2010.1
2060.1
2110.1
2160.1
2210.1
2260.1
2310.1
2360.1
2410.1
2460.1
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-399.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
Pad No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pad Name
V0
V0
V0
VREF
TEST3
VDD
M/S
CKS
VSS
M86
P/S
VDD
HPMB
VSS
IRS
VDD
NC3
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
NC4
NC5
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
NC6
NC7
COM8
COM7
COM6
COM5
Coordinate
X
Y
2510.1
2560.1
2610.1
2758.8
2808.8
2858.8
2908.8
2958.8
3008.8
3058.8
3108.8
3158.8
3208.8
3258.8
3308.8
3358.8
3408.8
3477.5
3527.5
3577.5
3627.5
3677.5
3727.5
3777.5
3827.5
3877.5
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3988.0
3875
3825
3775
3725
3675
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-388.0
-400.0
-350.0
-300.0
-250.0
-200.0
-150.0
-100.0
-50.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
388.0
388.0
388.0
388.0
388.0
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
Pad No.
Pad Name
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
COM4
COM3
COM2
COM1
COM0
COMS
NC8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
Coordinate
X
Y
3625.0
3575.0
3525.0
3475.0
3425.0
3375.0
3325.0
3275.0
3225.0
3175.0
3125.0
3075.0
3025.0
2975.0
2925.0
2875.0
2825.0
2775.0
2725.0
2675.0
2625.0
2575.0
2525.0
2475.0
2425.0
2375.0
2325.0
2275.0
2225.0
2175.0
2125.0
2075.0
2025.0
1975.0
1925.0
1875.0
1825.0
1775.0
1725.0
1675.0
1625.0
1575.0
1525.0
1475.0
1425.0
1375.0
1325.0
1275.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
•5
EM62100
65 COM/132 SEG STN LCD Driver
6•
Pad No.
Pad Name
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
Coordinate
X
Y
1225.0
1175.0
1125.0
1075.0
1025.0
975.0
925.0
875.0
825.0
775.0
725.0
675.0
625.0
575.0
525.0
475.0
425.0
375.0
325.0
275.0
225.0
175.0
125.0
75.0
25.0
-25.0
-75.0
-125.0
-175.0
-225.0
-275.0
-325.0
-375.0
-425.0
-475.0
-525.0
-575.0
-625.0
-675.0
-725.0
-775.0
-825.0
-875.0
-925.0
-975.0
-1025.0
-1075.0
-1125.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
Pad No.
Pad Name
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
NC9
COM32
COM33
COM34
COM35
Coordinate
X
Y
-1175.0
-1225.0
-1275.0
-1325.0
-1375.0
-1425.0
-1475.0
-1525.0
-1575.0
-1625.0
-1675.0
-1725.0
-1775.0
-1825.0
-1875.0
-1925.0
-1975.0
-2025.0
-2075.0
-2125.0
-2175.0
-2225.0
-2275.0
-2325.0
-2375.0
-2425.0
-2475.0
-2525.0
-2575.0
-2625.0
-2675.0
-2725.0
-2775.0
-2825.0
-2875.0
-2925.0
-2975.0
-3025.0
-3075.0
-3125.0
-3175.0
-3225.0
-3275.0
-3325.0
-3375.0
-3425.0
-3475.0
-3525.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
4
Pad No.
Pad Name
289
290
291
292
293
294
295
296
297
298
299
300
COM36
COM37
COM38
COM39
COM40
COM41
NC10
NC11
COM42
COM43
COM44
COM45
Coordinate
X
Y
-3575.0
-3625.0
-3675.0
-3725.0
-3775.0
-3825.0
-3875.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
388.0
388.0
388.0
388.0
388.0
388.0
388.0
400.0
350.0
300.0
250.0
200.0
Pad No.
Pad Name
301
302
303
304
305
306
307
308
309
310
311
312
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
NC12
Coordinate
X
Y
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
-3988.0
150.0
100.0
50.0
0.0
-50.0
-100.0
-150.0
-200.0
-250.0
-300.0
-350.0
-400.0
Pin Description
Table 1
Pin Name
I/O
VDD
VSS
Power Supply
Power Supply
VEE
Power Supply
V0
V1
V2
Power Supply
V3
V4
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP4+
O
O
O
O
O
O
VOUT
I/O
VREF
I
Function
Power supply terminal VCC
System Ground
Voltage supply pin for booster circuit. Usually the same voltage
level as VDD.
Multi-level power supply for the liquid crystal drive. The voltage
applied is determined by the liquid crystal cell, and is changed
through the use of a resistive voltage divider or by changing the
impedance using an Op. Amp. Voltage levels are determined
based on V0, and must maintain the relative magnitudes shown
below.
V0 V1 V2 V3 V4 VSS
Master operation: When the power supply is turned ON, the
internal power supply circuits produce the V1 to V4 voltages
shown below. The voltage settings are selected using the LCD
bias set command.
LCD bias V1
V2
V3
V4
1/4 bias 3/4V0 2/4V0 2/4V0 1/4V0
1/5 bias 4/5V0 3/5V0 2/5V0 1/5V0
1/6 bias 5/6V0 4/6V0 2/6V0 1/6V0
1/7 bias 6/7V0 5/7V0 2/7V0 1/7V0
1/8 bias 7/8V0 6/8V0 2/8V0 1/8V0
1/9 bias 8/9V0 7/9V0 2/9V0 1/9V0
Capacitor 1 positive pin for voltage converter
Capacitor 1 negative pin for voltage converter
Capacitor 2 positive pin for voltage converter
Capacitor 2 negative pin for voltage converter
Capacitor 3 positive pin for voltage converter
Capacitor 4 positive pin for voltage converter
DC/DC voltage converter input/output pin, connect a capacitor
between this terminal and VSS
V0 voltage adjustment pad. Applies voltage between V0 and VSS
using a resistive divider. This is only enabled (IRS=“L”) When the
V0 voltage regulator internal resistor is not used. When the V0
voltage regulator internal resistor is used (IRS=“H”), this pin must
be floating.
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
No. of Pins
8
12
6
21
2
2
2
3
2
2
3
1
•7
EM62100
65 COM/132 SEG STN LCD Driver
Pin Name
DUTY0
DUTY1
D0, D1,
D2, D3,
D4, D5,
D6 (SCL),
D7 (SI)
I/O
I
I/O
RS
I
RESB
I
CS1B
CS2
I
RDB (E)
I
WRB (RW)
I
M86
I
Function
Select the maximum LCD driver duty
DUTY
DUTY1
LCD Driver Duty
0
0
0
1/33
0
1
1/49
1
0
1/55
1
1
1/65
8-bit bi-directional data bus connected to an 8-bit or 16-bit
standard MPU data bus. When the chip select is inactive, D0 to
D7 are set to high impedance.
When serial interface is selected (P/S = “L”), then D7 serves as
the serial data input terminal (SI) and D6 serves as the serial
clock input terminal (SCL). During this time, D0 to D5 are set to
high impedance.
Determines whether the data bits are data or instruction
(command).
RS
D0 to D7
H
Display data
L
Instruction (Command)
When RESB is set to “L,” the settings are initialized.
Chip select signal. When CS1B = “L” and CS2 = “H,” then the
chip select CS2 becomes active, and data/command I/O is
enabled.
Enable clock signal input for the 68-series MPU, active high.
Active low input pin for the 80-series MPU RDB signal
Read/Write control signal with 68-series MPU
RW=”H”: Read, RW=”L”: Write
Active low input pin for the 80 series MPU WRB signal
MPU interface switch terminal
M86 =”H”: 68-series MPU interface
M86 =”L”: 80-series MPU interface
Selects the Parallel or Serial data input interface
P/S = “H”: Parallel data input interface, P/S = “L”: Serial data input
interface
The following applies depending on the P/S status:
P/S
P/S
CKS
8•
I
I
No. of Pins
Data/Command
Data
H
RS
D0 to D7
L
RS
D7 (SI)
Read/Write
RDB (E),
WRB (RW)
Write only
2
16
1
19
2
1
1
1
Serial Clock
1
D6 (SCL)
When P/S = “L”, D0 to D5 are hi-Z. D0 to D5 can be “H” or “L”
RDB (E) and WRB (RW) are fixed to either “H” or “L”. With serial
data input, RAM display data reading is not supported.
Terminal to select whether enable or disable the display clock
internal oscillator circuit.
CKS = “H”: Internal oscillator circuit is enabled
CKS = “L”: Internal oscillator circuit is disabled
(requires an external input)
When CKS = “L”, input the display clock through the CK terminal.
1
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
Pin Name
I/O
Function
No. of Pins
M/S = “H”: Master operation
M/S = “L”: Slave operation
The following is true depending on the M/S and CKS status:
M/S
M/S
I
H
L
CKS
Oscillator
Circuit
PowerSupply
Circuit
CK
M
FLM
DOFB
H
L
-
Enable
Disable
Disable
Enable
Enable
Disable
O
I
I
O
O
I
O
O
O
O
O
I
1
O: Output, I: Input
CK
I/O
M
I/O
DOFB
I/O
FLM
O
IRS
I
HPMB
I
Display clock input terminal
When the EM62100 chips are used in master/slave mode, the
various CK terminals must be connected.
Liquid crystal alternating current signal I/O terminal.
M/S = “H”: Output, M/S = “L”: Input
When the EM62100 Series chip is used in master/slave mode, the
various M terminals must be connected.
LCD blanking control terminal
M/S = “H”: Output, M/S = “L”: Input
When the EM62100 chip is used in master/slave mode, the
various DOFB terminals must be connected.
Output terminal for the static drive
This terminal is only enabled when the static indicator display is
ON during master mode operation, and is used in connection with
the M terminal.
This terminal selects the resistors for the V0 voltage level
adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V0 voltage level
is regulated by an external resistive voltage divider attached to
the VREF terminal.
This pin is enabled only when master mode operation is selected.
It is fixed to either “H” or “L” when slave mode operation is
selected.
Power control terminal for the power supply circuit for liquid
crystal drive.
HPMB = “H”: Normal mode, HPMB = “L”: High power mode
This pin is enabled only when master mode operation is selected.
It is fixed to either “H” or “L” when slave mode operation is
selected.
Liquid crystal segment drive outputs. Through a combination of
the contents of the display RAM and with the M signal, a single
level is selected from V0, V2, V3, and VSS.
RAM DATA
SEG0
To
SEG131
O
H
H
L
L
Power Save & Display OFF
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
M
Output Voltage
H
L
H
L
--
Normal Display Reverse Display
V0
V2
VSS
V3
V2
V0
V3
VSS
VSS
1
1
1
1
1
1
132
•9
EM62100
65 COM/132 SEG STN LCD Driver
Pin Name
I/O
Function
No. of Pins
LCD common drive outputs.
Through a combination of the contents of the scan data and with
the M signal, a single level is selected from V0, V1, V4, and VSS.
COM0
To
COM63
5
O
Scan Data
M
Output Voltage
H
H
L
L
Power Save
H
L
H
L
--
VSS
V0
V1
V4
VSS
64
COMS
O
Common output terminals for the indicator. Both terminals output
the same signal. Leave these open if they are not used.
When in master/slave mode, the same signal is output by both
master and slave.
TEST1~3
I/O
For IC chip testing. Must be floating.
2
3
Block Diagram
Segment Driver
Shift Register
Data Latch
COMS
Common Driver
COMS
---------
SEG131
SEG130
SEG129
SEG2
SEG0
SEG1
COM63
COM0
----
VDD
V0
V1
V2
V3
V4
VSS
Display Line Register
Column Address Decoder
Display Timing
Generator
Circuit
Column Address Register
Input/Output Buffer
Bus Holder
Display Line Counter
Display RAM
132 X 65 dots
Line Address Decoder
I/0 buffer circuit
Page
Address
Register
IRS
HPMB
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
VoltageConverter
VOUT
VEE
VREF
Booster Circuit
CAP1CAP1+
CAP2CAP2+
CAP3+
CAP4+
Bus Holder
DUTY0
DUTY1
FLM
M
CK
DOFB
CKS
Instruction Decoder
MPU Interface
OSC
CS1B CS2 RS RDB WRB P/S M86 RESB
(E) (RW)
CKS
Fig. 1 System Block Diagram
10 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
6
Function Description
6.1 MPU Interface
6.1.1 Selecting the Interface Type
The EM62100 chip has three types of interface with an MPU, which are two parallel
interfaces and serial interface. The interface is determined by the P/S terminal polarity
to the “H” or “L”, as shown in Table 2.
Table 2
P/S
CS1B
CS2
RS
RDB
WRB
M86
D7
D6
D5~D0
H: Parallel Input
CS1B
CS2
RS
RDB
WRB
M86
D7
D6
D5~D0
L: Serial Input
CS1B
CS2
RS
--
--
--
SI
SCL
(Hi-Z)
“--“Indicates fixed to either “H” or to “L”
6.1.2 Parallel Interface
When the parallel interface has been selected (P/S=”H”), then it is possible to connect
directly to either an 8080-series MPU or a 6800-series MPU by selecting the M86
terminal to either “H” or to “L”.
Table 3
M86
CS1B
CS2
RS
RDB
WRB
D7~D0
L: 80-series MPU
CS1B
CS2
RS
RDB
WRB
D7~D0
H: 68-series MPU
CS1B
CS2
RS
E
RW
D7~D0
The type of data transfer is determined by signals at RS, RDB (E), WRB (RW) as
shown in Table 4.
Table 4
RS
68-Series
80-Series
Function
RW
RDB
WRB
1
1
0
1
Reads display data
1
0
1
0
Writes display data
0
1
0
1
Read status
0
0
1
0
Write control data (command)
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 11
EM62100
65 COM/132 SEG STN LCD Driver
6.1.3 Serial Interface
When the EM62100 is active (CS1B=”L” and CS2=”H”), the serial data input (SI) and
the serial clock input (SCL) can be received. The serial data can be read from the SI
pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is
converted to 8 bits parallel data in the rising edge of the 8th serial clock for processing.
The RS input is used to determine whether the serial data input is display data
(RS=”H”) or command data (RS=”L”). The RS input is read and used for detection
every 8th rising edge of the serial clock after the chip becomes active. Figure 2 is a
serial interface signal chart.
CS1B = "L" and CS2 = "H"
CS
SI
D7
D6
D5
D4
D3
D2
D1
D0
D6
1
2
3
4
5
6
7
8
9
D6
D5
D4
SCL
10
11
12
RS
Fig. 2
NOTE
1. When the chip is not active, the shift registers and counter are reset to their initial
states.
2. Reading is not possible while in serial interface mode.
3. Caution is required on the SCL signal when it comes to line-end reflections and
external noise. It is recommended that operation be rechecked on the actual
equipment.
6.1.4 Chip Select
The EM62100 has two chip select terminals: CS1B and CS2. The MPU interface or the
serial interface is enabled only when CS1B=”L” and CS2=”H”. When the chip select is
non-active D0 to D7 enter high impedance and the RS, RDB, and WRB inputs are
inactive. When the serial interface is selected, the shift register and the counter are
reset.
12 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
6.2 Access to Display Data RAM and Internal Registers
To match operation frequencies between the MPU and display RAM or internal
register, the EM62100 performs an LSI-LSI pipelining via the bus holder attached to the
internal data bus.
When the MPU writes data to the display RAM, once the data is stored in the bus
holder, then it is written to the display RAM before the next data write cycle. Moreover,
when the MPU reads the display RAM, the first data read cycle (dummy) stores the
read data in the bus holder, and then the data is read from the bus holder to the system
bus at the next data read cycle.
There is a certain restriction in the read sequence of the display RAM. It should be
noted that data of the specified address is not generated by the read instruction issued
immediately after the address setup. This data is generated during the second time
data read. Thus, a dummy read is required whenever the address setup or the write
cycle operation is performed. This relationship is shown in Figure 3.
RS
MPU
E
RW
DATA
N
N
N
N
Address
Preset
Read
Internal Signal
Timing
Preset
Column
Address
Incremented
N+1
N
BUS Holder
N
Set Address n
N
Dummy Read
N+2
N+1
N+2
Data read address n Data read address n+1
Fig. 3
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 13
EM62100
65 COM/132 SEG STN LCD Driver
6.3 Busy Flag
The busy flag is output to pin D7 by a read status command. When the busy flag is “1”
it indicates that the EM62100 chip is executing its internal operations, any command
other than status read is ignored during this time. If the cycle time (tCYC) is correct, this
flag need not be checked before each instruction. This makes vast improvements in
MPU processing capabilities possible.
6.4 Display Data RAM
The display data RAM stores the pixel data for the LCD. It is a 65×132 addressable
array. It allows access to the desired bit by specifying the page address and the
th
column address. The 65 rows are divided into 8 pages of 8 lines and the 9 page with
a single line (D0). The D7 to D0 display data from the MPU corresponds to the LCD
common lines as show in Fig.4. There are few constraints at the time of display data
transfer when multiple EM62100 chip is used. However, the display structures can be
created easily and with a high degree of freedom. Reading from and writing to the
display RAM from the MPU side is performed through the I/O buffer, which is an
independent operation from signal reading for the liquid crystal driver. Consequently,
even if the display data RAM is accessed asynchronously, it will not cause adverse
effects on the display (such as flickering).
D0
D1
D2
D3
D4
1
0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
COM0
COM1
COM2
COM3
COM4
Display Data RAM
Liquid Crystal Display
Fig. 4
6.5 Page Address Circuit
The page address of the display data RAM is specified through the Page Address Set
Command. The page address needs to be specified again in accessing other pages.
Page address 8 is the page for the RAM region used only by the static indicators, and
only display data D0 is used.
14 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
6.6 Line Address Circuit
The line address circuit assigns the line address corresponding to the common output
when the contents of the display data RAM are displayed. Using the display start line
address set command, the normal top line of the display can be specified (which is the
COM0 output when the common output mode is normal, and the COM63 output for
EM62100 when the common output mode is reversed. The display area is a 65-line
area for the EM62100 from the display start line address.
If the line address is changed dynamically using the display start line address set
command, screen scrolling, page swapping, etc., can be performed.
6.7 Column Addresses Circuit
The column address is specified by the Column Address Set command, as shown in
Fig.5. The specified column address is incremented by 1 each time a read or write
display data instruction is executed. This allows the MPU display data to be accessed
continuously. The column address can no longer be incremented at 83H. Since the
column address is independent of the page address, when moving, for example, from
page 0 column 83H to page 1 column 00H, it is necessary to specify both the page
address and the column address.
Furthermore, as shown in Table 4, the ADC command can be used to invert the
relationship between the display data RAM column address and the segment output.
Because of this, the constraints on the IC layout when the LCD module is assembled
can be minimized.
Table 5
SEG Output
ADC"0"
ADC"1"
SEG0
0(H)
83(H)
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
SEG131
Column address
Column address
83(H)
0(H)
• 15
EM62100
65 COM/132 SEG STN LCD Driver
Page address Data
D3, D2, D1, D0
0, 0, 0, 0
0, 0, 0, 1
0, 0, 1, 0
0, 0, 1, 1
0, 1, 0, 0
0, 1, 0, 1
0, 1, 1, 0
0, 1, 1, 1
1, 0, 0, 0
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
ADC=0 0001020304050607
ADC=1 838281807F7E7D7C
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
LCD Output
7F80 81 82 83
04 03 02 01 00
SEG131
SEG130
SEG129
SEG128
SEG127
Column
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Line address
com output
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
When the inti. display
line address is 1CH
Fig. 5 Display Data RAM
16 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
6.8 Display Data Latch Circuit
The display data latch circuit temporarily stores the display data that is output to the
LCD from the display data RAM. The commands such as display normal/reverse
status, display ON/OFF status, and entire display ON/OFF, control only the data within
the latch, but do not change the data within the display data RAM itself.
6.9 Oscillator Circuit
This is an RC type oscillator that generates the display clock. The oscillator circuit is
only enabled when M/S=”H” and CKS=”H”. When CKS=”L” the oscillation stops, and
the display clock is input through the CK terminal.
6.10 Display Timing Generator Circuit
This circuit generates some signals used for displaying the LCD. The display clock, CK
generated by an oscillation clock, generates a clock to the line counter and a latch
signal to the display data latch. The line address of the on-chip RAM is generated in
synchronization with the display clock (CK) and the display data latch circuit in
synchronization, latches the 132-bit display data with the display clock. The display
data, which is read to the LCD driver, is completely independent of the access to the
display data RAM from the microprocessor.
Moreover, the display timing generator circuit generates the common timing and the
liquid crystal alternating current signal (M) from the display clock. It generates a drive
waveform using a 2-frame alternating current drive method, as shown in Figure 6, for
the liquid crystal drive circuit.
64
65
1
2
3
4
5
61
62
63
64
65
1
2
3
4
5
CK
M
COM0
V0
V1
V2
V3
V4
VSS
COM1
V0
V1
V2
V3
V4
VSS
RAM
data
V0
V1
V2
V3
V4
VSS
SEGn
Figure 6
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 17
EM62100
65 COM/132 SEG STN LCD Driver
When several EM62100 chips are used, the slave chips must supply the display timing
signals (M, CK, DOFB) from the master chip. Explanation is shown in Table 6.
Table 6
Operating Mode
The internal oscillator circuit is enabled (CKS=”H”)
Master (M/S= “H”)
The internal oscillator circuit is disabled (CKS=”L”)
The internal oscillator circuit is enabled (CKS=”H”)
Slave (M/S = “L”)
The internal oscillator circuit is disabled (CKS=”L”)
M
O
O
I
I
CK
O
I
I
I
DOFB
O
O
I
I
O: Output, I: Input
NOTE
When the EM62100 is used in the master/slave configuration, each of the CKS pins
are set to the same level together.
Table 7 shows the relationship between the oscillation frequency and frame frequency.
fOSC which can be selected as 31.4 or 26.3kHz by using Oscillation Frequency Select
command.
Table 7
Duty
1/65
1/55
1/49
1/33
1/17
1/9
18 •
Item
fCK
On-chip oscillator is used
On-chip oscillator is not used
On-chip oscillator is used
On-chip oscillator is not used
On-chip oscillator is used
On-chip oscillator is not used
On-chip oscillator is used
On-chip oscillator is not used
On-chip oscillator is used
On-chip oscillator is not used
On-chip oscillator is used
On-chip oscillator is not used
fOSC/6
External input fCL
fOSC/7
External input fCL
fOSC/8
External input fCL
fOSC/12
External input fCL
fOSC/22
External input fCL
fOSC/44
External input fCL
fM
fCK / (2 x 65)
fCK / (2 x 65)
fCK / (2 x 55)
fCK / (2 x 55)
fCK / (2 x 49)
fCK / (2 x 49)
fCK / (2 x 33)
fCK / (2 x 33)
fCK / (2 x 17)
fCK / (2 x 17)
fCK / (2 x 9)
fCK / (2 x 9)
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
6.11 Common Control (Shift Register)
6.11.1 Common Number
This circuit controls the relationship between the number of common output and
specified duty ratio. Common output mode select instruction specifies the scanning
direction of the common output pads, as shown in Table 8.
Table 8
Common Output Pads
Duty
1/33
1/49
1/55
1/65
Status
COM
[0:15]
COM
COM
COM
COM
COM
[16:23] [24:26] [27:36] [37:39] [40:47]
Normal
COM[0:15]
NC
Reverse
COM[31:16]
NC
Normal
COM[0:23]
NC
Reverse
COM[47:24]
NC
COM
[48:63]
COMS
COM[16:31] COMS
COM[15:0] COMS
COM[24:47]
COMS
COM[23:0]
Normal
COM[0:26]
NC
COM[27:53]
COMS
COMS
Reverse
COM[53:27]
NC
COM[26:0]
COMS
Normal
COM[0:63]
COMS
Reverse
COM[63:0]
COMS
6.11.2 LCD Driver Circuits
There are 197 channel drivers that generate four voltage levels for driving the liquid
crystal. The combination of the display data, the COM scan signal, and the M signal
produces the liquid crystal drive voltage output. Figure 7 shows examples of the SEG
SEG0
SEG1
SEG2
SEG3
SEG4
and COM output waveform.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM63
M
COM0
COM1
SEG0
Fig. 7
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 19
EM62100
65 COM/132 SEG STN LCD Driver
6.11.3 Configuration Setting
The EM62100 has two-optional configurations, configured by DUTY0 and DUTY1, as
shown in Table 9.
Table 9
Duty ratio
Duty1
Duty0
1/33
0
0
1/49
0
1
1/55
1
0
1/65
1
1
LCD bias
V1
V2
V3
V4
1/5
1/6
1/6
1/8
1/6
1/8
1/7
1/9
(4/5)V0
(5/6)V0
(5/6)V0
(7/8)V0
(5/6)V0
(7/8)V0
(6/7)V0
(8/9)V0
(3/5)V0
(4/6)V0
(4/6)V0
(6/8)V0
(4/6)V0
(6/8)V0
(5/7)V0
(7/9)V0
(2/5)V0
(2/6)V0
(2/6)V0
(2/8)V0
(2/6)V0
(2/8)V0
(2/7)V0
(2/9)V0
(1/5)V0
(1/6)V0
(1/6)V0
(1/8)V0
(1/6)V0
(1/8)V0
(1/7)V0
(1/9)V0
6.12 Power Supply Module
The power supply circuits have low power consumption and generate the voltage
levels necessary to drive the LCD.
There are Booster (step-up voltage) circuits,
Voltage regulator circuits, and voltage follower circuits. They are valid only when
operating in master mode.
The power supply circuit can turn the Booster circuits, the voltage regulator circuits and
the voltage follower circuit ON or OFF independently through the Power Control Set
command. Consequently, it is possible to make both external and internal power
supplies function in parallel. Table 10 shows the Power Control Set Command 3-bit
data control function. Table 11 shows the reference combinations.
Table 10
Status
Item
H
L
D2 Voltage Booster (V/B) circuit control bit
ON
OFF
D1 Voltage Regulator (V/R) circuit control bit
ON
OFF
D0 Voltage Follower (V/F) circuit control bit
ON
OFF
Table 11. Recommended Power Supply Combinations
Use Step-up
Only the internal power
supply is used
Only the V/R circuit and
V/F circuits are used
Only the V/F circuit is
used
Only the external
power supply is used
20 •
V/B V/R V/F
V/B
V/R
V/F
Circuit Circuit Circuit
External
Voltage
Input
Step-up
Voltage
System
Terminal
1
1
1
ON
ON
ON
VEE
Used
0
1
1
OFF
ON
ON
VOUT, VEE
Open
0
0
1
OFF
OFF
ON
V0, VEE
Open
0
0
0
OFF
OFF
OFF
V0 to V4
Open
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
NOTE
For the “Step-up system terminals” refer to CAP1+, CAP1-, CAP2+, CAP2-,
CAP3+ and CAP4+.
Other combinations, not shown above, are also possible, but such combinations
are not recommended for they have no practical use.
6.12.1 Step-up Voltage Circuit
With the built-in boost up voltage circuit of the EM62100 chip, it is possible to produce a
5X, 4X, 3X, and 2X step-up of the VEE voltage levels.
The step-up voltage
relationships are shown in Figure 8.
5X Step-up Voltage
Circuit
4X Step-up Voltage
Circuit
3X Step-up Voltage
Circuit
2X Step-up Voltage
Circuit
VSS
VSS
VSS
VOUT
VOUT
VOUT
VOUT
VSS
CAP3+
CAP3+
CAP3+
CAP3+
CAP1-
CAP1-
CAP1-
CAP1-
CAP1+
CAP2+
CAP1+
CAP2+
CAP1+
CAP2+
CAP1+
CAP2+
CAP2-
CAP2-
CAP2-
CAP2-
CAP4+
CAP4+
CAP4+
CAP4+
VOUT =5 X VEE=14V
VOUT=4X VEE=12V
VOUT=3 X VEE=9V
VEE = 2.8V
VSS = 0V
VEE = 3V
VSS = 0V
VOUT=2 X VEE=6V
VEE = 3V
VEE = 3V
VSS = 0V
VSS = 0V
Fig. 8
6.12.2 Voltage Regulator Circuit
The step-up voltage generated at VOUT outputs the LCD driver voltage V0 through the
voltage regulator circuit by adjusting resistors, Ra and Rb.
Because the EM62100 chip has an internal high-accuracy fixed voltage power supply
with a 64-level electronic volume function and internal resistors for the V0 voltage
regulator, systems can be constructed without having to include high-accuracy voltage
regulator circuit components.
Using V0 voltage regulator internal resistors
By using the V0 voltage regulator internal resistors and the electronic volume
function, the liquid crystal power supply voltage V0 can be controlled through
command executions alone (without adding external resistors), allowing for
adjustments on the LCD brightness. The V0 voltage can be calculated using
equation (a) over the range where V0<VOUT.
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 21
EM62100
65 COM/132 SEG STN LCD Driver
Rb
63 −
Rb
) x VEV = (1+
) x (1) x VREG ------------------- (a)
Ra
Ra
162
V0 = (1+
Rb
VOUT
-
V0
Ra
+
VEV (constant voltage supply
+ electronic volume)
VEV
VSS
Fig. 9
VREG is the IC internal fixed voltage supply, and its voltage at Ta = 25°C is as shown
below.
Equipment Type
Thermal Gradient
Internal power supply
-0.05
Units
%/
VREG
2.1
The α is set to 1 level of 64 possible levels of the electronic volume function depending
on the data set in the 6-bit electronic volume register. Table 12 shows the value for α
depending on the electronic volume register settings.
Table 12
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
:
0
:
1
1
1
1
1
1
0
1
0
:
0
:
0
1
V0
0
1
2
:
32
:
62
63
Minimum
:
:
:
(Default)
:
:
Maximum
Rb/Ra is the V0 voltage regulator internal resistor ratio and can be set to 8 different
levels through the V0 voltage regulator internal resistor ratio set command.
The
(1+Rb/Ra) ratio assumes the values shown in Table 13 depending on the 3-bit data
settings in the V0 voltage regulator internal resistor ratio register.
22 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
Table 13
Equipment Type by Thermal Gradient
(Unit: % / °C)
Register
D2
D1
D0
-0.05
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.0
3.5
4.0
4.5
5.0 (Default)
5.5
6.0
6.4
- (
% &
- $% '
- $% &
-/. % '
-/. % &
- - %'
- - %&
- &
% '
- &
% &
C ,,%% &'
?= @ AB> ++ %% &'
* %'
* %&
)% '
)% &
'% '
'% &
(
% '
(
% &
$% '
$% &
!"#
D
E F
D
E G
H
HE G
G
GE G
I
I EH
&
+
-)
$.
(&
.(
01 2/3/4 5 678 3:9 ;1 < 2
(+
')
)(
Fig.10 Contrast Curve of V0 Voltage with Internal Resistors
6.12.3 Liquid Crystal Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage divider within the IC, and can
generate the V1, V2, V3, and V4 voltage levels required for LCD driving. Moreover,
when the voltage follower changes the impedance, it provides V1, V2, V3, and V4 to
the liquid crystal drive circuit. 1/9 bias or 1/7 bias for EM62100 can be selected.
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 23
EM62100
65 COM/132 SEG STN LCD Driver
6.12.4 High Power Mode
The EM62100 built-in power supply circuit has very low power consumption (normal
mode: HPMB=“H”). If used for LCD panels with large loads, this low-power power
supply may cause the display quality to degrade. When this occurs, setting the HPMB
terminal to “L” (high power mode) can improve the display quality. It is recommended
that the display be checked on the actual equipment to determine whether or not to use
this mode.
Moreover, if the improvement to the display is inadequate even after the high power
mode has been set, then it is a must to add a Command Sequence when the Built-in
Power Supply is turned OFF. To turn off the built-in power supply, follow the command
sequence as shown below, wherein you have to turn it off after making the system
enter the standby mode.
6.12.5 Reference Power Supply Circuit for Driving the LCD Panel
Using all LCD power circuits
(Voltage booster, regulator and follower)
The following diagram illustrates using 4X
boosting circuit and internal regulator
resistors, IRS =1
Not using voltage booster circuits
The following circuit diagram illustrates
using external regulator resistors, IRS = 0
VDD
VDD
M/S
C1
M/S
External
Power
Supply
VOUT
CAP4+
VOUT
CAP4+
CAP2+
CAP2+
C1
C1
C1
CAP2-
CAP2-
CAP1+
CAP1+
CAP1-
CAP1CAP3+
CAP3+
VREF
Rb
Ra
VREF
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
Using only voltage follower
Not using internal LCD power supply circuits
VDD
VDD
M/S
CAP2+
External
Power
Supply
C2
C2
C2
C2
C2
M/S
Value of External Capacitance
VOUT
CAP4+
ITEM
Value
C1
1.0 - 4.7
C2
0.1 - 2.2
µF
VOUT
CAP4+
CAP2+
CAP2-
CAP2-
CAP1+
CAP1+
CAP1-
CAP1-
CAP3+
CAP3+
VREF
VREF
V0
V1
V2
V3
V4
V0
V1
V2
V3
V4
External
Power
Supply
VSS
VSS
Fig.11
24 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
6.13 Reset Circuit
6.13.1 Initial Value of the Command Register
When the RESB input falls to “L”, the EM62100 will re-enter into its default state and the
following conditions occur.
1.
Display OFF
2.
Normal display
3.
ADC select: Normal display (ADC command D0 = “L”)
4.
Power control register (D2, D1, D0) = (0, 0, 0,)
5.
The serial interface register data is reset to its initial value.
6.
LCD power supply bias ratio: 1/9 (1/65 duty), 1/8 (1/49 duty), 1/6 (1/33 duty)
7.
Read modify write: OFF
8.
Static indicator: OFF
Static indicator register: (D1, D2) = (0, 0)
9.
The Display start line register is set at the first line.
10. The Column address counter is set at address 0.
11. The Page address register is set at page 0.
12. Common output status: normal
13. The V0 voltage regulator internal power supply ratio is reset to its default value.
V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0)
14. The Electronic volume register is reset to its default value.
Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0,)
15. Resets during Test mode
16. Oscillation frequency: 31.4kHz
17. Normal display mode and frame inversion status (partial display and N-Line
inversion release)
18. Partial display duty register: (D2, D1, D0) = (1, 0, 0), 1/65 duty
19. Partial display bias register: (D2, D1, D0) = (1, 0, 1), 1/9 bias
20. N-Line inversion register: (D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0), 13-Line inversion
21. Partial start line register: (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0), the first line
22. DC/DC clock division register: (D3, D2, D1, D0) = (0, 0, 1, 1), fOSC/6
23. Output condition of COM, SEG
COM: VSS
SEG: VSS
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 25
EM62100
65 COM/132 SEG STN LCD Driver
When the reset command is used, only default settings (7) to (15) listed above are
executed.
The MPU interface, the RESB terminal is connected to the MPU reset terminal, making
the chip reinitialize simultaneously with the MPU. During power on, it is necessary to
reinitialize using the RESB terminal.
In the EM62100, if the internal liquid crystal power supply circuit is not used, it is
necessary to apply an “L” signal to the RESB terminal when the external liquid crystal
power supply is applied. Even though the oscillator circuit operates while the RESB
terminal is “L”, the display timing generator circuit is stopped, and the M, FLM, and
DOFB terminal is “H”, and the CKS terminal is fixed to “H” only when the internal
oscillator circuit is used. There is no influence on D0 to D7 terminals.
7
Command Register & Decoder
The EM62100 uses a combination of A0, RDB (E), and WRB (RW) signals to identify
the data bus signals. As the chip analyzes and executes each command using internal
timing clock only, regardless of external clock, its processing speed is very high and its
busy check is usually not required. The 8080 series MPU interface enters a read status
when a low pulse is input to the RDB (E) pin and to a write status when a low pulse is
input to the WRB (RW) pin. The 6800 series MPU interface enters a read status when
a high pulse is input to the RW pin and to a write status when a low pulse is input to the
RW pin. When there is a high pulse to the E pin, the command is activated. For timing
details, see AC characteristics section.
Taking the 8080 series MCU interface as an example, the commands are explained
below. Accordingly, in the command table and explanation, RDB (E) becomes high (1)
when 6800 series MPU interface reads the display data status. When the serial
interface is selected, the input data starts from D7 in sequence.
26 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.1 Command Table
Command
RS
RDB
WRB
Code
D7
D6
D5
D2
Hex
1
0
1
AEh
AFh
0
1
0
(2) Display Start
Line Set
0
1
0
0
1
(3) Page
Address Set
0
1
0
1
0
1
1
Page Address
0
1
0
0
0
0
1
High Column
Address
0
1
0
0
0
0
0
Low Column
Address
(5) Read Status
0
0
1
(6) Write Display
Data
1
1
0
(7) Read Display
Data
1
0
1
1
0
0
40h
to
7Fh
Display Start Address
1
B0h
to
B8h
Function
Turns on the
LCD panel
when high, and
turns off when
low
Specifies the
RAM display
line for COM0
Sets the display
data RAM page
in Page
Address
register
00h
to
18h
Sets 4 higher
bits and 4 lower
bits of column
address of
display data
RAM in register
XX
Reads the
status
information
Write Data
XX
Writes data in
display data
RAM
Read Data
XX
Reads data
from display
data RAM
Status
1
1
D0
1
0
1
D1
0
(8) ADC Select
0
D3
(1) Display OFF
(4) Column
Address Set
1
D4
0
0
0
0
0
0
0
0
0
1
A0h
A1h
Sets the display
data RAM
address SEG
output
correspondence
A6h
A7h
Normal display
when low, but
reverse display
when high
(9) Normal/
Reverse
Display
0
1
0
1
0
1
0
0
1
1
0
1
(10) Entire
Display
ON/OFF
0
1
0
1
0
1
0
0
1
0
0
1
A4h
A5h
Selects normal
display (0) or
entire display on
(11) LCD Bias
Set
0
1
0
1
0
1
0
0
0
1
0
1
A2h
A3h
Sets the LCD
driving voltage
bias ratio
E0h
Increments
column address
counter during
each write
(12)
Read-Modify
-Write
0
1
0
1
1
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
1
0
0
0
0
0
• 27
EM62100
65 COM/132 SEG STN LCD Driver
Command
RS
RDB
WRB
(13) End
0
1
(14) Reset
0
(15) Common
Output
Mode
Select
Function
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
1
1
0
1
1
1
0
EEh
Releases the
Read-ModifyWrite
1
0
1
1
1
0
0
0
1
0
E2h
Resets internal
functions
0
1
0
1
1
0
0
0
1
*
*
*
C0h
to
CFh
Selects COM
output scan
direction
(16) Power
Control Set
0
1
0
0
0
1
0
1
Operation
Status
28h
to
2Fh
Selects the
power circuit
operation mode
(17) V0 Voltage
Regulator
Internal
Resistor
Ratio Set
0
1
0
0
0
1
0
0
Resistor
Ratio
20h
to
27h
Selects internal
resistor ratio
Rb/Ra mode
0
1
0
1
0
0
0
0
(18) Electronic
Volume
Mode Set
Electronic
Volume
Register
Set
(19) Set Static
Indicator
ON/OFF
Set Static
Indicator
Register
28 •
Code
0
0
1
0
1
0
*
*
Electronic Control Value
0
1
0
1
0
1
0
1
1
0
0
1
0
*
*
*
*
*
*
Mode
81h
XX
0
1
ACh
ADh
Sets the V0
output voltage
electronic
volume register
Sets static
indicator
ON/OFF
XX
Sets the flash
mode
Compound
command of
Display OFF
and Entire
Display ON
(20) Power Save
0
1
0
-
-
-
-
-
-
-
-
-
(21) NOP
0
1
0
1
1
1
0
0
0
1
1
E3h
Command for
non-operation
(22) Oscillation
Frequency
Select
0
1
0
1
1
1
0
0
1
0
0
1
E4h
E5h
Selects the
oscillation
frequency
(23) Partial
Display
Mode Set
0
1
0
1
0
0
0
0
0
1
0
1
82h
83h
Enter/Release
the partial
display mode
(24) Partial
Display
Duty Set
0
1
0
0
0
1
1
0
30h
37h
Sets the LCD
duty ratio for
partial display
mode
Duty Ratio
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
Command
(25) Partial
Display
Bias Set
(26) Partial Start
Line Set
Partial Start
Line
(27) N-Line
Inversion
Set
Number of
Line Set
(28) N-Line
Inversion
Release
(29) DC/DC
Clock Set
DC/DC
Clock
Division Set
RS
RDB
WRB
Code
D7
D6
D5
D4
D3
0
1
0
0
0
1
1
1
0
1
0
1
1
0
1
0
D2
D1
D0
Hex
Bias Ratio
0
1
1
Partial Start Line
Function
38h
3Fh
Sets the LCD
bias ratio for
partial display
mode
D3h
Enters Partial
Start Line Set
0
1
0
1
1
0
1
0
1
0
0
0
1
0
*
*
*
0
1
0
1
0
0
0
0
1
0
0
84h
Exits N-Line
Inversion
0
1
0
1
1
0
0
0
1
1
0
E6h
Sets DC/DC
Clock
Frequency
0
1
0
1
1
0
0
XX
Sets the
Division of
DC/DC Clock
Frequency
0
0
1
XX
Sets the LCD
Number of
partial display
start line
Enters N-line
inversion
Sets the
number of line
used for N-Line
inversion
0
1
85h
Number of Line
XX
Clock Division
Table 14
7.2 Command Function
7.2.1 Display ON/OFF
This command turns the display on or off. When display OFF command is executed
during display all points ON mode, power saving mode is entered.
RS
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Setting
1
0
1
0
1
1
1
1
0
AFH
AEH
Display ON
Display OFF
7.2.2 Display Start Line Set
This command specifies a line address thus marking the display line that corresponds
to COM0. When this command changes the line address, smooth scrolling or a page
change occurs.
RS
0
RDB WRB
1
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
A5
A4
A3
A2
A1
A0
40H to 7FH
0
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 29
EM62100
65 COM/132 SEG STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
40H to 7FH
0
1
A5
A4
A3
A2
A1
A0
Line Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
J
J
J
1
1
1
1
J
J
1
1
1
1
1
1
J
0
1
62
63
7.2.3 Page Address Set
This command is used to specify a page address equivalent to a row address for MPU
access to the display data RAM. Any RAM data bit can be accessed when its page
address and column address are specified. The display remains unchanged even
when the page address is changed. Page address 8 is the display RAM area indicated
by the indicator, and only D0 is valid for data change.
RS
0
RDB WRB
1
D7
D6
D5
D4
D3
D2
D1
D0
Hex
1
0
1
1
A3
A2
A1
A0
B0H to B8H
0
D7
D6
D5
D4
D3
D2
D1
D0
B0H to B8H
1
0
1
1
A3
A2
A1
A0
Page Address
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
J
J
J
J
J
J
1
1
1
0
7
1
0
0
0
8
7.2.4 Column Address Set
This command specifies a display data RAM column address. In setting, the column
address is split into two parts (the upper 4-bits and the lower 4-bits). The column
address is automatically incremented by 1 each time the MPU accesses from the set
address to the display data RAM.
Therefore, the MPU can access the data
continuously. However, the column address is no longer incremented at address 131
(83H), and the page address is not changed continuously.
RS RDB WRB D7
0
30 •
1
0
0
D6
D5
0
0
D4
D3
D2
D1
D0
Hex
1
A7
A6
A5
A4
10H to 18H
0
A3
A2
A1
A0
00H to 0FH Lower bits
Upper bits
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
A7
A6
A5
A4
A3
A2
A1
A0
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
J
J
J
1
1
0
0
0
0
0
0
J
J
0
0
0
0
1
1
J
0
1
130
131
7.2.5 Read Status
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
BUSY
ADC
ON/OFF
RESET
0
0
0
0
Busy:
the busy bit indicates whether the driver accepts instruction or not.
Busy=0: the driver will accept new instruction
Busy=1: no new instruction will be accepted
ADC:
ADC=0: reverse (column address 131-n
ADC=1: normal (column address n
segment driver n)
segment driver n)
ON/OFF: indicates the current status of the display
ON/OFF=0: display ON
ON/OFF=1: display OFF
Reset:
indicates whether the driver is executing a hardware or software reset or if it
is in normal operating mode.
Reset=0: normal operation
Reset=1: currently executing a reset instruction
7.2.6 Write Display Data
Writes an 8-bit data from the data bus into the display RAM. Since the column address
automatically increments by 1 after each write, the microprocessor can continue to
write data with multiple words.
RS
RDB
WRB
1
1
0
D7
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
D6
D5
D4
D3
D2
D1
D0
Write data
• 31
EM62100
65 COM/132 SEG STN LCD Driver
7.2.7 Read Display Data
Reads an 8-bit data from the display RAM area specified by the column address and
page address. Since the column address is automatically incremented by 1 after each
write, the microprocessor can continue to read data of multiple words. A single dummy
read is required immediately after a column address setup. For details, refer to the
display RAM section of the FUNCTIONAL DESCRIPTION. When serial interface is
used, reading from the display data becomes invalid.
RS
RDB
WRB
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
7.2.8 ADC Select
Changes the relationship between the RAM column address and the segment driver.
This command specifies the order of the segment driver pads. The column address is
automatically incremented by 1 after every read or write operation is performed on the
display data.
RS
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Setting
1
0
1
0
0
0
0
0
1
A0H
A1H
Normal
Reverse
7.2.9 Normal/Reverse Display
This command can reverse the lit and unlit display command without overwriting the
contents of the display data RAM. After executing this command, the display data RAM
contents are maintained.
RS
0
RDB WRB D7
1
0
1
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
0
1
Hex
Setting
RAM data "H"
A6H LCD ON voltage
(normal)
RAM data "L"
A7H LCD ON voltage
(reverse)
7.2.10 Entire Display ON
This command makes it possible to force all display points ON regardless of the
contents of the display data RAM. The contents of the DISPLAY DATA RAM are
maintained after executing this command.
This command has priority over the
Normal/Reverse Display command. When D is low, the normal display status is
provided.
RS
0
RDB WRB D7
1
0
1
D6
D5
D4
D3
D2
D1
D0
Hex
Setting
0
1
0
0
1
1
0
A4H Normal display mode
1
A5H Display all points ON
When D0 is high, the entire display ON status is provided. If the Entire Display ON
command is executed in the display OFF status, the LCD panel enters Power saving
mode. Refer to the Power Saving section for details.
32 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.2.11 LCD Bias Set
This command specifies the voltage Bias ratio for the LCD.
Duty
RS RDB WRB D7 D6 D5 D4 D3 D2 D1 D0 Hex
0
1
0
1
0
1
0
1
1
1
1/33
1/49
1/55
1/65
0
A2H 1/6bias 1/8bias 1/8bias 1/9bias
1
A3H 1/5bias 1/6bias 1/6bias 1/7bias
7.2.12 Read-Modify-Write
A pair of Read-Modify-Write and End commands must always be used.
Once
Read-Modify-Write is issued, the column address is not incremented by a Read Display
Data command but incremented by a Write Display Data command only. The current
contents of the column address register are saved. This mode remains active until an
“End” command is issued, after which, the column address returns to the address when
Read-Modify-Write command was issued. This can reduce the microprocessor load
when data of a specific display area is repeatedly changed during cursor blinking or
other events.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
0
0
0
0
E0H
NOTE
Any command except Read/Write Display Data and Column Address Set can be
issued during Read-Modify-Write mode.
Set Page Address
Set Column Address
Read-Modify-Write
Dummy Read
Read Data
No
Data
Processing
Write Data
Completed
Yes
End
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 33
EM62100
65 COM/132 SEG STN LCD Driver
7.2.13 End
This instruction cancels the read-modify-write instruction, returning the column address
to the initial mode address.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
1
1
1
0
EEH
K
MK LON KPLQ
TVUXW/YZ S[YX\ ] ^Z _a` \ b U
c [YdUe\ fOf U/g UXhb U/Y
KPLR
K
KPLS
i KMj
7.2.14 Reset
This command initializes the Display Start Line register, the column address, the page
address counter, and the Common output mode register, the V0 voltage regulator
internal resistor ratio, the electronic volume, and the static indicator are reset, and
read-modify-write mode and test mode are released. This does not affect the contents
of the display RAM.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
0
0
1
0
E2H
The Reset command cannot initialize the LCD power supply. Only the Reset signal to
the RESB pad can initialize the supplies.
7.2.15 Output Status Select Register
This command can select the scan direction of the common output terminal. When D3
is high or low, the scan direction of the COM output pad is selectable. For details, refer
to the Output Status Selector Circuit in the FUNCTION DESCRIPTION section.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
0
0
0
*
*
*
C0H to C7H
1
C8H to CFH
* Invalid bit
D3 = 0: Normal (COM0
COM63/47/31)
D3 = 1: Reverse (COM63/47/31
34 •
COM0)
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.2.16 Power Control Set
This command sets the function of the power supply circuit. Select one of the eight
power circuit functions using a 3-bit register. An external power supply and part of an
on-chip power circuit can be used simultaneously. For details, refer to the Power
Supply Circuit in the FUNCTION DESCRIPTION section.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
0
0
1
0
1
VB
VR
VF
28H to 2FH
When VF goes low, the voltage follower turns off. When VF goes high, it turns on.
When VR goes low, the voltage regulator turns off. When VR goes high, it turns on.
When VB goes low, the voltage booster turns off. When VB goes high, it turns on.
7.2.17 V0 Voltage Regulator Internal Resistor Ratio Set
This command sets the V0 voltage regulator internal resistor ratio. For details, see the
explanation under “The Power Supply Circuits”.
RS
RDB
WRB
D7
D6
D5
D4
D3
0
1
0
0
0
1
0
0
D2
D1
D0
Hex
Setting
Small
0
0
0
20H
0
0
0
1
1
0
21H
22H
J
J
J
J
J
J
J
J
J
1
1
0
26H
1
1
1
27H
Large
7.2.18 Electronic Volume (Double Byte Command)
This command allows adjustments can be made on the brightness of the liquid crystal
display by controlling the liquid crystal drive voltage V0 through the output from the
voltage regulator circuits of the internal liquid crystal power supply. This command is
used in pair with the electronic volume mode set command and the electronic volume
register set command, and both commands must be issued one after the other.
(1) The Electronic Volume Mode Set
When this command is input, the electronic volume register set command is
enabled. Immediately after the electronic volume mode has been set, no other
command except for the electronic volume register command can be used. Once
the electronic volume register set command has been used to set data into the
register, then the electronic volume mode is released.
RS
0
RDB WRB
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Hex
1
0
0
0
0
0
0
1
81H
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 35
EM62100
65 COM/132 SEG STN LCD Driver
(2) Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the
LCD drive voltage V0 assumes one of the 64 voltage levels. When this command is
input, the electronic volume mode is released after the electronic volume register
has been set.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Setting
0
1
0
*
*
0
0
0
0
0
1
01H
Small
0
0
0
0
1
0
02H
J
J
J
J
J
J
J
J
1
1
1
1
1
0
3EH
1
1
1
1
1
1
3FH
J
Large
When the electronic volume function is not used, set D5 - D0 to 100000.
7.2.19 Static Indicator (Double Byte Command)
This command controls the static drive system indicator display. The static indicator
display is controlled by this command only, and is independent of other display control
commands. This is used when one of the static indicator LCD drive electrodes is
connected to the M terminal, and the other is connected to the FLM terminal. Different
patterns are recommended for the static indicator electrodes and for the dynamic drive
electrodes. If the patterns are too close, it can result in deterioration of the LCD and of
the electrodes.
The static indicator ON command is a double bytes command paired with the static
indicator register set command, and such commands must be executed one after the
other. (The static indicator OFF command is a single byte command)
(1) Static Indicator ON/OFF
When the static indicator ON command is executed, the static indicator register set
command is enabled, and no other command aside from the static indicator register
set command can be used. This mode is cleared when data is set in the register by
the static indicator register set command.
RS RDB WRB D7
0
36 •
1
0
1
D6
D5
D4
D3
D2
D1
D0
Hex
Setting
0
1
0
1
1
0
0
ACH Static indicator OFF
1
ADH Static indicator ON
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
(2) Static Indicator Register Set
This command sets two bits of data into the static indicator register and used to set
the static indicator into a blinking mode.
RS RDB WRB D7 D6 D5
0
1
0
*
*
*
D4 D3 D2
*
*
*
D1 D0 Hex
Setting
0
0
00H
OFF
0
1
01H
ON
blinking at ≈ 1sec interval
1
0
02H
ON
blinking at ≈0.5sec interval
1
1
03H
ON (constantly on)
7.2.20 Power Save (Compound Command)
The power save mode is entered when the display all points ON command is executed
while in the display OFF mode. The power save mode includes the sleep mode and the
standby mode. The sleep mode is entered when the static indicator is OFF, and the
standby mode is entered when the static indicator is ON. This mode is cleared by the
display all points OFF command.
The sleep mode operation stops all operations in the LCD display system, and as long
as there are no accesses from the MPU. In sleep mode operation, the oscillator circuit,
the LCD power supply circuit, and all LCD driver circuits are put on halt.
Release the Sleep mode using both Power Save OFF command (Display ON
command or Entire Display OFF command) and Set Indicator On command.
Static Indicator OFF
(D7-D0)=AC (Hex)
1. Display OFF
(D7-D0)=AE (Hex)
2. Entire Display ON
(D7-D0)=A5 (Hex)
Static Indicator ON
(D7-D0)=AD (Hex)
(D7-D0)=X0~X3H (Hex)
1. Display OFF
(D7-D0)=AE (Hex)
2. Entire display ON
(D7-D0)=A5 (Hex)
Sleep Mode
Stanby Mode
1. Normal Display Mode
(D7-D0)=A4 (Hex)
2. Static Indicator ON
(D7-D0)=AD (Hex)
(D7-D0)=X0~X3H (Hex)
Normal Display Mode
(D7-D0)=A4 (Hex)
Stanby Mode Cancel
Sleep Mode Cancel
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
X: don't care
• 37
EM62100
65 COM/132 SEG STN LCD Driver
Sleep Mode
This mode stops every operation of the LCD display system, and can reduce current
consumption nearly to a static current value if no access is made from the
microprocessor. The internal status in the sleep mode is as follows:
(1) Stops the oscillator circuit and LCD power supply circuit.
(2) Stops the LCD driver and outputs the VSS level as the segment/common driver
output.
(3) Holds the display data and operation mode that momentarily existed before the start
of the sleep mode.
(4) The MPU can access the built-in display data RAM.
Standby Mode
Stops the operation of the duty LCD display system and turns on only the static drive
system to reduce power consumption to the minimum level required for static drive.
The ON operation of the static drive system indicates that the EM62100 is in standby
mode. The internal status in the standby mode is as follows:
(1) Stops the LCD power supply circuit.
(2) Stops the LCD drive and outputs the VSS level as the segment / common driver
output. However, the static drive system still operates.
(3) Holds the display data and operation mode that momentarily existed before the start
of the standby mode.
(4) The MPU can access the built-in display data RAM.
When the Reset command is issued in the standby mode, the sleep mode is set.
When the LCD drive voltage level is provided by an external resistive driver, the
current of this resistor must be cut so that it may be fixed to floating or VSS level,
prior to or concurrently used, causing the EM62100 to go to the sleep mode or
standby mode.
When an external power supply is used, likewise, the function of this external
power supply must be stopped so that it may be fixed to floating or VSS level, prior
to or concurrently used, causing the EM62100 to go to the sleep mode or standby
mode.
7.2.21 NOP
Non-Operation Command
38 •
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
0
0
1
1
E3H
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.2.22 Test Command
This is the dedicated IC chip test command. It must not be used during operation. It
can be cleared by applying an “L” signal to set the RESB input or issue the reset
command to release the test mode.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
1
0
1
0
0
F0H to FFH
7.2.23 Oscillation Frequency Select
This command is to select the oscillation frequency of the driver IC as shown below.
RS
RDB
WRB
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0 Hex Oscillation Frequency
1
1
1
0
0
1
0
0
E4H
Typical 31.4kHz
1
E5H
Typical 26.3kHz
7.2.24 Partial Display Mode Set
This command is to select the display mode. When D0 is “L”, the IC is in normal display
mode, the maximum display duty ratio is determined by the pin connection of DUTY0
and DUTY1 and the command LCD Bias Set determines the LCD bias ratio. The IC
enters into partial display mode when D0 is high, then the commands Partial Display
Duty Set and Partial Display Bias Set determine the LCD display duty and bias ratios.
RS
RDB
WRB
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0 Hex
1
0
0
0
0
0
1
Display Mode
0
82H
Normal Display
1
83H
Partial Display
7.2.25 Partial Display Duty and Bias Set
These two commands set the LCD display duty and bias ratios when the IC is in partial
display mode. Such commands are invalid when the IC is in normal display mode.
When the partial display duty is set, the LCD bias for partial display is also set
concurrently. The partial display duty will be kept at maximum duty (determine by pins
DUTY0 and DUTY1) when the duty set is larger than the maximum duty.
RS
0
RDB WRB D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
1
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
0
Hex
Partial Duty Scanning Line
0
0
0
30H
1/9 duty
Line[0:7], COMS
0
0
1
31H
1/17 duty
Line[0:15], COMS
0
1
0
32H
1/33 duty
Line[0:31], COMS
0
1
1
33H
1/49 duty
Line[0:47], COMS
1
0
0
34H
1/65 duty
Line[0:63], COMS
1
0
1
35H
1/55 duty
Line[0:53], COMS
1
1
* 36H/37H
Reserved
No effect
• 39
EM62100
65 COM/132 SEG STN LCD Driver
Using Partial Display Bias Set command to adjust the LCD bias in partial display mode.
RS
RDB WRB D7
0
1
0
D6 D5 D4 D3 D2 D1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
D0
Hex
LCD Bias
0
1
0
1
0
1
0
1
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1/4
1/5
1/6
1/7
1/8
1/9
Reserved
Reserved
NOTE
The COM waveform of no display area is non-select waveform.
7.2.26 Partial Start Line Set (Double Byte Command)
This command makes it possible to set the partial start line for partial display. It is a
two-byte command used in pair and the Number of Start Line Set command must be
issued after the Partial Start Line Set command.
(1) Partial Start Line Set
When this command is input, no other commands except for the Number of Start
Line Set command can be used.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
0
1
0
0
1
1
D3H
(2) Number of Start Line Set
This command is used to set six bits of data to the Partial Start Line register.
Immediately after the Number of Start Line Set command has been issued to set
data into the register, then the partial start line will affect the LCD display. The
number of partial start line is always equal to zero when the partial start line is larger
than the maximum duty ratio (determine by pins DUTY0 and DUTY1).
RS RDB WRB D7
0
1
0
*
D6
D5
D4
D3
D2
D1
D0
Hex
Partial
Start Line
*
0
0
0
0
0
0
00H
0 line
0
0
0
0
0
1
01H
1 line
0
0
0
0
1
0
02H
2 lines
J
J
J
J
J
40 •
J
J
J
J
1
1
1
1
1
0
3EH
62 lines
1
1
1
1
1
1
3FH
63 lines
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.2.27 N-line Inversion (Double Byte Command)
This command allows adjustments on the number of scan lines for liquid crystal display
inversion. It is a two-byte command used in pair and the Number of Line Set command
must be issued after the N-Line Inversion Set command.
7.2.27.1 N-Line Inversion Set
When this command is input, no other command except for the Number of Line Set
command can be used.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
0
0
0
0
1
0
1
85H
7.2.27.2 Number of Line Set
This command is used to set five bits of data to the N-Line inversion register. Once the
Number of Line Set command has been issued to set data into the register, then the
N-Line inversion will affect the LCD display.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Line
Inversion
0
1
0
*
*
*
0
0
0
0
0
00H
1 line
0
0
0
0
1
01H
2 lines
1
1
1
1
1
1FH
32 lines
J
J
J
NOTE
The number of inversed scan line = register setting value + 1.
When Partial Duty = 1/9 or 1/17, the N-line inversion function is released and
the LCD display scan line is back to frame inversion status.
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Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 41
EM62100
65 COM/132 SEG STN LCD Driver
7.2.28 Release N-line Inversion
This command is used to cancel the N-Line inversion function. The N-Line inversion
function is cancelled and the LCD display is set back to frame inversion status once this
command is executed.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
0
0
0
0
1
0
0
84H
7.2.29 DC/DC Clock Frequency (Double Byte Command)
This command allows adjustments on the frequency for DC/DC clock. It is a two-byte
command used in pair and the DC/DC Frequency Division Set command should be
issued after the DC/DC Clock Set command.
7.2.29.1 DC/DC Clock Set
When this command is input, no other command except for the DC/DC Frequency
Division Set command can be used.
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
0
1
0
1
1
1
0
0
1
1
0
E6H
7.2.29.2 DC/DC Frequency Division Set
This command is used to set five bits of data to the frequency division register.
42 •
RS
RDB
WRB
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Division
0
1
0
*
*
*
*
0
0
0
0
00H
fOSC
0
0
0
1
01H
fOSC/2
0
0
1
0
02H
fOSC/4
0
0
1
1
03H
fOSC/6
0
1
0
0
04H
fOSC/8
0
1
0
1
05H
fOSC/10
0
1
1
0
06H
fOSC/12
0
1
1
1
07H
fOSC/14
1
0
0
0
08H
fOSC/16
1
0
0
1
09H
fOSC/18
1
0
1
0
0AH
fOSC/20
1
0
1
1
0BH
fOSC/22
1
1
0
0
0CH
fOSC/24
1
1
0
1
0DH
fOSC/26
1
1
1
0
0EH
fOSC/28
1
1
1
1
0FH
fOSC/30
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.3 Chip Initial State and Power ON/OFF Flowchart:
7.3.1 Initialization
Note: For this chip, when power is applied, the LCD driving non-selective potentials V2
and V3 (segment pins) and V1 and V4 (common pins) are output through the LCD
driving output pins SEG. and COM.
When electric charge still remains in the smoothing capacitor connecting between the
LCD driving voltage output pins (V0 - V4) and the VDD pin, the picture on the display
may instantaneously become totally dark when power is turned on. To avoid such
failure, we recommend the following flow sequence upon turning on the power.
7.3.1.1 With instant built-in power supply circuit, after turning on the power
Turn ON the VDD - VSS power, keeping the RESB pin = "L"
When power is stabilized
Release the reset state (RESB pin = "H")
Initialized state (Default)
Function setup by command input (User setup)
(11) LCD bias setting
( 8) ADC selection
(15) Common output state selection
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
to regulate the V0 voltage
(18) Electronic volume control
Function setup by command input (User setup)
(16) Power control setting
This concludes the initialization
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 43
EM62100
65 COM/132 SEG STN LCD Driver
7.3.1.2 Without instant built-in power supply circuit, after turning on the power
Turn ON the VDD - VSS power, keeping the RESB pin = "L"
When power is stabilized
Release the reset state (RESB pin = "H")
Initialized state (Default)
Power saver START (multiple commands)
Function setup by command input (User setup)
(11) LCD bias setting
( 8) ADC selection
(15) Common output state selection
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
to regulate the V0 voltage
(18) Electronic volume control
Power saver OFF (multiple commands)
Function setup by command input (User setup)
(16) Power control setting
This concludes the initialization
44 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
7.3.1.3 Displaying Data
End of initialization
Function setup by command input (User setup)
(11) LCD bias setting
( 8) ADC selection
(15) Common output state selection
Function setup by command input (User setup)
(6) Display data write
Function setup by command input (User setup)
(1) Display ON/OFF
End of Data Display
7.3.1.4 Power OFF
Optional status
Function setup by command input (User setup)
(20) Power save
VDD - VSS Power OFF
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 45
EM62100
65 COM/132 SEG STN LCD Driver
8
Absolute Maximum Ratings
Table 15 Absolute Maximum Ratings, unless otherwise specified, VSS = 0V
Parameter
Symbol
Conditions
Power Supply Voltage
VDD ,V EE
–0.3 to +4.0
V
Power Supply Voltage
VOUT
-0.3 to +15.0
V
Power Supply Voltage
V0
-0.3 to +15.0
V
Input Voltage
VIN
–0.3 to VDD + 0.3
V
Operating Temperature
TOPR
–40 to +85
°C
Storage Temperature
TSTR
–55 to +125
°C
Notes and Cautions
1. Ensure that the voltage levels of V1, V2, V3, and V4 are such that they are always
V0 V1 V2 V3 V4 VSS.
2. Permanent damage to the LSI may result if the LSI is used outside of the absolute
maximum ratings. Hence, it is recommended that in normal operation the chip be
used within the electrical characteristic conditions, otherwise, it may not only result
in malfunctions of the LSI, but may have a negative impact on the LSI reliability as
well.
9
DC Characteristics
Table 16. DC Characteristics
Item
46 •
Symbol
Operating
Voltage (1)
VDD
Operating
Voltage (2)
V0
High-level
Input Voltage
VIHC
Low-level
Input Voltage
VILC
High-level
Output Voltage
Low-level
Output Voltage
Condition & Application Pin
Pin VDD
Rating
Min.
Typ.
Max.
1.8
-
3.6
4.0
-
14.2
Pins RS, D0-D7, RDB (E), WRB
(RW), CS1B, CS2, CKS, CK, M,
M/S, M86, P/S, DOFB, RESB,
IRS, HPMB
0.8xVDD
VDD
VSS
0.2xVDD
VOH
C
IOH=-0.5mA
0.8xVDD
VDD
VOLC
IOL=0.5mA
VSS
0.2xVDD
Input Leakage
Current
ILI
VIN=VDD or VSS
Pins RS, RDB (E), WRB (RW),
CS1B, CS2, CKS, M/S, M86, P/S,
RESB, IRS, HPMB
-1.0
Hi-Z Leakage
Current
IHZ
Pins D0-D7, M, FLM , DOFB, CK
-3.0
Pins D0-D7, M ,
FLM, DOFB, CK
Unit
V
-
1.0
A
-
3.0
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
Item
LCD Driver
ON Resistor
Sleep Mode
Current
Consumption
Standby Mode
Current
Consumption
Symbol
Condition & Application Pin
RON1
Ta=25°C, Pin
COMn & SEGn
RON2
Ta=25°C, Pin
COMn & SEGn
ISP
ISB
IDD1
Current
Consumption
IDD2
IDD3
Input Terminal
Capacitance
Frame
Frequency
Input Voltage
CIN
fFRM
VEE
Rating
Typ.
Max.
V0=8V,
| V|=0.1V
2.0
3.5
V0=11V,
| V|=0.1V
3.2
5.4
VDD= 3V, 4 times booster
0.01
5
VDD= 3V, 4 times booster
4
10
20
35
VDD = 3V, V0=11V, built-in
boosting power supply off,
display on, display data =
checker and no access,
Ta=25 †
VDD, VEE = 3V, V0=11V, 4X
built-in boosting power supply,
display on, display data =
checker and no access,
temperature gradient is -0.05%
† , Ta=25 † , V0 voltage
internal resistor is used,
HPMB = 1
(normal power mode)
VDD, VEE = 3V, V0=11V, 4X
built-in boosting power supply,
display on, display data =
checker and no access,
temperature gradient is -0.05%
† , Ta=25 † , V0 voltage
internal resistor is used,
HPMB = 0 (high power mode)
Min.
k
-
A
-
90
160
-
150
255
-
5.0
8.0
fOSC = 31.4kHz,
1/65 duty VDD = 1.8~3.6V
78.1
80.5
82.9
fOSC = 26.3kHz,
1/65 duty VDD = 1.8~3.6V
65.4
With twice boost ratio
1.8
With triple times boost ratio
1.8
With quad and five times boost
ratio
1.8
Ta=25°C, f=1MHz
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
Unit
pF
Hz
67.4
-
69.5
3.6
3.3
V
3.0
• 47
EM62100
65 COM/132 SEG STN LCD Driver
Item
Supply
Step-up
Output
Voltage
Base Voltage
Symbol
Condition & Application Pin
VOUT1
Rating
Min.
Typ.
Max.
Booster output voltage on
VOUT pin (x5)
5xVEE
x0.95
5xVEE
x0.98
5xVEE
VOUT2
Booster output voltage on
VOUT pin (x4)
4xVEE
x0.95
4xVEE
x0.98
4xVEE
VOUT3
Booster output voltage on
VOUT pin (x3)
3xVEE
x0.95
3xVEE
x0.98
3xVEE
VOUT4
Booster output voltage on
VOUT pin (x2)
2xVEE
x0.95
2xVEE
x0.98
2xVEE
2.04
2.10
2.16
VREG
Ta=25°C
Unit
V
V
NOTE
1. Ensure that the voltage levels of V1, V2, V3, and V4 are in such a way that
V0 V1 V2 V3 V4 VSS.
2. Unless otherwise specified, VSS = 0V, VDD = 1.8 - 3.6V ±10%, Ta = –40 to 85°C
48 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
10 Timing Diagram
10.1 System Bus Read/Write Characteristics
(8080-Series Microprocessor)
RS
O‡ ˆ‰Š
‹ ‡Oˆ Œd‰Ž
tAH8
tAS8
tCYC8
WRB, RDB
tWRLW8, tRDLW8
tWRHW8, tRDLW8
tDH8
tDS8
D0-D7
(Write)
tOD8
tACC8
D0-D7
(Read)
(VDD = 2.7 ~ 3.6V, Ta = -40~+85°C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Address Hold time
tAH8
0
ns
Address Setup Time
tAS8
0
ns
System Cycle Time
tCYC8
240
ns
Write Pulse “L” Width
tWRLW8
120
ns
Write Pulse “H” Width
tWRHW8
100
ns
Data Setup Time
tDS8
40
ns
Data Hold Time
tDH8
10
ns
Read Pulse “L” Width
tRDLW8
120
ns
Read Pulse “H” Width
tRDHW8
100
ns
RDB Access Time
tACC8
Output Disable Time
tOD8
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
CL = 100 pF
5
140
ns
50
ns
Pin Used
RS
WRB
(RW)
D0-D7
RDB
(E)
D0-D7
• 49
EM62100
65 COM/132 SEG STN LCD Driver
10.2 System Bus Read/Write Characteristics
(6800-Series Microprocessor)
RS,
RW
‘’"“
” • –d—’"˜
tAH68
tAS68
tCYC68
tEHW68, tEHR68
E
tELW68, tELR68
tDS68
tDH68
D0-D7
(Write)
tOD68
tACC68
D0-D7
(Read)
VDD = 2.7 ~ 3.6V, Ta = -40~+85°C
Item
50 •
Symbol
Condition
Min.
Typ. Max. Unit Pin Used
Address Hold Time
tAH68
0
ns
Address Setup Time
tAS68
0
ns
System Cycle Time (Write)
tCYC68
240
ns
Enable pulse “H” Width (Write)
tEHW68
120
ns
Enable Pulse “H” Width (Read)
tEHR68
120
ns
Enable Pulse “L” Width (Write)
tELW68
100
ns
Enable Pulse “L” Width (Read)
tELR68
100
ns
Data Setup Time
tDS68
40
ns
Data Hold Time
tDH68
10
ns
RDB Access Time
tACC68
Output Disable Time
tOD68
CL = 100 pF
5
140
ns
50
ns
RS, RW
E
D0~D15
D0-D7
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
10.3 Serial Interface Characteristics
tCSH
tCSS
CS1B
(CS2)
RS
tASS
tAHS
tSLW
tSHW
SCL
tDSS
tDHS
SI
tCYCS
VDD = 2.7~3.6V, Ta = -40~+85°C . In serial mode, keep M86=L, RDB=H, WRB=H.
Item
Symbol
Condition
Min.
Typ.
Max.
Unit Pin Used
Serial Clock Period
tCYCS
120
ns
SCL Pulse “H” Width
tSHW
60
ns
SCL Pulse “L” Width
tSLW
60
ns
Address Setup Time
tASS
30
ns
Address Hold Time
tAHS
20
ns
Data Setup Time
tDSS
30
ns
Data Hold Time
tDHS
20
ns
CSB-SCL Time
tCSS
20
ns
CSB Hold Time
tCSH
40
ns
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
SCL
RS
SI
CSB, CS2
• 51
EM62100
65 COM/132 SEG STN LCD Driver
10.4 Reset Timing
tRW
RESB
tR
Internal
Status
Reset
Complete
During Reset
VDD = 2.7~3.6V , Ta = -40~+85°C
Item
Symbol
Reset Time
tR
Reset Low Pulse Width
tRW
Condition
Min.
Typ.
Max.
Unit
Pin Used
1
s
-
s
RESB
10
10.5 Display Control Timing
CK
(Out)
tDM
M
VDD = 2.7~3.6V , Ta = -40~+85°C
Item
M Delay Time
52 •
Symbol
Condition
tDM
CL=50pF
Min.
Typ.
Max.
Unit
Pin Used
20
80
ns
M
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
EM62100
65 COM/132 SEG STN LCD Driver
10.6 Application Circuit
The MPU Interface (Reference Example)
The EM62100 can be connected to either 80-Series MPU or 68-Series MPU. Using the
serial interface makes it possible to operate the EM62100 series chips with fewer signal
lines. The display area can be enlarged by integrating several EM62100 Series chips,
after which, the chip select signal can be used to select the individual ICs to access.
10.6.1 8080-Series MPU
VDD
VCC RS
A1-A7
/IORQ
RS VCC
Decoder
MPU D0-D7
CS1B,CS2
D0-D7 EM62100
RDB
WRB
RDB
WRB
RESB
GND
RESB
M86
P/S
/Reset
Fig. 12
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)
• 53
EM62100
65 COM/132 SEG STN LCD Driver
10.6.2 6800-Series MPU
VDD
VCC RS
A1-A15
VMA
RS VCC
CS1B,CS2
Decoder
D0-D7 EM62100
MPU D0-D7
E
RW
E
RW
RESB
GND
RESB
M86
P/S
/Reset
Fig. 13
10.6.3 Using the Serial Interface
V DD
VCC RS
A1-A7
RS VCC
Decoder
CS1B,CS2
MPU
EM62100
Port 1
Port 2
SI
SCL
RESB
GND
RESB
M86
P/S
VSS or
VCC
/Reset
Fig. 14
54 •
Product Specification (V1.1) 09.13.2005
(This specification is subject to change without further notice)