Elan Microelectronics Crop.
EPL43102
43 COM / 102 SEG LCD DRIVER
September 7, 2001
Version 1.1
Version
0.1
0.2
0.3
0.4
0.5
1.1
EPL43102 Specification Revision History
Content
Initial version
Add 1/3 , 1/3.5 bias
1.Add one more one VDD and VSS pad
2.Modify Pad sequence and configuration
1.Modify DC and AC characteristics
1.Add pin configuration
2.Add program example
3.Modify DC characteristics
Modify operating temperature range –30 to 80 OC
Date
November 20,2000
February 15,2001
March
2,2001
July 17,2001
July 25,2001
September 7, 2001
Contents
GENERAL DESCRIPTION ..........................................................................................................1
FEATURES.....................................................................................................................................1
APPLICATIONS.............................................................................................................................2
PIN ASSIGNMENT........................................................................................................................2
PIN DIMENSIONS ......................................................................................................................2
PAD COORDINATES ........................................................................................................................3
BLOCK DIAGRAM........................................................................................................................5
PIN DESCRIPTION .......................................................................................................................6
POWER SUPPLY.........................................................................................................................6
LCD DRIVER SUPPLY...............................................................................................................6
SYSTEM CONTROL ..................................................................................................................7
MPU INTERFACE.......................................................................................................................8
LCD DRIVER OUTPUT .............................................................................................................9
FUNCTION DESCRIPTION .......................................................................................................10
SYSTEM INTERFACE..............................................................................................................10
DISPLAY DATA RAM ..............................................................................................................13
LCD DRIVER CIRCUITS .........................................................................................................18
INTERNAL POWER CIRCUITS ..............................................................................................23
LCD DISPLAY CIRCUITS........................................................................................................28
THE RESET CIRCUIT ..............................................................................................................30
INSTRUCTION DESCRIPTION ................................................................................................31
READ DISPLAY DATA ..................................................................................................................32
WRITE DISPLAY DATA ................................................................................................................32
READ STATUS ..............................................................................................................................33
SET DUTY RATIO (TWO-BYTE INSTRUCTION) ............................................................................33
SET DISPLAY CLOCK CL FREQUENCY (TWO-BYTE INSTRUCTION) .............................................34
SELECT LCD BIAS (TWO-BYTE INSTRUCTION)..........................................................................35
DISPLAY ON/OFF .......................................................................................................................35
INITIAL DISPLAY LINE.................................................................................................................35
ELECTRONIC CONTRAST CONTROL SET (TWO-BYTE INSTRUCTION) .........................................36
SET PAGE ADDRESS ....................................................................................................................36
SET COLUMN ADDRESS ..............................................................................................................37
ADC SELECT ..............................................................................................................................37
INVERSE DISPLAY ON/OFF ........................................................................................................37
ENTIRE DISPLAY ON/OFF ..........................................................................................................38
SET MODIFY-READ ......................................................................................................................38
RESET MODIFY-READ .................................................................................................................38
RESET..........................................................................................................................................38
SHL SELECT ...............................................................................................................................39
POWER CONTROL .......................................................................................................................39
REGULATOR RESISTOR SELECT ..................................................................................................39
SET STATIC INDICATOR STATUS (TWO-BYTE INSTRUCTION) ......................................................40
POWER SAVE (COMPOUND INSTRUCTION) ..................................................................................40
APPLICATION INFORMATION ..............................................................................................42
INSTRUCTION PROCEDURE EXAMPLES...........................................................................42
PROGRAM EXAMPLES ..........................................................................................................44
ELECTRICAL CHARACTERISTICS ......................................................................................48
ABSOLUTE MAXIMUM RATINGS .................................................................................................48
RECOMMENDED OPERATING CONDITIONS .................................................................................48
DC CHARACTERISTICS ...............................................................................................................49
AC CHARACTERISTICS ...............................................................................................................51
PIN CONFIGURATION..............................................................................................................54
INPUT PIN CONFIGURATION................................................................................................54
INPUT/OUTPUT PIN CONFIGURATION...............................................................................54
OUTPUT PIN CONFIGURATION............................................................................................55
RESET INPUT PIN CONFIGURATION ..................................................................................55
LCD OUTPUT PIN CONFIGURATION...................................................................................56
MPU INTERFACE.......................................................................................................................57
APPLICATION CIRCUITS........................................................................................................59
43 COM / 102 SEG LCD DRIVER
GENERAL DESCRIPTION
The EPL43102 is a driver and controller LSI for graphic dot-matrix liquid crystal display
systems. It can be interfaced to the MPU via serial or 8-bit interface. It contains 43
common and 102 segment driver circuits. With one chip, it is possible to drive a graphic
display system with a maximum of 102 x 43 dots.
FEATURES
1. Direct Correspondence between Display Data RAM and LCD Pixel
2. Display Data RAM : 102 x 43 = 4386 bits
3. 145 LCD Drivers : 102-seg segment drivers, 42-common drivers and 1-icon
4. Serial Interface (SPI) or 8-Bit Parallel Interface Mode (80-series , 68-series MPU)
5. On-chip oscillator circuit
6. Multi-chip operation (Master, Slave) available
7. Programmable Duty Ratio :
Duty ratio
1: 42 (+ ICON)
1: 36 (+ ICON)
1: 32 (+ ICON)
1: 24 (+ ICON)
1: 16 (+ ICON)
1: 8 (+ ICON)
Common
42 (+ ICON)
36 (+ ICON)
32 (+ ICON)
24 (+ ICON)
16 (+ ICON)
8 (+ ICON)
Segment
102
102
102
102
102
102
NOTE: ICON: “1” Æ ICON pin enable;“0” Æ ICON pin disable
8. Selectable LCD driving bias level : 1/3,1/3.5,1/4,1/4.5,1/5,1/5.5,1/6,1/6.5,1/7,1/7.5,1/8
bias
9. Selectable LCD display clock frequency
10.
Electronic contrast control functions (64 steps)
11.
Built-in useful Instruction Set : Display data read/write, Display on/off, Inverse
display, Page address set, Common address set, LCD display contrast control, Set
Sleep mode, Standby mode….
12.
Operating Voltage range :
Supply voltage : 2.2 to 5.5 V
LCD driving voltage : 4.0 to 15.0 V
1
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
APPLICATIONS
Organizer
Electronic Dictionary
Scientific calculator
Cellular phone
Graphic pager
Handy Terminals (PDA)
.
.
PIN ASSIGNMENT
188
95
180
170
10
160
20
150
30
140
40
130
50
120
60
110
70
100
80
1
90
94
PIN DIMENSIONS
Pad Size A : 85X150 μm2 (Pad 1 to 15 and 80 to 94; Pad 95 to 109 and 174 to188)
Pad Size B : 75X150 (Pad 16 to 79; Pad 110 to 173)
Pad Pitch A: 95 μm
Pad Pitch B: 85 μm
The information in this document is subject to change without notice.
2
43 COM / 102 SEG LCD DRIVER
Pad coordinates
PAD NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
3
Symbol
X
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COMI1
VDD
VDD
C1+
C1C3
C4
C2C2+
VOUT
V0
V1
V2
V3
V4
VR
GND
GND
MS
PS
FR
C86
/DOF
CLS
CL
OSC
FRS
IRS
/RES
-4095.0
-4000.0
-3905.0
-3810.0
-3715.0
-3620.0
-3525.0
-3430.0
-3335.0
-3240.0
-3145.0
-3050.0
-2955.0
-2860.0
-2765.0
-2675.0
-2590.0
-2505.0
-2420.0
-2335.0
-2250.0
-2165.0
-2080.0
-1995.0
-1910.0
-1825.0
-1740.0
-1655.0
-1570.0
-1485.0
-1400.0
-1315.0
-1230.0
-1145.0
-1060.0
-975.0
-890.0
-805.0
-720.0
-635.0
-550.0
-465.0
-380.0
-295.0
-210.0
-125.0
-40.0
45.0
130.0
215.0
Y
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
PAD NO.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
D7
D6
D5
D4
D3
D2
D1
D0
CS2
/CS1
A0
/WR
/RD
TEST
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMI2
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
X
300.0
385.0
470.0
555.0
640.0
725.0
810.0
895.0
980.0
1065.0
1150.0
1235.0
1320.0
1405.0
1490.0
1575.0
1660.0
1745.0
1830.0
1915.0
2000.0
2085.0
2170.0
2255.0
2340.0
2425.0
2510.0
2595.0
2680.0
2770.0
2865.0
2960.0
3055.0
3150.0
3245.0
3340.0
3435.0
3530.0
3625.0
3720.0
3815.0
3910.0
4005.0
4100.0
4100.0
4005.0
3910.0
3815.0
3720.0
3625.0
The information in this document is subject to change without notice.
Y
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
-742.5
742.5
742.5
742.5
742.5
742.5
742.5
43 COM / 102 SEG LCD DRIVER
PAD NO.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
X
3530.0
3435.0
3340.0
3245.0
3150.0
3055.0
2960.0
2865.0
2770.0
2680.0
2595.0
2510.0
2425.0
2340.0
2255.0
2170.0
2085.0
2000.0
1915.0
1830.0
1745.0
1660.0
1575.0
1490.0
1405.0
1320.0
1235.0
1150.0
1065.0
980.0
895.0
810.0
725.0
640.0
555.0
470.0
385.0
300.0
215.0
130.0
45.0
-40.0
-125.0
-210.0
-295.0
-380.0
-465.0
-550.0
-635.0
-720.0
Y
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
PAD NO.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Symbol
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
X
-805.0
-890.0
-975.0
-1060.0
-1145.0
-1230.0
-1315.0
-1400.0
-1485.0
-1570.0
-1655.0
-1740.0
-1825.0
-1910.0
-1995.0
-2080.0
-2165.0
-2250.0
-2335.0
-2420.0
-2505.0
-2590.0
-2675.0
-2765.0
-2860.0
-2955.0
-3050.0
-3145.0
-3240.0
-3335.0
-3430.0
-3525.0
-3620.0
-3715.0
-3810.0
-3905.0
-4000.0
-4095.0
Y
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
742.5
Note: For PCB layout, IC substrate must be connected to VSS or floating.
The information in this document is subject to change without notice.
4
43 COM / 102 SEG LCD DRIVER
BLOCK DIAGRAM
SEG0
V0
V1
V2
V3
V4
VSS
COM41 COMI
SEG101 COM0
SEGMENT DRIVER
CIRCUITS
COMMON DRIVER
CIRCUITS
LATCH CIRCUIT
SHIFT REGISTER
Voltage
Converter
DISPLAY DATA RAM
INITIAL DISPLAY LINE
REGISTER
Connect the
capacitor
LINE COUNTER
VOUT
LINE ADDRESS
DECODE
Voltage
Regulator
LOW ADDRESS
DECODER
VR
PAGE ADDRESS
REGISTER
Voltage
Followers
COLUMN ADDRESS
DECODER
FR
Display
Timing
Generator
Circuit
COLUMN ADDRESS
COUNTER
COLUMN ADDRESS
REGISTER
CL
/DOF
FRS
M/S
INSTRUCTION
DECODER
Oscillator
Bus holder
INSTRUCTION
REGISTER
STATUS
REGISTER
I/O Buffer
( Serial / Parallel )
MPU Interface
IRS /CS1CS2 A0 /RD /WR C86 P/S /RES D7 D6 D5 D4 D3 D2 D1 D0
(E) (R/W)
(SDI)(SCK)(SDO)
Figure 1
5
The information in this document is subject to change without notice.
CLS
OSC
43 COM / 102 SEG LCD DRIVER
PIN DESCRIPTION
POWER SUPPLY
Name
I/O
VDD
VSS
V0
V1
V2
V3
V4
Power
Power
Power
Description
VDD Power Supply
0V (GND)
LCD driver supply voltages. The voltage determined by LCD pixel is
impedance-converted by an operational amplifier (OPA) for
application. Voltages have the following relationship:
V0 ≧V1≧V2≧V3≧V4≧VSS
When the internal power circuit is active, these voltages are
generated according to the state of LCD bias, The selection of
voltages is determined by the “LCD bias select” instruction, as
shown in the table below.
LCD Bias
1/8 Bias
1/7.5 Bias
1/7 Bias
1/6.5 Bias
1/6 Bias
1/5.5 Bias
1/5 Bias
1/4.5 Bias
1/4 Bias
1/3.5 Bias
1/3 Bias
V1
(7/8)XV0
(6.5/7.5)XV0
(6/7)XV0
(5.5/6.5)XV0
(5/6)XV0
(4.5/5.5)XV0
(4/5)XV0
(3.5/4.5)XV0
(3/4)XV0
(2.5/3.5) XV0
(2/3)XV0
V2
(6/8)XV0
(5.5/7.5)XV0
(5/7)XV0
(4.5/6.5)XV0
(4/6)XV0
(3.5/5.5)XV0
(3/5)XV0
(2.5/4.5)XV0
(2/4)XV0
(1.5/3.5)XV0
(1/3)XV0
V3
(2/8)XV0
(2/7.5)XV0
(2/7)XV0
(2/6.5)XV0
(2/6)XV0
(2/5.5)XV0
(2/5)XV0
(2/4.5)XV0
(2/4)XV0
(2/3.5)XV0
(2/3)XV0
V4
(1/8)XV0
(1/7.5)XV0
(1/7)XV0
(1/6.5)XV0
(1/6)XV0
(1/5.5)XV0
(1/5)XV0
(1/4.5)XV0
(1/4)XV0
(1/3.5)XV0
(1/3)XV0
LCD DRIVER SUPPLY
Name
C1+
C1C2+
C2C3
C4
VOUT
VR
I/O
O
Description
Boosted capacitor connecting terminals used for voltage booster.
O
Boosted capacitor connecting terminals used for voltage booster.
O
Boosted capacitor connecting terminals used for voltage booster.
I/O
I
Voltage converter output
V0 voltage adjustment pin.
The information in this document is subject to change without notice.
6
43 COM / 102 SEG LCD DRIVER
SYSTEM CONTROL
Name
M/S
I/O
I
Description
Master/slave operation select pin.
- MS = "H": Master operation
- MS = "L": Slave operation
M/S CLS
“H”
“H”
“L”
*
“L”
OSC.
Power
CL FR FRS /DOF
supply
circuit
Available
Available
O O
O
O
Unavailable Available
O O
O
O
Unavailable Unavailable I
I Hi-Z
I
NOTE: * : Don’t Care
O : Output
I : Input
P/S
I
FR
I/O
C68
I
/DOF
I/O
Select Interface mode with the MPU.
When PS = "High": Parallel interface mode.
When PS = "Low": Serial interface mode.
LCD AC signal input/output pin.
When is used in master/slave mode (multi-chip), the FR pins must
be connected each other.
- MS = “H”: Output
- MS = “L”: Input
Select the kinds of the MPU to interface.
When C68 = "High": 68-series MPU interface mode
When C68 = "Low": 80-series MPU interface
LCD Display blanking control pin. In multi-chip mode, the /DOF pin
must be connected to each other.
M/S = ”H” (Master) : /DOF is output pin.
ÆDisplay “On” = “H”, Display “Off” = “L”
M/S = ”L” (Slave) : /DOF is input pin.
ÆVia external control. Refer to the following table.
Instruction
Display “On”
Display “Off”
CLS
CL
7
I
I/O
/DOF
H
On
Off
L
Off
Off
Internal oscillator circuit enable / disable select pin.
CLS = “H”: Internal oscillator circuit is enable
CLS = “L”: Internal oscillator circuit is disable
(External display clock input to OSC pin)
Display clock input/output pin.
When the EPL43102 is used in master/slave mode (multi-chip), the
CL pins must be connected each other.
M/S
“H”
CL
Output
“L”
Input
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
OSC
I
FRS
O
IRS
I
When using an external oscillator, input the clock to OSC pin.
When using an internal oscillator, leave this pin open.
Static driver output pin.
This pin is used in combination with the FR pin.
Internal resistor select pin.
This pin selects the resistors for adjusting V0 voltage level and is
available only in master mode.
- IRS = "H": The internal resistors are used.
- IRS = "L": The external resistors are used. V0 voltage is controlled
using the external divider resistor connect the VR pin.
MPU INTERFACE
Name
/RES
I/O
I
/CS1,CS2
I
Description
Hardware reset input.
The LSI is reset when this signal is pulled low. (Active low)
These are the chip select signals. The Chip Select of the LSI
becomes active when CS1 is "L" and also CS2 is "H" and allows the
input/output of data or commands.
/CS1
“L”
“L”
“H”
“H”
A0
I
/WR (R/W)
I
/RD (E)
I
D0 to D7
I/O
CS2
“L”
“H”
“L”
“H”
Status
The device is not active. (D7~D0 is Hi-Z)
Data and instruction are available.
The device is not active. (D7~D0 is Hi-Z)
The device is not active. (D7~D0 is Hi-Z)
Used as register selection input.
When A0 = "High", Data register.
When A0 = "Low", Instruction register.
When C68 = "High"(68-series MPU interfacing), used as
read (/WR = "High"),write (/WR = "Low")
When C68 = "Low "(80-series MPU interfacing), used as write
enable input (/WR).
When C68 = "High"(68-series MPU interfacing), used as read/write
enable input (E).
When C68 = "Low "(80-series MPU interfacing), used as read enable
input (/RD).
When serial mode, D6 (SCK) is used as serial clock input pin, D7
(SDI) is used as serial data input pin, D5 (SDO) is used as serial
data output pin and the others are not used.
When parallel mode, D0 to D7 are used as bi-directional data bus
pin.
The information in this document is subject to change without notice.
8
43 COM / 102 SEG LCD DRIVER
LCD DRIVER OUTPUT
Name
COM0 to
COM41
I/O
O
Description
The LCD common output pins.
Scan Data
FR
H
L
L
H
L
Power Save Mode
H
COMI
O
SEG0 to
SEG101
O
These are two icon display pins. Both pins output the same signal.
Leave these pins open when they are not used.
The LCD segment output pins.
Display Data
H
FR
H
L
L
H
L
Power Save Mode
9
COMs Output Voltage
Vss
V0
V1
V4
Vss
SEGs Output Voltage
Normal Display Reverse Display
V0
V2
Vss
V3
V2
V0
V3
Vss
Vss
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
FUNCTION DESCRIPTION
SYSTEM INTERFACE
INSTRUCTION
DECODER
INSTRUCTION
REGISTER
Bus holder
STATUS
REGISTER
I/O Buffer
( Serial/Parallel )
MPU Interface
D7 D6 D5 D4 D3 D2 D1 D0 BUSY
/CS1 CS2 A0 /RD /WR C86 P/S /RES
(E) (R/W)
(SDI)(SCK)(SDO)
Figure 2
MPU interface
The EPL43102 has two chip select pin /CS1 and CS2. In case of /CS1="L" and CS2=”H”,
the interface with MPU is available. When the chip select pin is inactive (Other /CS1 and
CS2 condition), D7 to D0 are high impedance (invalid) and input of A0, /RD, or /WR
inputs are not effective. If the serial interface has been selected, the shift register and
counter are both reset.
However, the reset is always operated in any conditions of /CS1 and CS2.
P/S
Serial
Mode
(L)
Parallel
mode
(H)
C68
SPI interface
(-)
A0
A0
/WR /RD
R/W
-
D0~D4 D5
D6
*
SDO SCK
80-series (L)
A0
/WR /RD
D0~D7
68-series (H)
A0
R/W
D0~D7
E
D7
SDI
NOTE: * : Don’ t care ("High", "Low" or "Open")
- : Fixed “ High” (VDD) or “ Low” (VSS)
The EPL43102 can be operated with serial interface (SPI) and parallel interface
(80-series or 68-series) is selected by P/S pin.
The information in this document is subject to change without notice.
10
43 COM / 102 SEG LCD DRIVER
1. Serial mode (SPI): When serial mode (PS = "L"), D6 (SCK) is used as serial clock
input pin, D7 (SDI) is used as serial data input pin, D5 (SDO) is used as serial data
output pin. When the LSI is active (/CS1=”L”, CS2=”H”), serial data input (D7), serial
clock input (D6) inputs and serial data output (D5) are enabled. The 8-bit shift
register and 3-bit counter are reset to the initial condition when the chip is not
selected. The data input/output from SDI/SDO terminal is MSB first like as the order
of D7, D6…D0, and is latched at the rising edge of the serial clock SCK. Serial input
data is display data when A0="H" and instruction when is A0="L". The A0 input is
read in and identified at the rising edge of the (8 x n) serial clock pulse. Since the
clock signal (D6) is easy to be affected by the external noise caused by the line
length, the operation check on the actual machine is recommended.
/CS1
CS2
SCK
(D6)
SDI
(D7)
D7
SDO
(D5)
D6
D7
D5
D6
D4
D5
D3
D4
D2
D3
D1
D2
D0
D1
D7
D0
D7
A0
Figure 3
A0
0
0
1
1
11
/WR (R/W)
0
1
0
1
D7 (SDI)
Instruction Write
Invalid
Display Data Write
Invalid
D5 (SDO)
Status Read
Status Read
Status Read
Display Data Read
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
2.
Parallel mode (8-bit length): When the parallel input is selected (PS = ”H”), D0~D7
can be connected directly to the 80-series or 68-series MPU by setting the C86 pin
to high or low.
A0
/RD
/WR
D7~D0
N
D(N)
D(N+1)
D(N+2)
D(N+3)
D(N+4)
D(N+2)
D(N+3)
Writing Timing
A0
/RD
/WR
D7~D0
N
Dummy
D(N)
D(N+1)
Reading Timing
Figure 4
Common
A0
H
H
L
L
80-series
/RD
/WR
L
H
H
L
L
H
H
L
68-series
R/W
H
L
H
L
Description
Display data read
Display data write
Register status read
Writes to Instruction register
DATA TRANSFER
The EPL43102 uses a bus holder and an internal data bus for data transfer with MPU.
When writing data from the MPU to the DDRAM, data is automatically transferred from
the bus holder to the DDRAM. When reading data from the DDRAM to MPU, the data for
the initial read cycle is stored in the bus holder (dummy read) and MPU reads this stored
data from bus holder for the next data read cycle.
The information in this document is subject to change without notice.
12
43 COM / 102 SEG LCD DRIVER
REGISTER
INITIAL DISPLAY LINE
LINE COUNTER
DISPLAY DATA RAM
LINE ADDRESS DECODE
LOW ADDRESS DECODER
PAGE ADDRESS REGISTER
DISPLAY DATA RAM
COLUMN ADDRESS DECODER
COLUMN ADDRESS COUNTER
COLUMN ADDRESS REGISTER
Figure 5
The display data RAM (DDRAM) stores pixel data for the LCD. It is a 43-row x
102-column addressable array. It is possible to access any required bit by specifying the
page address and the column address. The 43 rows are divided into 5 pages of 8 lines, 1
page with 2 line (D0,D1) and the seventh page with a single line (D0 only).
The each bit in the Display Data RAM corresponds to the each pixel of the LCD each
pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel
of the LCD panel and controls the display by following bit data.
When Normal Display : On="1" , Off="0"
When Inverse Display : On="0" , Off="1"
(Refer to “Inverse Display ON/OFF” instruction for more detail.)
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
DISPLAY DATA RAM
NORMAL DISPLAY
INVERSE DISPLAY
Figure 6
13
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
The microprocessor (MPU) can read from and write to RAM through the I/O buffer. Since
the LCD controller operates independently, data can be written into RAM at the same
time as data is being displayed without causing the LCD flicker.
Page Address Data
P3,P2,P1,P0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Column Address
PAGE0
PAGE1
PAGE2
PAGE3
PAGE4
PAGE5
Line
Common Common Common Common
Address Output
Output
Output
Output
(HEX)
(1/42,1/43) (1/36,1/37) (1/32,1/33) (1/16,1/17)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
COM36
COM37
COM38
COM39
COM40
COM41
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
The information in this document is subject to change without notice.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
14
43 COM / 102 SEG LCD DRIVER
0 1 1 0
Column
Address(HEX)
LCD Output
D1
D0
ADC
=0
ADC
=1
29
0
0
6
5
S
E
G
0
0
1
6
4
S
E
G
1
PAGE6
0 --------- 6
2
2
6 --------- 0
3
3
S --------- S
E
E
G
G
9
2
8
6
3
0
2
S
E
G
9
9
6
4
0
1
S
E
G
1
0
0
COM35 COM35
COMI
COMI
COMI
COMI
6
5
0
0
S
E
G
1
0
1
NOTE: For example the initial display line address is 06H.
Programmable Duty Ratio
The duty ratio is selected by “Set Duty Ratio” instruction.
The common output circuits have showed as following figure 7. They are separated into
three shift registers and control by "duty ratio register".
15
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
The common output circuits have showed as following figure. They are separated into
three shift registers and control by "duty ratio register".
COM0
COM20
COM21
COM41
COMI
COMMON DRIVER (21)
COMMON DRIVER (21)
COMMON
DRIVER (1)
21-bit SHIFT REGISTER
21-bit SHIFT REGISTER
1-bit SHIFT
REGISTER
4
DUTY RATIO
REGISTER
Figure 7
Duty
SHL
1/43
1/42
1/37
1/36
1/33
1/32
1/25
1/24
1/17
1/16
1/9
1/8
0
1
0
1
0
1
0
1
0
1
0
1
Common Output Pins
0
1
2
COM[0..17]
COM[35..18]
COM[0..15]
COM[31..16]
COM[0..11]
COM[23..12]
COM[0..7]
COM[15..8]
COM[0..3]
COM[7..4]
……………………….
COM[0..41]
COM[41..0]
39 40 41
COM[18..35]
COM[17..0]
COM[16..31]
COM[15..0]
COM[12..23]
COM[11..0]
COM[8..15]
COM[7..0]
COM[4..7]
COM[3..0]
COMI
COMI
−
COMI
−
COMI
−
COMI
−
COMI
−
COMI
−
The Relationship between Duty Ratio and Common Output
The information in this document is subject to change without notice.
16
43 COM / 102 SEG LCD DRIVER
Initial display line register
The initial display line register assigns a DDRAM line address which corresponds to
COM0 by “Initial display line set” instruction. It is used for not only normal display but
also vertical display scrolling and page switching without changing the contents of the
DDRAM. However, the 43th address for icon display can’t be assigned for initial display
line address.
Line counter
The line counter provides a DDRAM line address. It initializes its contents at the
switching of frame reversal signal (FR), and also counts-up in synchronization with
common timing signal.
Column address counter
The column address counter is an 8-bit preset counter which provides a DDRAM column
address, and it is independent of below-mentioned page address register.
It will increment (+1) the column address whenever “display data read” or “display data
write” instructions are issued. However, the incrementing of column address is stopped
at column address of 65H. The count-lock will be able to be released by the “column
address set” instruction again. The counter can invert the correspondence between the
column address and segment driver direction by means of “ADC select” instruction.
Page address register
The page address register provides a DDRAM page address. The page address 6 is
used for icon display, and only D0 is valid.
17
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
LCD DRIVER CIRCUITS
COM0
V0
V1
V2
V3
V4
VSS
COM41 COMI SEG0
SEG101
COMMON
DRIVER
CIRCUITS
SEGMENT DRIVER
CIRCUITS
SHIFT
REGISTER
LATCH CIRCUIT
Display
Timing
Generator
Circuit
FROM DISPLAY DATA
RAM
Figure 8
This driver circuit is configured by 42-common drivers, 102-segment drivers and
1-icon-common driver. This LCD panel driver voltage depends on the combination of
display data and FR signal.
Display data latch circuit
The display data latch circuit is a latch that temporarily stores the display data that is
output to the liquid crystal driver circuit from the display data RAM.
“Display on/off”, “Inverse display on/off” and “Entire display on/off” instructions control
only the contents of this latch circuit, they can’t change the contents of the DDRAM.
Shift register circuit
The circuit contains a 42-bit shift register to shift the turn-on data required for the LCD
drive common signals and 1-bit shift register used for icon. The clock of this shift register
is generated by display clock CL.
The information in this document is subject to change without notice.
18
43 COM / 102 SEG LCD DRIVER
Examples of 1/33 and 1/43 duty (ICON enable) driving waveform
1/33 Duty
0
1
2
3
32 0
1
2
31 32 0
1
1/43 Duty
0
1
2
3
42 0
1
2
41 42 0
1
CL
FR
COM0
COM1
COM31
(COM41)
COMI
Figure 9
19
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
Examples of 1/32 and 1/42 duty (ICON disable) driving waveform
1/32 Duty
0
1
2
3
31 0
1
2
30 31 0
1
1/42 Duty
0
1
2
3
41 0
1
2
40 41 0
1
CL
FR
COM0
COM1
COM30
(COM40)
COM30
(COM41)
Figure 10
The information in this document is subject to change without notice.
20
43 COM / 102 SEG LCD DRIVER
Common driver circuit
Common driver circuit consists of 43 drive circuits. One of the four LCD driving level is
selected by the combination of FR and the data from the sift register.
V0
VCON
VSS
COM0~41,COMI
Shift Data
V4
VCOFF
V1
Scan
Data
FR
H
H
L
H
L
L
FR
Power save mode
COMs Output
Voltage
VSS
V0
V1
V4
VSS
Figure 11
Segment driver circuit
Segment driver circuit consists of 102 driver circuits. One the four LCD driving level is
selected by the combination of FR and the display data transferred from the latch circuit.
VSS
VSON
V0
SEG0~101
Display Data
Display
Data
FR
SEGs Output
Voltage
V3
VSOFF
V2
FR
Normal Inverse
Display Display
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
V3
VSS
VSS
Power save mode
Figure 12
21
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
LCD Driving Waveform
The following illustration is an example of how the common and segment drivers to a
LCD panel.
SEG0
CL
COM0
COM1
FR
V0
V1
COM0
V4
VSS
V0
V1
COM1
V4
VSS
V0
V2
SEG0
V3
VSS
V0
SEG0-COM0
-V0
Figure 13
The information in this document is subject to change without notice.
22
43 COM / 102 SEG LCD DRIVER
INTERNAL POWER CIRCUITS
LCD Driving Voltage
Supply
Voltage
Followers
Voltage
Regulator
VR
IRS
VOUT
Voltage
Converter
Connect the capacitor
Internal Power Circuits
Figure 14
The internal power supply circuits generate the voltage levels necessary to drive liquid
crystal driver circuits with low-power consumption and the fewest components. There are
voltage converter (V/C) circuits, voltage regulator (V/R) circuits, and voltage follower (V/F)
circuits. They are valid only in master operation and controlled by “Power Control”
instruction. For details, refers to "Instruction Description".
User Setup
Only the internal
power supply
circuits are used
Only the voltage
Regulator circuits
and voltage
follower circuits are
used
Only the voltage
follower circuits are
used
Only the external
power supply
circuits are used
23
V/C
Power
Circuits
control
(VC VR VF)
V/R
circuits
V/F
Circuits
VOUT
V0
V1 to V4
111
On
On
On
Open
Open
Open
011
Off
On
On
External
input
Open
Open
001
Off
Off
On
Open
External
input
Open
000
Off
Off
Off
Open
External
input
External
input
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
Voltage converter circuits
These circuits boost up the electric potential between VDD and VSS to 2, 3, 4, or 5 times
toward positive side and boosted voltage is outputted from VOUT pin. The boosting
magnitude of internal booster circuit is selected by the capacitor connection (Refer
Figure 15). The internal oscillator is required to be operating when using this converter,
because the divided signal provided from the oscillator is used for the internal timing of
this circuit.
C1+
C1+
C1+
C1+
C1-
C1-
C1-
C1-
OPEN
C3
C3
C3
C3
OPEN
C4
C4
C4
C4
OPEN
C2-
C2-
C2-
C2-
C2+
C2+
C2+
C2+
VOUT
VOUT
VOUT
VOUT
2X
3X
4X
5X
OPEN
Boost Capacitors = 1 uF~4.7 uF
Figure 15
Voltage regulator circuits
The voltage regulator determines the LCD driving voltage V0, by adjusting resistors, Ra
and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits, it is necessary to be applied internally or externally. For the
Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or
externally by IRS pin. And VEV called the voltage of electronic volume is determined by
Eq. 2, where the parameter α is the value selected by instruction, "Set Contrast Control
Mode", within the range 0 to 63.
VREF, a constant voltage source is 2 V at TA=25oC.
The information in this document is subject to change without notice.
24
43 COM / 102 SEG LCD DRIVER
VOUT
V0
Rb
VEV
VR
(Constant reference voltage
+ electronic volume)
Ra
VSS
Figure 16
V 0 = (1 +
Rb
) × VEV …………………Eq.1
Ra
VEV = (1 −
(63 − α )
) × VREF ……….Eq.2
252
Register value
(R2 R1 R0)
000
001
010
011
100
101
110
111
1+(Rb/Ra)
Value
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Small
.
.
.
.
.
.
Large
(Refer to “Regulator Resistor Select” instruction for detail.)
α
0
1
..
..
62
63
D5
0
0
.
.
1
1
D4
0
0
.
.
1
1
D3
0
0
.
.
1
1
D2
0
0
.
.
1
1
D1
0
0
.
.
1
1
D0
0
1
.
.
0
1
(Refer to “Set Contrast Control Mode” instruction for detail.)
25
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
In case of using internal resistors, Ra and Rb. (IRS = "H")
When IRS pin is “ H” , resistor Ra is connected internally between VR pin and VSS, and
Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator
Resistor Select" and "Set Reference Voltage".
In case of using external resistors, Ra and Rb. ( IRS = "L" )
When IRS pin is “ L” , it is necessary to connect external regulator resistor Ra between
VR and VSS, and Rb between V0 and VR.
For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate.
For duty ratio is 1/43, the optimum operating voltage of the liquid can be calculated as:
VLCD =
1 + 43
1
2 × 1 −
43
× Vth = 5.805 × Vth
where Vth is the threshold voltage of the liquid crystal material used.
Voltage follower circuits
FROM VOLTAGE
REGULATOR
V0
V1
0.890xV0
V2
0.880xV0
Total Req = 4M
Switching
Network
0.120xV0
V3
0.110xV0
V4
BYPASS CAPACITOR = 0.47uF~1uF
OP TYPE VOLTAGE FOLLOWER
Figure 17
The information in this document is subject to change without notice.
26
43 COM / 102 SEG LCD DRIVER
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3, V4), and
those output impedance are converted by the voltage follower (OPA) for increasing drive
capability. Total 6 levels LCD reference voltage ( V0,V1,V2,V3,V4,VSS ) is generated by
the voltage follower circuits.
LCD Bias
1/8
1/7.5
1/7
1/6.5
1/6
1/5.5
1/5
1/4.5
1/4
1/3.5
1/3
V1
0.875*V0
0.865*V0
0.855*V0
0.845*V0
0.835*V0
0.820*V0
0.800*V0
0.780*V0
0.750*V0
0.715*V0
0.665*V0
V2
0.750*V0
0.735*V0
0.715*V0
0.690*V0
0.665*V0
0.635*V0
0.600*V0
0.555*V0
0.500*V0
0.430*V0
0.335*V0
V3
0.250*V0
0.265*V0
0.285*V0
0.310*V0
0.335*V0
0.365*V0
0.400*V0
0.445*V0
0.500*V0
0.570*V0
0.665*V0
V4
0.125*V0
0.135*V0
0.145*V0
0.155*V0
0.165*V0
0.180*V0
0.200*V0
0.220*V0
0.250*V0
0.285*V0
0.335*V0
Different duty radio requires different bias level. For optimum bias level, BL can be
calculated from:
BL =
1
Duty ratio + 1
Changing the bias system from the optimum will have a consequence on the contrast
and viewing angle.
The LCD Bias affects the display quality. But for reducing the current consumption, the
unsuitable bias may be selected. Therefore, the LCD Bias could be selected by “Select
LCD bias” instruction.
27
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
LCD DISPLAY CIRCUITS
FR
CL
Display
Timing
Generator
Circuit
/DOF
FRS
M/S
CLS
Oscillator
OSC
Figure 18
Oscillator
This is a completely on-chip oscillator and its frequency is nearly independent of VDD.
This is the low power consumption RC type oscillator which provides the display clock
and voltage converter timing clock.
When “M/S=”H” and “CLS”=”H”, the oscillator circuit is enable. When CLS=”L”, the
oscillator is stop, and the oscillator clock has to be input to the OSC pin.
The oscillator circuit is available in master mode only. The oscillator signal is divided and
output as display clock at CL pin.
RC Oscillator
CLS
To internal circuit
OSC
Sleep mode
Figure 19
The information in this document is subject to change without notice.
28
43 COM / 102 SEG LCD DRIVER
/DOF pin description
The pin is used to control blinking LCD display.
Instruction
Display “ON”
Display “OFF”
M/S= “H”
M/S=”L”
/DOF (Output) /DOF (Input) =”H” /DOF (Input) =”L”
“H”
LCD On
LCD Off
“L”
LCD Off
LCD Off
When the “Power Save” Instruction is activating, the /DOF pin is set to low level.
Display timing generator circuit
This circuit generates some signals to be used to display LCD. When using in
master/slave mode (multi-chip), some pins must be connected each other. That’s due to
synchronization output. The display clock (CL) generated by the oscillation clock,
generates a clock to the line counter and a latch signal to the display data latch. The line
address of the on-chip RAM is generated in synchronization with the display clock (CL),
and the 102-bit display data is latched by the display data latch circuit in synchronization
with the display clock. The display data which is read to the LCD driver is completely
independent of the access to the display data RAM from the microprocessor.
The display clock generates an LCD frame reversal signal (FR) which enables the LCD
driver to make an AC drive waveform, and also generates an internal common timing
signal and start signal to the common driver.. When this EPL43102 is used for a
multi-chip, the slave chip must receive the FR, CL, /DOF signals from the master.
Operation Mode
Master
Internal oscillator is enable(CLS=”H”)
(M/S=”H”)
Internal oscillator is disable (CLS=”L”)
Slave (M/S=”L”) Internal oscillator is disable
(CLS =”L” or “H”)
FR
Output
Output
Input
Input
CL
Output
Output
Input
Input
/DOF FRS
Output Output
Output Output
Input Hi-Z
Input Hi-Z
OSC
Open
Input
Open
Open
Note: Open means “leave the pin open”
Oscillator frequency
The EPL43102 contains a RC oscillator. The frame frequency (fFM) is derived from the
RC circuit’s oscillation frequency (fOSC) by driving it an appropriate value. The
relationship between the oscillation frequency (fOSC), display clock frequency (fCL) and
the frame frequency (fFM) is shown below.
29
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
The fOSC could be selected internal or external oscillator via CLS pin, fCL could be
selected via “Set display clock CL frequency” instruction, and frame frequency could be
calculated via following equation.
fCL = (Duty ratio) x (Frame frequency)
THE RESET CIRCUIT
When the /RES input comes to the “L” level, these LSI return to the default state. Their
default states are as follows:
1. Display OFF
2. Normal display
3. ADC select: Normal (ADC select instruction D0 = “L”)
4. SHL select: Normal (SHL select instruction D3 = “L”)
5. Power control register: (D2, D1, D0) = (0, 0, 0)
6. Serial interface internal register data clear
7. Duty ratio = 1/43
8. CL frequency Register (D4, D3, D2, D1,D0) = (0, 0, 0, 0, 1, 1)
9. LCD power supply bias level = (1/8)
10. Entire display OFF (Entire display instruction D0 = “L”)
11. Power saving clear
12. Modify-Read OFF
13. Static indicator OFF
Static indicator register : (D1, D2) = (0, 0)
14. Display initial line set to first line : 0
15. Column address set to Address : 0
16. Page address set to Page : 0
17. V0 voltage regulator internal resistor ratio set mode clear: (R2, R1, R0) = (0, 0, 0)
18. Contrast control set mode clear
Contrast control register : (D5, D4, D3, D2, D1,D0) = (1, 0, 0, 0, 0, 0)
The information in this document is subject to change without notice.
30
43 COM / 102 SEG LCD DRIVER
INSTRUCTION DESCRIPTION
Instruction
A0 /RD /WR D7
Read Display Data
1
0
1
Write Display Data
1
1
0
Read Status
0
0
1
Set Duty Ratio Mode
0
1
0
1
Duty Ratio Register
0
1
0
*
Set CL frequency Mode 0
1
0
1
CL frequency Register
0
1
0
*
Set LCD Bias select
0
1
0
1
Mode
LCD Bias select
0
1
0
*
Register
Display On/Off
0
1
0
1
D6
D5
Status
0
0
*
*
0
0
*
*
0
0
D4 D3
Read Data
Write Data
0
0
0
* ICON
0
0
D4 D3
0
0
D2
D1
0
1
D2
0
D2
1
0
0
D1
1
D1
0
Description
Read data from DDRAM
Write data into DDRAM
0 Read the internal status
0 Set duty ratio Mode
D0 Select the duty ratio
0 Set CL frequency Mode
D0 Set CL frequency Register
1 Set LCD Bias select Mode
D0 Select the LCD Bias
*
*
*
D3
D2
D1
0
1
0
1
1
1
D0
0
0
1
1
0
0
0
1
1
0
D5
0
D4
0
D3
0
D2
0
Don Turn on/off LCD panel
When DON=0: display off
When DON=1: display on
D1 D0 Specify DDRAM line for COM0
0
1 Set Contrast Control Mode
0
1
0
*
*
D5
D4
D3
D2
D1
0
0
1
1
0
0
1
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
Inverse Display
ON/OFF
0
1
0
1
0
1
0
0
1
1
Entire Display ON/OFF
0
1
0
1
0
1
0
0
1
0
Set Modify-read
Reset Modify-read
Reset
SHL Select
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
*
0
1
1
*
0
0
0
*
Initial Display Line
Set Contrast Control
Mode
Set Contrast Control
Register
Set Page Address
Set Column Address
MSB
Set Column Address
LSB
ADC Select
D0 Set Contrast Control Register
Page Address
Higher order Column
Add.
Lower order column
Add.
0
0
0
ADC
REV
EON
SHL
Power Control
Regulator Resistor
Select
Set Static Indicator
Mode
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
VC
R2
VR
R1
VF
R0
0
1
0
1
0
1
0
1
1
0
SM
Set Static Indicator
Register
Power Save
0
1
0
*
*
*
*
*
*
S1
S0
-
-
-
-
-
-
-
-
-
-
-
Set page address
DDRAM column address of Higher
4-bits
DDRAM column address of lower
4-bits
Select segment direction
When ADC=0: normal direction
(SEG0 ÆSEG101)
When ADC=1: reverse direction
(SEG101ÆSEG0)
Select normal/inverse display
0 : Normal display
1 : Inverse display on
Select normal/entire display ON
When EON=0: normal display.
When EON=1: entire display ON
Set modify-read mode
Release modify-read mode
Initialize the internal functions
Select COM output direction
When SHL=0: normal direction
(COM0 -> OM41)
When SHL=1: reverse direction
(COM41 -> COM0)
Control power circuit operation
Select internal resistance ratio of
the regulator resistor
Set static indicator mode
When SM = 0: off
When SM = 1: on
Set static indicator register
Compound instruction of display
OFF and entire display ON
Note: * : Don’t care
31
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
Read Display Data
8-bit data from display data RAM specified by the column address and page address can
be read by this instruction. As the column address is increased by 1 automatically after
each this instruction, the microprocessor can continuously read data from the addressed
page.
A0
1
/RD /WR
0
D7
D6
D5
1
D4
D3
D2
D1
D0
Read Data
Write Display Data
8-bit data of display data from the microprocessor can be written to the RAM location
specified by the column address and page address. After writing the display data, the
column address is automatically incremented so that the microprocessor can
continuously write data to the addressed page.
A0
1
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write Data
The information in this document is subject to change without notice.
32
43 COM / 102 SEG LCD DRIVER
Read Status
This instruction reads out the internal status regarding “ADC select”, “Display on/off” and
“Reset”.
A0
0
/RD
0
Flag
ADC
On/Off
RESET
/WR
1
D7
-
D6
ADC
D5
D4
On/Off RESET
D3
0
D2
0
D1
0
D0
0
Description
It shows the correspondence between the column
address and segment drivers.
ADC =0 : Reverse direction (SEG101 Æ SEG0)
=1 : Normal direction (SEG0 Æ SEG101)
This bit indicates the ON/OFF state of the display.
0: Display ON 1: Display OFF
Indicates the initialization is in progress by RESETB
signal.
RESET =0 : Normal display operation state
=1 : Internal reset operation state with reset
command.
Set Duty Ratio (Two-Byte instruction)
Consists of 2-byte instruction. The first instruction sets duty ratio mode, the second one
updates the contents of duty ratio register. After second instruction, set duty mode is
released. The LSI can’t accept any instructions except the “Set duty ratio register” during
the sets duty ratio mode
Set Duty Ratio mode (First instruction)
A0
0
33
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
0
0
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
Set Duty Ratio Register (Second instruction)
A0
0
/RD /WR
1
0
D7
*
D6
*
D5
*
D4
*
D3
ICON
D2
0
0
0
0
1
1
D1
0
0
1
1
0
0
D0
0
1
0
1
0
1
Duty ratio
8 (+ICON)
16(+ICON)
24(+ICON)
32(+ICON)
36(+ICON)
42(+ICON)
ICON: “1” Enable COMI (icon display) pin
: ”0” Disable COMI (icon display) pin
Set display clock CL frequency (Two-Byte instruction)
The display clock CL affects the current consumption and the frame frequency affects
the flicker, so the fine adjustment is required for the display clock CL and the frame
frequency.
Set CL frequency select mode (First instruction)
A0
0
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
1
0
Set CL frequency select Register (Second instruction)
A0
0
/RD /WR
1
0
D7
*
D6
*
D5
*
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
*
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
*
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
CL frquency
fOSC
fOSC / 2
fOSC / 3
fOSC / 4
fOSC / 5
fOSC / 6
fOSC / 7
fOSC / 8
fOSC / 9
fOSC / 10
fOSC / 11
fOSC / 12
fOSC / 13
fOSC / 14
fOSC / 15
fOSC / 16
fOSC / 32
The information in this document is subject to change without notice.
34
43 COM / 102 SEG LCD DRIVER
Select LCD Bias (Two-Byte instruction)
Selects LCD bias ratio of the voltage required for driving the LCD.
Set LCD Bias select mode (First instruction)
A0
0
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
0
1
D1
0
0
1
1
0
0
1
1
0
0
1
D0
0
1
0
1
0
1
0
1
0
1
0
Set LCD Bias select Register (Second instruction)
A0
0
/RD /WR
1
0
D7
*
D6
*
D5
*
D4
*
D3
0
0
0
0
0
0
0
0
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
LCD Bias
1/3
1/3.5
1/4
1/4.5
1/5
1/5.5
1/6
1/6.5
1/7
1/7.5
1/8
Display ON/OFF
This is the instruction for controlling the turning on or off the LCD panel regardless of the
contents of the DDRAM.
A0
1
/RD /WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
1
Display On or Off
0 :Off
1 :On
Initial Display Line
Sets the line address of display RAM to determine the initial display line. The initial
display line corresponds to COM0.The display area read from the display data RAM
corresponds to the number of the lines set by the Duty select command.
A0
0
35
/RD /WR
1
0
D7
0
D6
1
D5
0
0
.
.
1
1
D4
0
0
.
.
0
0
D3
0
0
.
.
1
1
D2
0
0
.
.
0
0
D1
0
0
.
.
0
0
D0
0
1
.
.
0
1
Line address for COM0
0
1
.
.
40
41
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
Electronic Contrast Control Set (Two-Byte instruction)
Consists of 2-byte instruction. The first instruction sets contrast control mode, the second
one updates the contents of contrast control register. After second instruction, contrast
control mode is released. The LSI can’t accept any instructions except the “Set Contrast
Control Register” during the Contrast Control Mode.
Sets Contrast Control Mode (First instruction)
A0
0
/RD /WR
1
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
1
D1
0
0
.
.
1
1
D0
0
1
.
.
0
1
0
Set Contrast Control Register (Second instruction)
A0
0
/RD /WR
1
0
D7
*
D6
*
D5
0
0
.
.
1
1
D4
0
0
.
.
1
1
D3
0
0
.
.
1
1
D2
0
0
.
.
1
1
Electronic volume value (α)
0 Minimum
1
.
.
62
63
Set Page Address
Sets the page address of display data RAM from the microprocessor into the page
address register. It is possible to access any required bit in the display data RAM by
specifying the page address and the column address.
Along with the column address, the page address defines the address of the display
RAM to write or read display data. Changing the page address doesn't effect to the
display status. Page 6 is assigned to the icon display. D0 only is valid.
A0
0
/RD /WR
1
0
D7
1
D6
0
D5
1
D4
1
D3
0
0
.
.
0
D2
0
0
.
.
1
D1
0
0
.
.
1
D0
0
1
.
.
0
Page address
0
1
.
.
6
The information in this document is subject to change without notice.
36
43 COM / 102 SEG LCD DRIVER
Set Column Address
Sets the column address of display RAM from the microprocessor into the column
address register. When accessing the display data RAM from the MPU, the column
address is incremented. The incrementing of the column address is stopped at the
address 65H.
A0
0
/RD /WR
1
0
D7
0
D6
0
D5
0
D4
1
0
D3
A7
A3
D2
A6
A2
D1
A5
A1
D0
A4
A0
Column address setting
Upper 4-bit
Lower 4-bit
A7
0
0
.
.
0
0
A6
0
0
.
.
1
1
A5
0
0
.
.
1
1
A4
0
0
.
.
0
0
A3
0
0
.
.
0
0
A2
0
0
.
.
1
1
A1
0
0
.
.
0
0
A0
0
1
.
.
0
1
Column address
0
1
.
.
100
101
ADC Select
This instruction selects segment driver direction. Normal or reverse can be selected for
the correlation between the column address of the display data RAM and the segment
output terminal.
A0
0
/RD /WR
1
0
D0 = 0 Normal
D7
1
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
1
Segment driver direction
Normal
Reverse
Column addresses 00H to 65H correspond to segment outputs 0 to
101.
= 1 Reverse
Column addresses 00H to 65H correspond to segment outputs 101
to 0.
Inverse Display ON/OFF
The instruction is used to invert the display status on LCD panel without rewriting the
contents of the display data RAM.
A0
0
37
/RD /WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
D0
0
1
Display status
Normal
Inverse
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
D0 = 0 Normal
Display data “1” makes the LCD on.
= 1 Inverse
Display data “0” makes the LCD on.
Entire Display ON/OFF
Forces the whole LCD points to be turned on regardless of the contents of the display
data RAM. At this time, the contents of the display data RAM will be retained. This
instruction has priority over the Reverse Display On/Off instruction.
A0
0
/RD /WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
1
Entire display on/off
Normal
Entire display on
Set Modify-read
This instruction stops the automatic increment of the column address by the Read
Display Data instruction, but the column address is still increased by the Write Display
Data instruction. This instruction can reduce the load of MPU, during the display data in
specific DDRAM area is repeatedly changed for cursor blink or others. This mode is
canceled by the Reset Modify-read instruction.
A0
0
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
0
0
Reset Modify-read
This instruction cancels the Modify-read mode. The column address of the display data
RAM returns to the address before Read Modify Write is executed.
A0
0
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
1
1
0
Reset
This instruction resets initial display line, column address, page address, and common
output status select to their initial status, but dose not affect the contents of display data
RAM. This instruction cannot initialize the LCD power supply, which is initialized by the
/RES pin.
The information in this document is subject to change without notice.
38
43 COM / 102 SEG LCD DRIVER
A0
0
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
0
0
1
0
Reset status by “Reset” instruction:
1. Read modify write off
2. Static indicator off and static indicator register: (S1,S0)=(0,0)
3. Initial display line address : (00)H
4. Column address : (00)H
5. Page address : (0) page
6. SHL select : Normal mode (D3=0)
7. Regulator resistor select register: (R2,R1,R0)=(0,0,0)
8. Sets contrast control set mode off and contrast control register : (20)H
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD
driver output status.
A0
0
/RD /WR
1
0
D3 =0 Normal
=1 Reverse
D7
1
D6
1
D5
0
D4
0
D3
0
1
D2
*
D1
*
D0
*
Common driver direction
Normal
Reverse
Normal direction (COM0 Æ COM 41)
Reverse direction (COM41 Æ COM 0)
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power
supply and part of internal power supply functions can be used simultaneously.
A0
0
/RD /WR
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
VC
VR
VF
VC: Voltage converter
VR: Voltage regulator
VF: Voltage follower
0: Off 1: ON
Regulator Resistor Select
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See
39
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
voltage regulator section in power supply circuit for more details.
A0
0
/RD /WR
1
0
D7
0
D6
0
D5
1
R2
0
0
..
1
1
D4
0
R1
0
0
..
1
1
D3
0
R0
0
1
..
0
1
D2
R2
D1
R1
D0
R0
[Rb/Ra] Ratio
Small
…
..
..
Large
Set Static Indicator status (Two-Byte instruction)
Consists of two bytes instruction. The first byte instruction (Set Static Indicator Mode)
enables the second byte instruction (Set Static Indicator Register) to be valid. The first
byte sets the static indicator on/off. When it is on, the second byte updates the contents
of static indicator register without issuing any other instruction and this static indicator
state is released after setting the data of indicator register.
Set Static Indicator Mode (First instruction)
A0
0
/RD /WR
1
0
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
0
D0
0
1
D1
0
0
1
1
D0
0
1
0
1
Static indicator
Off
On
Set Static Indicator Register (Second instruction)
A0
0
/RD /WR
1
0
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
Status
Off
On（Blink at 4 frame intervals ）
On（Blink at 2 frame intervals ）
On（Turn on at all time ）
Power Save (compound instruction)
The current consumption can be greatly reduced by entering the power save status by
inputting the “Entire Display ON” instruction while the display is in OFF mode. According
to the status of static indicator mode, power save is entered to one of two modes (sleep
and standby mode). When Static Indicator mode is ON, standby mode is issued, when
OFF, sleep mode is issued. Power Save mode is released by the “Display ON” & “Entire
Display OFF” instruction.
The information in this document is subject to change without notice.
40
43 COM / 102 SEG LCD DRIVER
Static indicator OFF
Static indicator ON
Power saver (compound command)
[ Display OFF ]
[ Entire Display ON ]
Static Indicator ON
Sleep mode
Standby mode
Reset instruction
Power Save OFF ( Compound
Instruction )
[ Entire Display OFF ]
[ Display ON ]
[ Static Indicator ON ]
Power Save OFF ( Compound
Instruction )
[ Entire Display OFF ]
[ Display ON ]
Sleep mode cancel
Standby mode cancel
Sleep Mode
This stops all operations in the LCD display system, and as long as there are no
accesses from the MPU, the consumption current is reduced to a value near the static
current. The internal modes during sleep mode are as follows:
1.
The oscillator circuit and the LCD power supply circuit are stopped.
2.
All liquid crystal drive circuits are stopped, and the segment and common driver
output VSS level.
When a “static indicator on” instruction is issued in the sleep mode, the LSI goes into the
standby mode.
Standby Mode
All operations of the dynamic LCD display section are stopped, only the static display
circuits for the indicators operate and hence the current consumption will be the
minimum necessary for static drive. The internal conditions in the standby state are as
follows:
1.
The power supply circuit for LCD drive is stopped. The oscillator circuit will be
operating.
2.
The LCD drive circuits for dynamic display are stopped and the segment and
common driver outputs will be at the VSS level. The static display section will be
operating.
When a reset instruction is issued in the standby mode, the LSI goes into the sleep
mode.
41
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
APPLICATION INFORMATION
INSTRUCTION PROCEDURE EXAMPLES
Initial setup
(From power application to display ON using internal power supply circuits)
VDD-VSS Power ON
Power stabilization
Input Reset Signal
Wait for more than 20 ms
Initial settings state (default)
User settings via instruction input (1)
DUTY select
LCD bias select
CL frequency select
ADC select
SHL select
User settings via command input (2)
Regulator resistor select
Contrast control volume
User settings via command input (3)
Power control
VC,VR,VF=(1,1,1)
Waiting for more than 300ms to stabilize the LCD
power levels
End of initial settings
LCD display screen settings
Display start line set
Writing screen data, etc.
Display ON
The information in this document is subject to change without notice.
42
43 COM / 102 SEG LCD DRIVER
The sequence of “Modify-read”
Page address set
Colume address set
Set modefy-read
Dummy read
Data read
Data write
NO
Change complete
YES
End
43
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
The sequence of “External oscillator input”
Set CL frequency select mode
Set CL frequency select register
Input the clock to OSC pin
End
PROGRAM EXAMPLES
Use Elan Risc II MCU assembly
;*****************************************************************************
;
INITIALIZATION SETTING EXAMPLE OF EPL43102
;*****************************************************************************
INI_DRIVER_IC:
MOV
A,#LCD_COM_RESET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_COM_DUTY
CALL
WRITE_LCD_1BYTE
MOV
A,#DUTY_SET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_COM_BIAS
CALL
WRITE_LCD_1BYTE
MOV
A,BIAS_SET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_COM_FREQ
;INITIAL SETTINGS STATE (DEFAULT)
;SET DUTY 1ST INSTRUCTION
;SET DUTY 2ND INSTRUCTION
;SET LCD BIAS 1ST INSTRUCTION
;SET BIAS 2ND INSTRUCTION
;SET LCD CL FREQUENCY 1ST INSTRUCTION
The information in this document is subject to change without notice.
44
43 COM / 102 SEG LCD DRIVER
CALL
WRITE_LCD_1BYTE
MOV
A,#CL_FREQ
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_ADC_SET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_SHL_SET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_REGULATOR_RES_SET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_COM_CONTRAST
CALL
WRITE_LCD_1BYTE
MOV
A,#CONTRAST_SET
CALL
WRITE_LCD_1BYTE
MOV
A,#LCD_POWER_CONTROL_SET
CALL
WRITE_LCD_1BYTE
BS
REG_CPUCON,F_CKS
;SET CL FREQUENCE 2ND INSTRUCTION
;SET ADC FUNCTION SELECT
;SET SHL FUNCTION SELECT
;SET REGULATOR RESISTOR 1+(Rb/Ra)
;SET CONTRAST 1ST INSTRUCTION
;SET CONTRAST 2ND INSTRUCTION
;SET POWER CONTROL (INTERNAL OR EXTERNAL)
;ADD CLOCK BY OSC PIN (CLOCK FROM CPU)
MOV
A,#150
;WAITING FOR STABILIZING THE LCD POWER
CALL
WAIT_A_MS
CALL
LCD_DISPLAY_ON
;TURN ON LCD
MOV
A,#LCD_DISPLAY_INI_LINE
;SET INITIAL DISPLAY LINE
CALL
WRITE_LCD_1BYTE
CALL
LCD_DATA_WRITE
;WRITING SCREEN DATA
RET
*****************************************************************************
;
WRITE DISPLAY_PICTURE DATA INTO DISPLAY DATA RAM OF EPL43102
;*****************************************************************************
DATA_WRITE:
TBPTL
#DISPLAY_PICTURE*2
TBPTM
#DISPLAY_PICTURE/0x80
TBPTH
#DISPLAY_PICTURE/0x8000
;DEFINE DISPLAY PICTURE DATA INDEX
DATA_WRITE_43102:
45
MOV
A,#LINE_Y_MAX
MOV
REG_LCDARH,A
;MAX PAGES OF DDRAM
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
DATA_W1:
MOV
A,#LINE_X_MAX
MOV
REG_LCDARL,A
BC
REG_PORTB,F_LCD_A0
MOV
A,#LCD_COM_PAGE
ADD
A,REG_LCDARH
CALL
WRITE_LCD_1BYTE
MOV
A,#0b00000000
CALL
WRITE_LCD_1BYTE
MOV
A,#0b00010000
CALL
WRITE_LCD_1BYTE
BS
REG_PORTB,F_LCD_A0
;SET MAX SEGMENTS OF DDRAM
;SET LCD /A0 = 0 INSTRUCTION OUTPUT
;SET LOWER ORDER COLUMN ADDRESS=0000
;SET HIGHER ORDER COLUMN ADDRESS=0000
;SET LCD /A0 = 1 DATA OUTPUT
DATA_W2:
TBRD
01,REG_ACC
CALL
WRITE_LCD_1BYTE
DEC
REG_LCDARL
JBS
REG_STATUS,F_C,DATA_W2
DEC
REG_LCDARH
JBS
REG_STATUS,F_C,DATA_W1
BC
REG_PORTB,F_LCD_A0
;ACCESS THE DATA OF DISPLAY_PICTURE
;IDENTIFY RES_STATUS CARRY BIT SET OR NOT
;LCD /A0 = 0 FOR INSTRUCTION OUTPUT
RET
;*****************************************************************************
;
WRITE ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES)
;*****************************************************************************
;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION WRITE
WRITE_LCD_1BYTE:
JBS
REG_DCRG,F_LAHEN,WRITE_LCD_1BYTE_1
;CHECK REG_DCRG LAHEN BIT=1 OR NOT
BC
REG_PORTC,F_LCD_WR
;SET /WR=0 ENABLE WRITE
MOV
REG_DATA,A
NOP
;MOVE A==> PORT_G
;Write low pulse( Wait 2 instruction cycles)
NOP
BS
REG_PORTC,F_LCD_WR
;SET /WR=1 DISABLE WRITE
NOP
NOP
The information in this document is subject to change without notice.
46
43 COM / 102 SEG LCD DRIVER
NOP
NOP
RET
WRITE_LCD_1BYTE_1:
MOV
REG_DATA,A
;MOVE A==> PORT_G
RET
;*****************************************************************************
;
;
READ ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES)
;
;*****************************************************************************
;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ
READ_LCD_1BYTE:
BC
REG_PORTB,F_LCD_RD
;SET /RD=0 ENABLE READ
NOP
NOP
MOV
A,REG_DATA
;MOVE PORT_G ==> A
NOP
BS
REG_PORTB,F_LCD_RD
;SET /RD=1 DISABLE READ
NOP
RET
47
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Power supply
voltage
Driver supply voltage
Input voltage
Operating
temperature range
Storage temperature
range
Applicable
pins
VDD
Symbol
Condition
Rate value
VDD
－
-0.3 to +7
VOUT
ALL INPUT
－
VLCD
VIN
TA
－
－
－
-0.3 to +17
-0.3 to VDD+0.3
-30 to +80
－
-55 to +125
Rated value
Min.
Typ.
Max.
2.2
5.5
－
－
Unit
V
O
C
Recommended Operating Conditions
Parameter
Power supply
Voltage
Voltage converter
output voltage
V0 output voltage
Output voltage
Applicable
pins
VDD
Symbol
Condition
VDD
－
VOUT
VOUT
－
V0
V0
VOH
VOL
VIH
－
－
－
－
VIL
TA
－
－
Input voltage
Operating
temperature range
－
4.0
－
3.0
0.7VDD
－
－
－
－
VSS
－
0.7VDD
VSS
Unit
V
15
12
VDD
0.3VDD
VDD
0.3VDD
0
The information in this document is subject to change without notice.
40
O
C
48
43 COM / 102 SEG LCD DRIVER
DC Characteristics
(VSS=0V, VDD=2.6 to 3.3V, TA= -30~80 oC )
Parameter
Power supply
voltage
Voltage converter
input voltage
Applicable
Pins
VDD
Symbol
VDD
VDD
VDD
VDD
VDD2
VDD3
VDD4
VDD5
VREF0
VREF20
VREF40
V0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT
Reference voltage
－
Regulated voltage
OP Amp voltage
output of LCD
power supply
Voltage converter
output voltage
LCD driver ON
resistance
Reset resistor
Output current
(Source and Drain)
Input leakage
current
Output Tri-state
Dynamic current
consumption
(1/43 duty)
V0 (*1)
V0
V1
V2
V3
V4
VOUT
COMn
SEGn
/RES
(*5)
All Input (*4)
VDD
RON
RRESET
IOH
IOL
IIL
IDDD1
IDDD2
V1 sink ability
V1
Isv1
V4 source ability
V4
Isv4
49
Rated value
Min.
Typ. Max.
2.2
5.5
－
2 x boost
3 x boost
4 x boost
5 x boost
o
TA=0 C
o
TA=20 C
o
TA=40 C
o
TA=0~40 C
No load
(*2) (*3)
2.2
2.2
2.2
2.2
2.07
1.96
1.86
V0-4%
x2/x3/x4/x5
no-load
Current load
Iload= 50μA
VDD=3V, Vin=0V
VDD=3V, Vin=1.7V
VDD=3V, VOH=2.4V
VDD=3V, VOL=0.2V
VIN= VDD or 0V
95
IDDs1
VDD=3V, five
o
boosting, TA=25 C,
internal OSC.
fOSC=22kHz ,1/43
duty ratio, all display
pattern off, no load
VDD=3V, double
o
boosting, TA=25 C,
external OSC,.
fOSC=22kHz,1/32 duty
ratio, all display
pattern off, no load
V0=3.6V,
V1=2.4V (No load)
VOH=2.8V
V0=3.6V,
V4=1.2V (No load)
VOL=0.8V
Standby mode
Unit
V
5.5
－
5.0
－
3.75
－
3.0
－
2.16
2.25
2.05
2.14
1.94
2.02
V0 V0+4%
mV
V0
V1
V2
V3
V4
99
100
%
－
2
5
kΩ
400
25
-3
1.2
－
800
50
-4
2.2
－
1200
75
-5
3.2
±1
mA
－
70
±3
100
－
40
55
0.75
1
－
-0.75
-1
－
－
5
10
(*5)
Dynamic current
consumption
(1/32 duty)
Current
consumption
Condition
The information in this document is subject to change without notice.
μA
43 COM / 102 SEG LCD DRIVER
Current
consumption
Frame frequency
Internal Oscillator
frequency
External input
Oscillator
Note1:
V 0 = (1 +
IDDs2
Sleep mode
－
fFM
fOSC
TA=25 C
OSC
fOSC
TA=25 C
o
o
－
1
2
－
17
85
22
－
27
－
22
－
Hz
kHz
(63 − α )
Rb
) × VEV ; VEV = (1 −
) × VREF
252
Ra
Note2:
LCD Bias
1/8 Bias
1/7.5 Bias
1/7 Bias
1/6.5 Bias
1/6 Bias
1/5.5 Bias
1/5 Bias
1/4.5 Bias
1/4 Bias
1/3.5 Bias
1/3 Bias
V0
V1
(7/8)XV0
(6.5/7.5)XV0
(6/7)XV0
(5.5/6.5)XV0
(5/6)XV0
(4.5/5.5)XV0
(4/5)XV0
(3.5/4.5)XV0
(3/4)XV0
(2.5/3.5) XV0
(2/3)XV0
V2
(6/8)XV0
(5.5/7.5)XV0
(5/7)XV0
(4.5/6.5)XV0
(4/6)XV0
(3.5/5.5)XV0
(3/5)XV0
(2.5/4.5)XV0
(2/4)XV0
(1.5/3.5)XV0
(1/3)XV0
V3
(2/8)XV0
(2/7.5)XV0
(2/7)XV0
(2/6.5)XV0
(2/6)XV0
(2/5.5)XV0
(2/5)XV0
(2/4.5)XV0
(2/4)XV0
(2/3.5)XV0
(2/3)XV0
V4
(1/8)XV0
(1/7.5)XV0
(1/7)XV0
(1/6.5)XV0
(1/6)XV0
(1/5.5)XV0
(1/5)XV0
(1/4.5)XV0
(1/4)XV0
(1/3.5)XV0
(1/3)XV0
Note3: The target value of V0~V4 is Theoretical Value +/- 50mV
Note4: Input pin D0~D7、A0、/RD、/WR、/CS1、CS2、CLS、M/S、C86、P/S、IRS
Note5: Output pin D0~D7、FR、FRS、/DOF、CL
The information in this document is subject to change without notice.
50
43 COM / 102 SEG LCD DRIVER
AC Characteristics
Serial Interface Timing Characteristics
/CS1,CS2
tCHS
tCSS
A0
/WR
(R/W)
tASS
D6
(SCK)
tCYCS
tCLLS
tDSS
tAHS
tCLHS
tDHS
D7
(SDI)
tOHS
tDDS
D5
(SDO)
Parameter
Chip Select Setup Time
Chip Select Hold Time
Address Setup time
Address Hold time
Data Setup Time
Data Hold Time
Clock Cycle Time
Clock L Time
Clock H Time
Data Delay Time
Data Disable Time
Applicable
pins
/CS1
CS2
A0
R/W
D7
(SDI)
Symbol
Condition
tCSS
tCHS
tASS
tAHS
tDSS
tDHS
DATAÆSCK↑
SCK↑ÆDATA
D6
(SCK)
tCYCS
tCLLS
tCLHS
tDDS
tOHS
D5
(SDO)
Rated value
Min. Max.
100
－
100
100
－
100
80
－
80
300
100
100
CL= 100 pF
10
Unit
ns
－
80
50
(VSS= 0V,VDD= 2.6~3.3 V, TA=0~40oC)
51
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
80-Family MPU Read/Write Timing Characteristics
tAH8
A0
/CS1
(CS2)
tAW8
tCYC8
tCC8
/WR,/RD
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Parameter
Address Setup Time
Address Hold Time
System Cycle Time
Pulse Width(/WR)
Pulse Width(/RD)
Data Setup Time
Data Hold Time
Read Access Time
Output Disable Time
Applicable
pins
A0
A0
/WR
/RD
D0~D7
Symbol
Condition
tAW8
tAH8
tCYC8
tCC8
tDS8
tDH8
tACC8
tOH8
CL=100pF
Rated value
Min. Max.
0
－
0
500
－
160
－
200
20
－
10
60
－
40
10
Unit
ns
(VSS= 0V,VDD= 2.6~3.3 V, TA=0~40oC)
The information in this document is subject to change without notice.
52
43 COM / 102 SEG LCD DRIVER
68-Family MPU Read/Write Timing Characteristics
tcyc6
E
tEW
tAW6
A0
R/W
tAH6
/CS1
(CS2)
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Parameter
Address Setup Time
Address Hold Time
System Cycle Time
Pulse Width(/WR)
Pulse Width(/RD)
Data Setup Time
Data Hold Time
Read Access Time
Output Disable Time
Applicable
pins
A0
R/W
A0
E
Symbol
Condition
tAW6
tAH6
tCYC6
tEW
tDS6
D0~D7
tDH6
tACC6
tOH6
CL=100pF
Rated value
Min. Max.
0
－
0
500
－
160
－
200
20
－
10
60
－
40
10
Unit
ns
(VSS= 0V,VDD= 2.6~3.3 V, TA=0~40oC)
53
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
PIN CONFIGURATION
INPUT PIN CONFIGURATION
VDD
INPUT/OUTPUT PIN CONFIGURATION
VDD
Output data
Output enable
Input enable
The information in this document is subject to change without notice.
54
43 COM / 102 SEG LCD DRIVER
OUTPUT PIN CONFIGURATION
VDD
RESET INPUT PIN CONFIGURATION
VDD
55
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
LCD OUTPUT PIN CONFIGURATION
V0
V0
V1
V2
COMMON
OUTPUT
SEGMENT
OUTPUT
V4
V3
VSS
VSS
The information in this document is subject to change without notice.
56
43 COM / 102 SEG LCD DRIVER
MPU INTERFACE
Elan 8-bit MPU ( with an external memory )
VDD
VCC
PORT D_1
PORT A,B
A0
VCC
/CS1
CS2
RISC2 MPU
C68
EPL43102
PORT G
PORT D_2
PORT D_3
/RES
GND
D0 ~D7
/RD
/WR
/RES
VDD
LCD PANEL
PORT D_4
PORT D_5
PS
GND
/RESET
VDD
VCC
/OE
R/W
/CE
FLASH
D0 ~D7
A0~An
GND
Serial Interface (SPI)
VDD
VCC
A0
A0
PORT3_1
/CS1
CS2
MPU
VDD OR VSS
C68
LCD PANEL
VDD
VCC
EPL43102
SDI (D7)
SCK (D6)
SDO (D5)
PORT2
PORT1
PORT0
PS
/RES
/RES
GND
GND
/RESET
57
The information in this document is subject to change without notice.
43 COM / 102 SEG LCD DRIVER
80-Family MPU
VDD
VCC
A0
A1~A7
/IORQ
A0
DECODER
VCC
/CS1
CS2
80 type MPU
C68
EPL43102
D0 ~D7
/RD
/WR
/RES
D0 ~D7
/RD
/WR
/RES
GND
VDD
PS
GND
/RESET
68-Family MPU
VDD
VCC
A0
A1~A15
VMA
A0
DECODER
68 type MPU
VCC
/CS1
CS2
VDD
C68
EPL43102
D0 ~D7
E
R/W
/RES
GND
D0 ~D7
/RD
/WR
/RES
VDD
PS
GND
/RESET
The information in this document is subject to change without notice.
58
43 COM / 102 SEG LCD DRIVER
APPLICATION CIRCUITS
Example 1:
42x102 pixels driving application circuits (“Single-chip” using internal oscillator)
LCD PANEL
42X102 PIXELS
COM0~41
SEG0~SEG101
CLS
/IORQ
A0
.
.
An
FR
CL
/DOF
V0
V1
DECODER
MASTER
V2
V3
V4
M/S
( EPL43102 )
OSC
/CS1 CS2 A0
/RD /WR
D0~D7
/RST
A0
/RD
/WR
D0~D7
/RES
RESET
CIRCUIT
Example 2:
43x204 pixels driving application circuits (“Multi-chip” using external oscillator)
LCD PANEL
42X204 PIXELS
WITH ICONS DISPLAY
COM0~41+COMI
SEG0~SEG101
CLS
/IORQ
A0
.
.
An
DECODER
SEG0~SEG101
FR
CL
/DOF
V0
V1
MASTER
(EPL43102)
V2
V3
V4
M/S
OSC /CS1 CS2 A0 /RD /WR D0~D7 /RST
FR
CL
/DOF
V0
V1
V2
V3
V4
M/S
SLAVE
(EPL43102)
OSC /CS1 CS2 A0 /RD /WR D0~D7 /RST
MPU
CLK0
A0
/RD
/WR
D0~D7
/RES
RESET
CIRCUIT
59
The information in this document is subject to change without notice.