18 GHz Microwave PLL Synthesizer ADF41020 Data Sheet FEATURES GENERAL DESCRIPTION 18 GHz maximum RF input frequency Integrated SiGe prescaler Software compatible with the ADF4106/ADF4107/ADF4108 family of PLLs 2.85 V to 3.15 V PLL power supply Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 GHz in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and high frequency programmable feedback dividers (A, B, and P). A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The synthesizer can be used to drive external microwave VCOs via an active loop filter. Its very high bandwidth means a frequency doubler stage can be eliminated, simplifying system architecture and reducing cost. The ADF41020 is software-compatible with the existing ADF4106/ADF4107/ADF4108 family of devices from Analog Devices, Inc. Their pinouts match very closely with the exception of the ADF41020’s single-ended RF input pin, meaning only a minor layout change is required when updating current designs. APPLICATIONS Microwave point-to-point/multipoint radios Wireless infrastructure VSAT radios Test equipment Instrumentation FUNCTIONAL BLOCK DIAGRAM AVDD VP DVDD RSET GND REFERENCE REFIN CLK DATA LE 24-BIT INPUT REGISTER R COUNTER PHASE FREQUENCY DETECTOR R COUNTER LATCH LOCK DETECT FUNCTION LATCH CHARGE PUMP CP CURRENT SETTING 1 CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH-Z A, B COUNTER LATCH AVDD MUXOUT MUX N = 4(BP + A) 3pF RFIN DIVIDE BY 4 SDOUT P/P+ 1 A AND B COUNTERS M3 M2 M1 50Ω CE 10304-001 GND ADF41020 GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF41020 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF Input Stage ................................................................................8 Applications ....................................................................................... 1 Prescaler..........................................................................................8 General Description ......................................................................... 1 A Counter and B Counter ............................................................8 Functional Block Diagram .............................................................. 1 R Counter .......................................................................................9 Revision History ............................................................................... 2 PFD and Charge Pump.................................................................9 Specifications..................................................................................... 3 MUXOUT and Lock Detect.........................................................9 Timing Characteristics ................................................................ 4 Input Shift Register .......................................................................9 Absolute Maximum Ratings............................................................ 5 The Function Latch .................................................................... 13 ESD Caution .................................................................................. 5 Applications Information .............................................................. 15 Pin Configuration and Function Descriptions ............................. 6 Interfacing ................................................................................... 15 Typical Performance Characteristics ............................................. 7 PCB Design Guidelines ............................................................. 15 Theory of Operation ........................................................................ 8 Outline Dimensions ....................................................................... 16 Reference Input Section ............................................................... 8 Ordering Guide .......................................................................... 16 REVISION HISTORY 10/12—Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet ADF41020 SPECIFICATIONS DVDD = AVDD = VP = 3.0 V ± 5%, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 1 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 2 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage IOL, Output Low Current POWER SUPPLIES AVDD DVDD VP IDD 3 IP3 Power-Down Mode Min Typ Max Unit 4.0 −10 18.0 +10 350 GHz dBm MHz 10 0.8 400 DVDD 10 ±100 MHz V p-p pF µA 100 MHz Test Conditions/Comments See Figure 1 for input circuit For f < 10 MHz, ensure slew rate > 50 V/μs Biased at DVDD/2 when input is ac-coupled Programmable, see Figure 17 5.1 5.0 625 3 5.1 1 2 1 2 5.1 2 1.4 0.6 ±1 10 1.4 DVDD − 0.4 500 0.4 500 2.85 2.85 2.85 27 4.5 1 3.15 3.15 3.15 30 5 Rev. 0 | Page 3 of 16 mA µA % kΩ nA % % % With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Figure 17 TA = 25°C 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 V V µA pF The SPI interface is 1.8 V and 3 V logic compatible V Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V CMOS output chosen V µA V µA V V V mA mA µA TA = 25°C TA = 25°C TA = 25°C ADF41020 Data Sheet Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor 4 Normalized 1/f Noise 5 Phase Noise Performance 6 5.7 GHz Min Typ Unit Test Conditions/Comments −221 −118 dBc/Hz dBc/Hz −89 dBc/Hz 12.5 GHz 7 −82 dBc/Hz 17.64 GHz −96 dBc/Hz PLL loop bandwidth = 500 kHz Normalized to 10 kHz offset at 1 GHz At VCO output At 1 kHz offset and 2.5 MHz PFD frequency with 20 kHz loop bandwidth At 3 kHz offset and 2.5 MHz PFD frequency with 20 kHz loop bandwidth At 100 kHz offset and 90 MHz PFD frequency with 700 kHz loop bandwidth −80/−86 −98/<−110 −109/−113 dBc dBc dBc Spurious Signals 5.7 GHz 12.5 GHz7 17.64 GHz Max At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency At 90 MHz/180 MHz and 90 MHz PFD frequency 1 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. Guaranteed by design. Sample tested to ensure compliance. 3 TA = 25°C; AVDD = DVDD = VP = 3.0 V; P = 16; fREF = 100 MHz; fPFD = 100 MHz; RFIN = 12.8 GHz. 2 IN 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log fPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 log N. 5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 6 The phase noise is measured with a Rohde & Schwarz FSUP spectrum analyzer. The reference is provided by a Rohde & Schwarz SMA100A. 7 The phase noise and spurious noise is measured with the EV-ADF41020EB1Z evaluation board and the Rohde & Schwarz FSUP spectrum analyzer. TIMING CHARACTERISTICS AVDD = DVDD = VP = 3.0 V, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 Limit 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min t3 Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t4 CLK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE 10304-002 t5 LE Figure 2. Timing Diagram Rev. 0 | Page 4 of 16 Data Sheet ADF41020 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage, REFIN to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance1 (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to AVDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 62.82°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION 260°C 40 sec 6610 358 Two signal planes (that is, on the top and bottom surfaces of the board), two buried planes, and four vias. Rev. 0 | Page 5 of 16 ADF41020 Data Sheet 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 ADF41020 TOP VIEW 15 14 13 12 11 MUXOUT LE DATA CLK CE NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND. 10304-003 AVDD 6 AVDD 7 REFIN 8 GND 9 GND 10 GND GND GND RFIN GND Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 2, 3, 5, 9, 10 4 6, 7 Mnemonic GND RFIN AVDD 8 REFIN 11 CE 12 CLK 13 DATA 14 LE 15 MUXOUT 16, 17 DVDD 18 19 VP RSET Description Ground Pins. Input to the RF Prescaler. This input is ac-coupled internally. Analog Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. Pin 6 is the supply for the fixed divide-by-4 prescaler. Reference Input. This is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input resistance of 100 kΩ (see Figure 9). This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking the pin high powers up the device, depending on the status of the power-down bit, PD1. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches with the latch being selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. Connecting a resistor between this pin and GND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is I CP MAX = 20 CP EP 25.5 RSET So, with RSET = 5.1 kΩ, ICP MAX = 5.0 mA. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO. Exposed Pad. The exposed pad must be connected to GND. Rev. 0 | Page 6 of 16 Data Sheet ADF41020 TYPICAL PERFORMANCE CHARACTERISTICS 10 20 8/9 PRESCALER 10 REFERENCE SENSITIVITY (dBm) 5 RFIN LEVEL (dB) 0 –10 –20 –30 –40 16/17 PRESCALER –50 0 –5 –10 –15 –20 0 5 10 15 20 25 FREQUENCY (GHz) –25 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz) Figure 7. REFIN Sensitivity Figure 4. RF Input Sensitivity 6 5.0mA 4.375mA 3.75mA 3.125mA 2.5mA 1.875mA 1.25mA 0.625mA 5 4 3 2 0 0.625mA 1.25mA 1.875mA 2.5mA 3.125mA 3.75mA 4.375mA 5.0mA –1 –2 –3 –4 –5 –6 0 0.5 1.0 1.5 2.0 2.5 3.0 VCP (V) 10304-005 ICP (mA) 1 0 –20 PHASE NOISE (dBc/Hz) –40 –60 –80 –100 –120 –140 10k 100k 1M 10M FREQUENCY OFFSET (Hz) 10304-006 –160 1k MAGS11 0.20099200 0.19669930 0.19140480 0.18317790 0.17232760 0.16071930 0.14943970 0.13791310 0.12839340 0.12090700 0.11516160 0.11252430 0.11213720 0.11236920 0.11323590 0.11401910 0.11361600 0.11225360 0.10909150 0.10484100 0.09871251 0.09258573 0.08667851 0.08075383 0.07542522 0.07048169 0.06751262 0.06561201 0.06308079 0.05995205 0.05666475 ANGS11 –133.9429000 –134.7069000 –135.0024000 –135.1249000 –135.0415000 –135.1840000 –136.0447000 –137.7694000 –140.5623000 –144.7454000 –149.8260000 –155.1801000 –160.0477000 –164.5794000 –168.1217000 –170.9163000 –173.2882000 –175.2539000 –176.9327000 –179.0774000 178.5525000 175.9697000 172.5878000 168.3692000 163.5676000 159.0954000 154.6976000 149.2087000 142.2284000 137.8226000 134.1730000 FREQ 10.2 10.4 10.6 10.8 11.0 11.4 11.8 12.2 12.6 13.0 13.4 13.8 14.2 14.6 15.0 15.2 15.4 15.6 15.8 16.0 16.2 16.4 16.6 16.8 17.0 17.2 17.4 17.6 17.8 18.0 MAGS11 0.05542031 0.05306026 0.05123230 0.04471957 0.03846882 0.03402513 0.04456061 0.05158395 0.06039219 0.05580344 0.08402054 0.10374910 0.11639920 0.13647950 0.16700580 0.18309070 0.19458010 0.20377790 0.21170140 0.21883690 0.22280700 0.22498210 0.22589250 0.22572100 0.22596830 0.23197900 0.24339450 0.26023130 0.28636130 0.31905490 Figure 8. S-Parameters Figure 5. Charge Pump Output Characteristics –180 100 FREQ 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 10.0 Figure 6. Closed-Loop Phase Noise, RF = 12.5 GHz, PFD = 2.5 MHz, Loop Bandwidth = 20 kHz Rev. 0 | Page 7 of 16 ANGS11 130.0581000 126.9556000 115.8988000 102.0333000 86.3895600 51.1515300 21.0829700 16.8124600 16.5178200 31.4631600 36.3540700 18.8428500 0.2817307 –15.4473000 –22.3273100 –24.3333900 –25.3870800 –25.0101800 –24.2554800 –23.4312200 –23.5596400 –24.411100 –26.5202700 –30.3773300 –36.2808700 –42.8398200 –50.7222200 –57.5844600 –63.0764200 –67.5389600 10304-008 FREQ UNIT: GHz KEYWORD: R PARAM TYPE: s DATA FORMAT: MA 1000 10304-007 –70 10304-004 –60 ADF41020 Data Sheet THEORY OF OPERATION REFERENCE INPUT SECTION PRESCALER The reference input stage is shown in Figure 9. SW1 and SW2 are normally closed switches. SW3 is a normally open switch. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The ADF41020 uses a two prescaler approach to achieve operation up to 18 GHz. The first prescaler is a fixed divide-by-4 block. The second prescaler, which takes its input from the divide-by-4 output, is implemented as a dualmodulus prescaler (P/P + 1), which allows finer frequency resolution vs. a fixed prescaler. Along with the A counter and B counter, this enables the large division ratio, N, to be realized (N = 4(BP + A)). The dual-modulus prescaler, operating at CML levels, takes the clock from the fixed prescaler stage and divides it down to a manageable frequency for the CMOS A counter and B counter. The second prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. There is a minimum divide ratio possible for contiguous output frequencies. This minimum is given by 4(P2 − P). POWER-DOWN CONTROL 100kΩ NC SW2 REFIN TO R COUNTER NC BUFFER SW1 10304-009 SW3 NO Figure 9. Reference Input Stage A COUNTER AND B COUNTER RF INPUT STAGE The RF input stage is shown in Figure 10. It is followed by a buffer, which generates the differential CML levels needed for the prescaler. AVDD The A counter and B counter combine with the two prescalers to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 350 MHz or less. Pulse Swallow Function 3pF RFIN BUFFER Because of the fixed divide-by-4 block, the generated output frequencies are spaced by four times the reference frequency divided by R. The equation for VCO frequency is TO DIVIDE BY 4 PRESCALER fVCO (P B) A 50Ω IN R where: fVCO is the output frequency of the external voltage controlled oscillator (VCO). P is the preset modulus of the dual-modulus prescaler (such as, 8/9, 16/17). B is the preset divide ratio of the binary 13-bit counter (2 to 8191). A is the preset divide ratio of the binary 6-bit swallow counter (0 to 63). fREFIN is the external reference frequency oscillator. 10304-010 GND 4 f REF Figure 10. RF Input Stage N = 4(BP + A) 13-BIT B COUNTER DIVIDE BY 4 FROM RF INPUT BUFFER PRESCALER P/P + 1 LOAD LOAD 6-BIT A COUNTER 10304-011 MODULUS CONTROL TO PFD N DIVIDER Figure 11. Prescalers, A and B Counters that Make Up the N-Divide Value Rev. 0 | Page 8 of 16 Data Sheet ADF41020 R COUNTER DVDD The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. DIGITAL LOCK DETECT R COUNTER OUTPUT PFD AND CHARGE PUMP MUX CONTROL MUXOUT N COUNTER OUTPUT MUXOUT AND LOCK DETECT The output multiplexer on the ADF41020 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 17 shows the full truth table. Figure 12 shows the MUXOUT section in block diagram form. Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. Digital lock detect is set high when the phase error on five consecutive phase detector cycles is less than 15 ns. It stays set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. SDOUT GND Figure 12. MUXOUT Circuit INPUT SHIFT REGISTER The ADF41020 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of three latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. C2 and C1 are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5. Table 5 shows a summary of how the latches are programmed. The SPI is both 1.8 V and 3 V compatible. Table 5. C1, C2 Truth Table Control Bits C2 C1 0 0 0 1 1 0 Data Latch R counter N counter (A and B) Function latch (including prescaler) VP CHARGE PUMP HIGH D1 Q1 UP U1 CLR1 FIXED DELAY HIGH U3 CP CLR2 DOWN D2 Q2 U2 N DIVIDER GND Figure 13. PFD Simplified Schematic Rev. 0 | Page 9 of 16 10304-012 R DIVIDER 10304-013 The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 13 is a simplified schematic. The PFD includes a fixed delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. The charge pump converts the PFD output to current pulses, which are integrated by the PLL loop filter. ADF41020 Data Sheet REFERENCE COUNTER LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 1 0 0 1 CONTROL BITS 14-BIT REFERENCE COUNTER RESERVED 0 0 0 1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) RESERVED CP GAIN N COUNTER LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 0 G1 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 6-BIT A COUNTER B5 B4 B3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) MUXOUT CONTROL CONTROL BITS DB1 DB0 CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 P2 P1 PD2 CURRENT SETTING 2 CPI6 CPI5 CURRENT SETTING 1 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 F5 DB1 DB0 C2 (1) C1 (0) 10304-014 FAST LOCK ENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 PRESCALER VALUE POWERDOWN 2 FAST LOCK MODE FUNCTION LATCH Figure 14. Latch Summary 0 0 1 0 0 0 1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 0 1 1 0 . . . 1 0 1 0 . . . 1 2 3 4 . . . 1 1 1 1 1 1 1 1 1 .......... .......... .......... 1 1 1 0 0 1 0 1 0 16380 16381 16382 1 1 1 .......... 1 1 1 16383 Figure 15. Reference Counter Latch Map Rev. 0 | Page 10 of 16 10304-015 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 1 CONTROL BITS 14-BIT REFERENCE COUNTER RESERVED ADF41020 CP GAIN Data Sheet RESERVED CONTROL BITS 6-BIT A COUNTER 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 B13 B12 B11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... A5 .......... A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 60 61 62 63 B2 B1 B COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED NOT ALLOWED 2 3 . . . 8188 8189 8190 8191 CP GAIN OPERATION 0 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. 0 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. 1 0 CHARGE PUMP CURRENT SETTING 1 IS USED. 1 1 CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FAST LOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. DB0 A6 B3 F4 (FUNCTION LATCH) FASTLOCK ENABLE DB1 C2 (0) C1 (1) N = 4(BP + A), P IS A PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × FREF), AT THE OUTPUT, N MIN IS 4(P2 – P). 10304-016 BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. Figure 16. N (A, B) Counter Latch Map Rev. 0 | Page 11 of 16 CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) POWERDOWN 2 FAST LOCK ENABLE Data Sheet FAST LOCK MODE ADF41020 PRESCALER VALUE PD2 P1 CPI6 CPI5 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPI6 CPI5 CPI4 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 PD2 PD1 MODE 0 0 0 X 0 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION SOFTWARE POWER-DOWN P1 PRESCALER VALUE 0 1 0 1 8/9 16/17 32/33 64/65 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FAST LOCK MODE 0 1 1 X 0 1 FAST LOCK DISABLED FAST LOCK MODE 1 FAST LOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT RESERVED SERIAL DATA OUTPUT DGND 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 CE PIN 0 0 1 1 F2 CONTROL BITS ICP (mA) 0 1 1 P2 F5 MUXOUT CONTROL 10304-017 P2 CURRENT SETTING 1 CURRENT SETTING 2 Figure 17. Function Latch Map Rev. 0 | Page 12 of 16 Data Sheet ADF41020 THE FUNCTION LATCH Fast Lock Mode 2 With C2 and C1 set to 1 and 0, respectively, the on-chip function latch is programmed. Figure 17 shows the input data format for programming the function latch. The charge pump current is switched to the contents of Current Setting 2. The device enters fast lock when 1 is written to the CP gain bit in the N (A, B) counter latch. The device exits fast lock under the control of the timer counter. After the timeout period, which is determined by the value in TC4 to TC1, the CP gain bit in the N (A, B) counter latch is automatically reset to 0, and the device reverts to normal mode instead of fast lock. See Figure 17 for the timeout periods. Counter Reset DB2 (F1) is the counter reset bit. When this is 1, the R counter and the N (A, B) counter is reset. For normal operation, this bit should be 0. When powering up, disable the F1 bit (set to 0). The N counter then resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle). Power-Down Bit DB3 (PD1) provides a software power-down mode to reduce the overall current drawn by the device. It is enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the state of PD1. In the programmed software power-down, the device powers down immediately after latching 1 into the PD1 bit. PD2 is a reserved bit and should be cleared to 0. When a power-down is activated, the following events occur: • • • • • • • All active dc current paths in the main synthesizer section are removed. However, the RF divide-by-4 prescaler remains active. The R, N, and timeout counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital clock detect circuitry is reset. The RFIN input is debiased. The reference input buffer circuitry is disabled. The input register remains active and capable of loading and latching data. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF41020. Figure 17 shows the truth table. Fast Lock Enable Bit Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). The normal sequence of events follows. The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 0.85 mA as Current Setting 1 and 1.7 mA as Current Setting 2. Simultaneously, the decision must be made as to how long the secondary current stays active before reverting to the primary current. This is controlled by the timer counter control bits, DB14 to DB11 (TC4 to TC1), in the function latch. The truth table is given in Figure 17. To program a new output frequency, simply program the N (A, B) counter latch with new values for A and B. Simultaneously, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6 to CPI4 for a period of time determined by TC4 to TC1. When this time is up, the charge pump current reverts to the value set by CPI3 to CPI1. At the same time, the CP gain bit in the N (A, B) counter latch is reset to 0 and is ready for the next time the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fast Lock Mode 2 is chosen by setting the fast lock mode bit (DB10) in the function latch to 1. Charge Pump Currents Bit DB9 (F4) of the function latch is the fast lock enable bit. When this bit is 1, fast lock is enabled. Fast Lock Mode Bit Bit DB10 (F5)of the function latch is the fast lock mode bit. When fast lock is enabled, this bit determines which fast lock mode is used. If the fast lock mode bit is 0, then Fast Lock Mode 1 is selected; and if the fast lock mode bit is 1, then Fast Lock Mode 2 is selected. Fast Lock Mode 1 The charge pump current is switched to the contents of Current Setting 2. The device enters fast lock when 1 is written to the CP gain bit in the N (A, B) counter latch. The device exits fast lock when 0 is written to the CP gain bit in the N (A, B) counter latch. CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 17. Prescaler Value P2 and P1 in the function latch set the programmable P prescaler value. The P value should be chosen so that the prescaler output frequency is always less than or equal to 350 MHz. PD Polarity Bit DB7 (F2) sets the phase detector polarity bit. See Figure 17. Rev. 0 | Page 13 of 16 ADF41020 Data Sheet CP Three-State 6. Bit DB8 (F3) controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. Device Programming After Initial Power-Up After initial power up of the device, there are three methods for programming the device: function latch, CE pin, and counter reset. Function Latch Method 1. 2. 3. 4. Apply VDD. Program the function latch load (10 in two LSBs of the control word), making sure that the F1 bit is programmed to a 0. Do an R load (00 in two LSBs). Do an N (A, B) load (01 in two LSBs). CE Pin Method 1. 2. 3. 4. 5. Apply VDD. Bring CE low to put the device into power-down. This is an asychronous power-down in that it happens immediately. Program the function latch (10). Program the R counter latch (00). Program the N (A, B) counter latch (01). Bring CE high to take the device out of power-down. The R and N (A, B) counters now resume counting in close alignment. Note that after CE goes high, a 1 µs duration may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it is programmed at least once after VDD is initially applied. Counter Reset Method 1. 2. 3. 4. 5. Apply VDD. Do a function latch load (10 in two LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. Do an R counter load (00 in two LSBs). Do an N (A, B) counter load (01 in two LSBs). Do a function latch load (10 in two LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides direct control over the internal counter reset. Rev. 0 | Page 14 of 16 Data Sheet ADF41020 APPLICATIONS INFORMATION INTERFACING Blackfin BF527 Interface The ADF41020 has a simple 1.8 V and 3 V SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. Figure 19 shows the interface between the ADF41020 and the Blackfin® ADSP-BF527 digital signal processor (DSP). The ADF41020 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the Blackfin family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. As in the microcontroller case, ensure the clock speeds are within the maximum limits outlined in Table 1. The maximum allowable serial clock rate is 20 MHz. ADuC7020 Interface Figure 18 shows the interface between the ADF41020 and the ADuC7019 to ADuC7023 family of analog microcontrollers. The ADuC70xx family is based on an AMR7 core, although the same interface can be used with any 8051-based microcontroller. The microcontroller is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF41020 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microcontroller to the device. When the third byte is written, bring the LE input high to complete the transfer. SCK MOSI ADSP-BF527 GPIO Figure 19. ADSP-BF527-to-ADF41020 Interface PCB DESIGN GUIDELINES The lands on the LFCSP (CP-20) are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center the land on the pad to ensure that the solder joint size is maximized. The bottom of the LFCSP has a central thermal pad. DATA ADF41020 CE MUXOUT (LOCK DETECT) Figure 18. ADuC70xx-to-ADF41020 Interface 10304-018 I/O PORTS The thermal pad on the PCB should be at least as large as the exposed pad. To avoid shorting, on the PCB, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. CLK LE ADF41020 Thermal vias may be used on the PCB thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and plate the via barrel with 1 oz copper to plug the via. Connect the PCB thermal pad to GND. Rev. 0 | Page 15 of 16 10304-019 MUXOUT (LOCK DETECT) When operating in the mode described, the maximum SPI transfer rate of the ADuC7023 is 20 Mbps. This means that the maximum rate at which the output frequency can be changed is 833 kHz. If using a faster SPI clock, ensure adherence to the SPI timing requirements listed in Table 1. ADuC70xx LE I/O FLAGS I/O port lines on the microcontroller are also used to control power-down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). MOSI DATA CE On first applying power to the ADF41020, it needs three writes (one each to the function latch, R counter latch, and N counter latch) for the output to become active. SCLOCK CLK ADF41020 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. 08-16-2010-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 20. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-6) Dimensions shown in millimeters ORDERING GUIDE Model1 ADF41020BCPZ ADF41020BCPZ-RL7 EV-ADF41020EB1Z 1 Temperature Range –40°C to +85°C –40°C to +85°C Package Description 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ) Evaluation Board Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10304-0-10/12(0) Rev. 0 | Page 16 of 16 Package Option CP-20-6 CP-20-6