Integrated Synthesizer and VCO ADF4360-1 FEATURES GENERAL DESCRIPTION Output frequency range: 2050 MHz to 2450 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4360-1 is a fully integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-1 is designed for a center frequency of 2250 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF output of between 1025 MHz and 1225 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD CE RSET ADF4360-1 MUXOUT MULTIPLEXER 14-BIT R COUNTER REFIN LOCK DETECT CLK DATA MUTE 24-BIT FUNCTION LATCH 24-BIT DATA REGISTER LE CHARGE PUMP CP PHASE COMPARATOR VVCO VTUNE CC CN INTEGER REGISTER RFOUTA VCO CORE 13-BIT B COUNTER 5-BIT A COUNTER MULTIPLEXER N = (BP + A) RFOUTB LOAD LOAD AGND DGND DIVSEL = 1 DIVSEL = 2 ÷2 04414-0-001 PRESCALER P/P+1 OUTPUT STAGE CPGND Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADF4360-1 TABLE OF CONTENTS Specifications..................................................................................... 3 VCO ............................................................................................. 10 Timing Characteristics..................................................................... 5 Output Stage................................................................................ 11 Absolute Maximum Ratings............................................................ 6 Latch Structure ........................................................................... 12 Transistor Count........................................................................... 6 Control Latch .............................................................................. 16 ESD Caution.................................................................................. 6 N Counter Latch......................................................................... 17 Pin Configuration and Function Descriptions............................. 7 R Counter Latch ......................................................................... 17 Typical Performance Characteristics ............................................. 8 Applications..................................................................................... 18 Circuit Description........................................................................... 9 Direct Conversion Modulator .................................................. 18 Reference Input Section............................................................... 9 Fixed Frequency LO................................................................... 19 Prescaler (P/P + 1)........................................................................ 9 Power-Up..................................................................................... 19 A and B Counters ......................................................................... 9 Interfacing ................................................................................... 19 R Counter ...................................................................................... 9 PCB Design Guidelines for Chip-Scale Package.......................... 20 PFD and Charge Pump................................................................ 9 Output Matching ........................................................................ 20 MUXOUT and Lock Detect...................................................... 10 Outline Dimensions ....................................................................... 21 Input Shift Register..................................................................... 10 Ordering Guide .......................................................................... 21 REVISION HISTORY 6/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specifications ................................................................ 3 Changes to Table 6.......................................................................... 12 Changes to Table 7.......................................................................... 13 Changes to Table 9.......................................................................... 15 8/03—Revision 0: Initial Version Rev. A | Page 2 of 24 ADF4360-1 SPECIFICATIONS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source3 High Value Low Value RSET Range ICP 3-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH,, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VVCO AIDD4 DIDD4 IVCO4, 5 IRFOUT4 Low Power Sleep Mode4 RF OUTPUT CHARACTERISTICS5 VCO Output Frequency VCO Sensitivity Lock Time6 Frequency Pushing, (Open Loop) Frequency Pulling, (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power Variation VCO Tuning Range B Version Unit Conditions/Comments 10/250 MHz min/max 0.7/AVDD 0 to AVDD 5.0 ±100 p-p min/max V max pF max µA max For f < 10 MHz, use a dc-coupled CMOS compatible square wave, slew rate > 21 V/µs. AC-coupled. CMOS compatible. 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.5 2 mA typ mA typ kΩ nA typ % typ % typ % typ 1.5 0.6 ±1 3.0 V min V max µA max pF max DVDD – 0.4 500 0.4 V min µA max V max 3.0/3.6 AVDD AVDD 10 2.5 24.0 3.5–11.0 7 V min/V max mA typ mA typ mA typ mA typ µA typ 2050/2450 57 400 6 15 −20 −35 −13/−6 ±3 1.25/2.5 MHz min/max MHz/V typ µs typ MHz/V typ kHz typ dBc typ dBc typ dBm typ dB typ V min/max With RSET = 4.7 kΩ. Rev. A | Page 3 of 24 1.25 V ≤ VCP ≤ 2.5 V. 1.25 V ≤ VCP ≤ 2.5 V. VCP = 2.0 V. CMOS output chosen. IOL = 500 µA. ICORE = 15 mA. RF output stage is programmeable. ICORE = 15 mA. To within 10 Hz of final frequency. Into 2.00 VSWR load. Programmable in 3 dB steps. Table 7. For tuned loads, see Output Matching section. ADF4360-1 Parameter NOISE CHARACTERISTICS1, 5 VCO Phase Noise Performance8 Synthesizer Phase Noise Floor9 In-Band Phase Noise10, 11 RMS Integrated Phase Error12 Spurious Signals due to PFD Frequency11, 13 B Version Unit Conditions/Comments −110 −130 −141 −148 −172 −163 −147 −81 0.72 −70 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Degrees typ dBc typ @ 100 kHz offset from carrier. @ 1 MHz offset from carrier. @ 3 MHz offset from carrier. @ 10 MHz offset from carrier. @ 25 kHz PFD frequency. @ 200 kHz PFD frequency. @ 8 MHz PFD frequency. @ 1 kHz offset from carrier. 100 Hz to 100 kHz. 1 Operating temperature range is: –40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance. ICP is internally modified to maintain constant-loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32. 5 These characteristics are guaranteed for VCO Core Power = 15 mA. 6 Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 Using 50 Ω resistors to VVCO, into a 50 Ω load. For tuned loads, see Output Matching section. 8 The noise of the VCO is measured in open-loop conditions. 9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 10 The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 12500; Loop B/W = 10 kHz. 12 fREFIN = 10 MHz; fPFD = 1 MHz; N = 2400; Loop B/W = 25 kHz. 13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFOUT = 10 MHz @ 0 dBm. 2 3 Rev. A | Page 4 of 24 ADF4360-1 TIMING CHARACTERISTICS AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04414-0-002 Parameter t1 t2 t3 t4 t5 t6 t7 LE Figure 2. Timing Diagram Rev. A | Page 5 of 24 ADF4360-1 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance (Paddle Soldered) (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 150°C This device is a high performance RF integrated circuit with an ESD rating of <1 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 50°C/W 88°C/W TRANSISTOR COUNT 215°C 220°C 12543 (CMOS) and 700 (Bipolar) GND = AGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 ADF4360-1 CE AGND DVDD MUXOUT LE 22 21 20 19 CP 24 23 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IDENTIFIER CPGND 1 AVDD 2 18 DATA 17 CLK ADF4360 AGND 3 16 REFIN TOP VIEW (Not to Scale) RFOUTA 4 15 DGND RFOUTB 5 14 CN 04414-0-003 CC 12 AGND 11 AGND 10 AGND 9 VTUNE 7 13 RSET AGND 8 VVCO 6 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic CPGND AVDD 3, 8 to 11, 22 4 AGND RFOUTA 5 RFOUTB 6 VVCO 7 VTUNE 12 13 CC RSET Function Charge Pump Ground. This is the ground return path for the charge pump. Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must have the same value as DVDD. Analog Ground. This is the ground return path of the prescaler and VCO. VCO Output. The output level is programmable from −6 dBm to −13 dBm. See the Output Matching section for a description of the various output stages. VCO Complementary Output. The output level is programmable from −6 dBm to −13 dBm. See Output Matching section for a description of the various output stages. Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VVCO must have the same value as AVDD. Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage. Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor. Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is I CPmax = 14 15 16 CN DGND REFIN 17 CLK 18 DATA 19 LE 20 MUXOUT 21 DVDD 23 CE 24 CP 11.75 RSET With RSET = 4.7 kΩ, ICPMAX = 2.5 mA. Internal Compensation Node. This pin must be decoupled to VVCO with a 10 µF capacitor. Digital Ground. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, and the relevant latch is selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must have the same value as AVDD. Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. Taking the pin high powers up the device depending on the status of the power-down bits. Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn drives the internal VCO. Rev. A | Page 7 of 24 ADF4360-1 0 –10 –20 OUTPUT POWER (dB) 1 2 3 100k 1M FREQUENCY OFFSET (Hz) –40 –50 –60 –83.0dBc/Hz –70 –80 4 10k –30 VDD = 3V, VVCO = 3V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 10kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10 04414-0-007 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 1k –90 04414-0-004 OUTPUT POWER (dB) TYPICAL PERFORMANCE CHARACTERISTICS –2kHz –1kHz 2250MHz 1kHz 2kHz 10M Figure 7. Close-In Phase Noise at 2250 MHz (200 kHz Channel Spacing) VDD = 3V, VVCO = 3V ICP = 2.5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 10kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 1.3 SECONDS AVERAGES = 1 –10 –20 OUTPUT POWER (dB) –30 –40 –50 –70 –80 10k 100k FREQUENCY OFFSET (Hz) 1M 04414-0-008 1000 –70.7dBc –60 –90 10M –200kHz –145 –150 –155 100 2250MHz 100kHz 200kHz Figure 8. Reference Spurs at 2250 MHz (200 kHz Channel Spacing, 10 kHz Loop Bandwidth) 0 –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 –125 –130 –135 –140 –10 OUTPUT POWER (dB) –20 –30 –40 VDD = 3V, VVCO = 3V ICP = 2.5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 25kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 1.9 SECONDS AVERAGES = 10 –50 –60 –84.8dBc/Hz –70 –80 04414-0-006 OUTPUT POWER (dB) Figure 5. VCO Phase Noise, 2250 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth –100kHz 1000 10k 100k FREQUENCY OFFSET (Hz) 1M 04414-0-009 –145 –150 –155 100 0 04414-0-005 OUTPUT POWER (dB) Figure 4. Open Loop VCO Phase Noise –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 –125 –130 –135 –140 –90 –1MHz 10M –0.5MHz 2250MHz 0.5MHz 1MHz Figure 9. Reference Spurs at 2250 MHz (1 MHz Channel Spacing, 25 kHz Loop Bandwidth) Figure 6. VCO Phase Noise, 1125 MHz, Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth Rev. A | Page 8 of 24 ADF4360-1 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 10. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. N = BP + A 13-BIT B COUNTER LOAD PRESCALER P/P+1 FROM VCO POWER-DOWN CONTROL 5-BIT A COUNTER MODULUS CONTROL 100kΩ N DIVIDER TO R COUNTER Figure 11. A and B Counters SW3 NO 04414-0-010 BUFFER SW1 R COUNTER Figure 10. Reference Input Stage PRESCALER (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the VCO and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, or 32/33 and is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies; this minimum is determined by P, the prescaler value, and is given by (P2−P). A AND B COUNTERS The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 12 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9). The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide range division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with a VCO frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. VP HI D1 Q1 CHARGE PUMP UP U1 R DIVIDER CLR1 Pulse Swallow Function PROGRAMMABLE DELAY The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The VCO frequency equation is ABP1 CLR2 HI fVCO = [(P × B) + A] × f REFIN / R D2 Q2 CP U3 ABP2 DOWN U2 N DIVIDER where: fVCO is the output frequency of the VCO. P is the preset modulus of the dual-modulus prescaler (8/9, 16/17, and so on). B is the preset divide ratio of the binary 13-bit counter (3 to 8191). A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31). fREFIN is the external reference frequency oscillator. CPGND R DIVIDER N DIVIDER CP OUTPUT Figure 12. PFD Simplified Schematic and Timing (In Lock) Rev. A | Page 9 of 24 04414-0-012 SW2 REFIN NC LOAD 04414-0-011 NC TO PFD ADF4360-1 MUXOUT AND LOCK DETECT Table 5. C2 and C1 Truth Table The output multiplexer on the ADF4360 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown on Table 7. Figure 13 shows the MUXOUT section in block diagram form. Lock Detect MUXOUT can be programmed for two types of lock detect: digital and analog. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output will be high with narrow low-going pulses. DVDD Data Latch Control Bits C1 0 1 0 1 C2 0 0 1 1 Control Latch R Counter N Counter (A and B) Test Modes Latch VCO The VCO core in the ADF4360 family uses eight overlapping bands, as shown in Figure 14, to allow a wide frequency range to be covered without a large VCO sensitivity (KV) and resultant poor phase noise and spurious performance. The correct band is chosen automatically by the band select logic at power-up or whenever the N counter latch is updated. It is important that the correct write sequence be followed at power-up. This sequence is 1. R counter latch 2. Control latch 3. N counter latch During band select, which takes five PFD cycles, the VCO VTUNE is disconnected from the output of the loop filter and connected to an internal reference voltage. ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT MUX 3.0 MUXOUT CONTROL 2.8 N COUNTER OUTPUT 2.6 SDOUT The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed. Note that the test modes latch is used for factory testing and should not be programmed by the user. 1.6 1.4 1.2 1.0 0.6 2550 2500 2450 2400 2350 2300 2250 2200 2150 2100 2050 0.2 2000 0.4 2600 04414-0-014 0.8 1950 The ADF4360 family’s digital section includes a 24-bit input shift register, a 14-bit R counter, and an 18-bit N counter, comprising of a 5-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs—DB1, DB0—as shown in Figure 2. 1.8 1900 INPUT SHIFT REGISTER 2.0 1850 Figure 13. MUXOUT Circuit 2.2 VOLTAGE (V) DGND 04414-0-013 2.4 FREQUENCY (MHz) Figure 14. Frequency vs. VTUNE, ADF4360-1 The R counter output is used as the clock for the band select logic and should not exceed 1 MHz. A programmable divider is provided at the R counter input to allow division by 1, 2, 4, or 8 and is controlled by Bits BSC1 and BSC2 in the R counter latch. Where the required PFD frequency exceeds 1 MHz, the divide ratio should be set to allow enough time for correct band selection. Rev. A | Page 10 of 24 ADF4360-1 After band select, normal PLL action resumes. The nominal value of KV is 57 MHz/V or 28 MHZ/V if divide-by-2 operation has been selected (by programming DIV2 (DB22), high in the N counter latch). The ADF4360 family contains linearization circuitry to minimize any variation of the product of ICP and KV. The operating current in the VCO core is programmable in four steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by Bits PC1 and PC2 in the control latch. If the outputs are used individually, the optimum output stage consists of a shunt inductor to VDD. Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the Mute-Till-Lock Detect (MTLD) bit in the control latch. RFOUTA RFOUTB OUTPUT STAGE Rev. A | Page 11 of 24 VCO BUFFER/ DIVIDE BY 2 04414-0-015 The RFOUTA and RFOUTB pins of the ADF4360 family are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 15. To allow the user to optimize the power dissipation versus the output power requirements, the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch. Four current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give output power levels of −13 dBm, −10.5 dBm, −8 dBm, and −6 dBm, respectively, using a 50 Ω resistor to VDD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section). Figure 15. Output Stage ADF4360-1 ADF4360-1 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed. Table 6. Latch Structure DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG MUXOUT CONTROL COUNTER RESET CP THREESTATE PHASE DETECTOR POLARITY OUTPUT POWER LEVEL CURRENT SETTING 1 CP GAIN CURRENT SETTING 2 MUTE-TILLLD POWERDOWN 1 PRESCALER VALUE POWERDOWN 2 CONTROL LATCH CORE POWER LEVEL CONTROL BITS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CP PDP M3 M2 M1 CR PC2 PC1 C2 (0) C1 (0) DB1 DB0 RESERVED CP GAIN DIVIDEBY-2 DIVIDE-BY2 SELECT N COUNTER LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DIVSEL DIV2 CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 CONTROL BITS 5-BIT A COUNTER DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 RSV A5 A4 A3 A2 A1 DB1 DB0 C2 (1) C1 (0) ANTIBACKLASH PULSE WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 CONTROL BITS 14-BIT REFERENCE COUNTER R14 R13 R12 R11 R10 R9 Rev. A | Page 12 of 24 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (0) C1 (1) 04414-0-026 BAND SELECT CLOCK TEST MODE BIT LOCK DETECT PRECISION RESERVED RESERVED R COUNTER LATCH ADF4360-1 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 PD1 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 PL2 PL1 MTLD CPG COUNTER RESET OUTPUT POWER LEVEL CP THREESTATE PHASE DETECTOR POLARITY CURRENT SETTING 1 CP GAIN CURRENT SETTING 2 MUTE-TILLLD POWERDOWN 1 PRESCALER VALUE POWERDOWN 2 Table 7. Control Latch MUXOUT CONTROL CORE POWER LEVEL DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 CP PDP M3 M2 M1 CR PC2 PC1 C2 (0) C1 (0) PC2 0 0 1 1 CPI6 CPI5 CPI4 ICP(mA) CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 4.7kΩ 0.31 0.62 0.93 1.25 1.56 1.87 2.18 2.50 PDP 0 1 CP 0 1 CPG 0 1 MTLD 0 1 PL2 0 0 1 1 P2 0 0 1 1 P1 0 1 0 1 PD2 X X 0 1 PD1 X 0 1 1 PRESCALER VALUE 8/9 16/17 32/33 32/33 OUTPUT POWER LEVEL 0 1 0 1 CURRENT 3.5mA 5.0mA 7.5mA 11.0mA PHASE DETECTOR POLARITY NEGATIVE POSITIVE PC1 0 1 0 1 DB1 DB0 CORE POWER LEVEL 5mA 10mA 15mA 20mA COUNTER OPERATION CR 0 1 NORMAL R, A, B COUNTERS HELD IN RESET CHARGE PUMP OUTPUT NORMAL THREE-STATE CP GAIN CURRENT SETTING 1 CURRENT SETTING 2 MUTE-TILL-LOCK DETECT DISABLED ENABLED POWER INTO 50Ω (USING 50Ω TO VVCO) –13dBm –10.5dBm –8dBm –6dBm MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN 04414-0-016 CE PIN 0 1 1 1 PL1 CONTROL BITS Rev. A | Page 13 of 24 M3 0 0 M2 0 0 M1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 1 0 1 OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4360-1 RESERVED CP GAIN DIVIDEBY-2 DIVIDE-BY2 SELECT Table 8. N Counter Latch 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DIVSEL DIV2 CPG B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 CONTROL BITS 5-BIT A COUNTER DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 RSV A5 A4 A3 A2 A1 DB1 DB0 C2 (1) C1 (0) THIS BIT IS NOT USED BY THE DEVICE AND IS A DON'T CARE BIT. A5 0 0 0 0 . . . 1 1 1 1 B12 0 0 0 0 . . . 1 1 1 1 B11 0 0 0 0 . . . 1 1 1 1 F4 (FUNCTION LATCH) CP GAIN FASTLOCK ENABLE 0 0 0 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... B3 0 0 0 1 . . . 1 1 1 1 B2 0 0 1 1 . . . 0 0 1 1 B1 0 1 0 1 . . . 0 1 0 1 .......... A2 A1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 A COUNTER DIVIDE RATIO 0 1 2 3 . . . 28 29 30 31 B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 8188 8189 8190 8191 OPERATION CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × FREF), AT THE OUTPUT, NMIN IS (P2–P). DIV2 0 1 DIVSEL 0 1 DIVIDE-BY-2 FUNDAMENTAL OUTPUT DIVIDE-BY-2 DIVIDE-BY-2 SELECT (PRESCALER INPUT) FUNDAMENTAL OUTPUT SELECTED DIVIDE-BY-2 SELECTED Rev. A | Page 14 of 24 04414-0-018 B13 0 0 0 0 . . . 1 1 1 1 A4 ADF4360-1 TEST MODE BIT LOCK DETECT PRECISION RESERVED RESERVED Table 9. R Counter Latch BAND SELECT CLOCK ANTIBACKLASH PULSE WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 RSV BSC2 BSC1 TMB THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. LDP ABP2 ABP1 TEST MODE BIT SHOULD BE SET TO 0 FOR NORMAL OPERATION. LDP 0 1 BSC1 0 1 0 1 R13 R12 R11 R10 R14 0 0 0 0 . . . 1 1 1 1 ABP2 0 0 1 1 BSC2 0 0 1 1 R14 ABP1 0 1 0 1 ANTIBACKLASH PULSE WIDTH 3.0ns 1.3ns 6.0ns 3.0ns LOCK DETECT PRECISION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. BAND SELECT CLOCK DIVIDER 1 2 4 8 04414-0-017 RSV CONTROL BITS 14-BIT REFERENCE COUNTER Rev. A | Page 15 of 24 R9 R13 0 0 0 0 . . . 1 1 1 1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 R12 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... R3 0 0 0 0 . . . 1 1 1 1 R2 0 0 1 1 . . . 0 0 1 1 R1 0 1 0 1 . . . 0 1 0 1 DB1 DB0 C2 (0) C1 (1) DIVIDE RATIO Not Allowed 1 2 3 . . . 16380 16381 16382 16383 ADF4360-1 CONTROL LATCH With (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Charge Pump Currents Prescaler Value CPI3, CPI2, and CPI1 in the ADF4360 family determine Current Setting 1. In the ADF4360 family, P2 and P1 in the control latch set the prescaler values. CPI6, CPI5, and CPI4 determine Current Setting 2. See the truth table in Table 7. Power-Down Output Power Level DB21 (PD2) and DB20 (PD1) provide programmable powerdown modes. Bits PL1 and PL2 set the output power level of the VCO. See the truth table in Table 7. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into Bit PD1 (on the condition that a 1 has also been loaded to PD2), the device will go into power-down on the second rising edge of the R counter output, after LE goes high. When the CE pin is low, the device is immediately disabled regardless of the state of PD1 or PD2. Mute-Till-Lock Detect When a power-down is activated (either in synchronous or asynchronous mode), the following events occur: DB11 of the control latch in the ADF4360 family is the Mute-TillLock Detect bit. This function, when enabled, ensures that the RF outputs are not switched on until the PLL is locked. CP Gain DB10 of the control latch in the ADF4360 family is the Charge Pump Gain bit. When it is programmed to a 1, Current Setting 2 is used. When it is programmed to a 0, Current Setting 1 is used. Charge Pump Three-State This bit puts the charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. Phase Detector Polarity The PDP bit in the ADF4360 family sets the phase detector polarity. The positive setting enabled by programming a 1 is used when using the on-chip VCO with a passive loop filter or with an active noninverting filter. It can also be set to 0. This is required if an active inverting loop filter is used. • All active dc current paths are removed. • The R, N, and timeout counters are forced to their load state conditions. • The charge pump is forced into three-state mode. MUXOUT Control • The digital lock detect circuitry is reset. The on-chip multiplexer is controlled by M3, M2, and M1. See the truth table in Table 7. • The RF outputs are debiased to a high impedance state. Counter Reset • The reference input buffer circuitry is disabled. • The input register remains active and capable of loading and latching data. DB4 is the counter reset bit for the ADF4360 family. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0. Core Power Level PC1 and PC2 set the power level in the VCO core. The recommended setting is 15 mA. See the truth table in Table 7. Rev. A | Page 16 of 24 ADF4360-1 N COUNTER LATCH R COUNTER LATCH With (C2, C1) = (1, 0), the N counter latch is programmed. Table 8 shows the input data format for programming the N counter latch. With (C2, C1) = (0, 1), the R counter latch is programmed. Table 9 shows the input data format for programming the R counter latch. A Counter Latch R Counter A5 to A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111). R1 to R14 set the counter divide ratio. The divide range is 1 (00......001) to 16383 (111......111). Reserved Bits Antibacklash Pulse Width DB7 is a spare bit and has been designated as Reserved. It should be programmed to 0. DB16 and DB17 set the antibacklash pulse width. B Counter Latch DB18 is the lock detect precision bit and sets the number of references cycles with less than 15 ns phase error for entering the locked state. With LDP at 1, five cycles are taken, and with LDP at 0, three cycles are taken. Lock Detect Precision B13 to B1 program the B counter. The divide range is 3 (00.....0011) to 8191 (11....111). Overall Divide Range The overall divide range is defined by ((P × B) + A), where P is the prescaler value. CP Gain DB21 of the N counter latch in the ADF4360 family is the charge pump gain bit. When this is programmed to 1, Current Setting 2 is used. When programmed to 0, Current Setting 1 is used. This bit can also be programmed through DB10 of the control latch. The bit will always reflect the latest value written to it, whether this is through the control latch or the N counter latch. Test Mode Bit DB19 is the test mode bit (TMB) and should be set to 0. With TMB = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, R counter latch, and N counter latch. Note that test modes are for factory testing only and should not be programmed by the user. Band Select Clock DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2 function is chosen. When it is set to 0, normal operation occurs. These bits set a divider for the band select logic clock input. The output of the R counter is by default the value used to clock the band select logic, but if this value is too high (>1 MHz), a divider can be switched on to divide the R counter output to a smaller value (see Table 9). Divide-by-2 Select Reserved Bits DB23 is the divide-by-2 select bit. When programmed to 1, the divide-by-2 output is selected as the prescaler input. When set to 0, the fundamental is used as the prescaler input. For example, using the output divide-by-2 feature and a PFD frequency of 200 kHz, the user will need a value of N = 12,000 to generate 1.2 GHz. With the divide-by-2 select bit high, the user may keep N = 6,000. DB23 to DB22 are spare bits and have been designated as Reserved. They should be programmed to 0. Divide-by-2 Rev. A | Page 17 of 24 ADF4360-1 APPLICATIONS DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 16 shows how ADI parts can be used to implement such a system. The LO ports of the AD8349 can be driven differentially from the complementary RFOUTA and RFOUTB outputs of the ADF4360-1. This gives a better performance than a singleended LO driver and eliminates the often necessary use of a balun to convert from a single-ended LO input to the more desirable differential LO inputs for the AD8349. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 1.09°. The circuit block diagram shows the AD9761 TxDAC® being used with the AD8349. The use of dual integrated DACs, such as the AD9761 with its specified ±0.02 dB and ±0.004 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4360-1, which allows levels from −13 dBm to −6 dBm from each output. The local oscillator is implemented using the ADF4360-1. The low-pass filter was designed using ADIsimPLL for a channel spacing of 1 MHz and an open-loop bandwidth of 25 kHz. The frequency range of the ADF4360-1 (2.05 GHz to 2.45 GHz) makes it ideally suited for implementation of a Bluetooth® transceiver. The RF output is designed to drive a 50 Ω load but must be accoupled, as shown in Figure 16. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power from the modulator will be approximately 2 dBm. REFIO IOUTA MODULATED DIGITAL DATA LOW-PASS FILTER IOUTB AD9761 TxDAC QOUTA LOW-PASS FILTER QOUTB FSADJ 2kΩ VVCO LOCK DETECT VDD IBBP 6 SPI COMPATIBLE SERIAL BUS FREFIN 21 2 23 CLK 18 DATA 19 LE 12 CC 13 1nF 3.9kΩ IBBN TO RF PA 10nF 680pF 330pF AD8349 2kΩ QBBP ADF4360-1 VVCO QBBN 47nH RSET 47nH 1.5pF 3.9nH RFOUTA 4 4.7kΩ CPGND 1 VPS2 100pF VVCO DVDD AVDD CE MUXOUT VTUNE 7 14 CN CP 24 1nF 1nF 16 REFIN 51Ω 17 VPS1 20 3 AGND 8 9 10 LOIN DGND RFOUTB 5 11 22 15 LOIP 1.5pF 3.9nH Figure 16. Direct Conversion Modulator Rev. A | Page 18 of 24 PHASE SPLITTER 04414-0-019 10µF ADF4360-1 FIXED FREQUENCY LO ADuC812 Interface Figure 17 shows the ADF4360-1 used as a fixed frequency LO at 2.2 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360-1 is 8 MHz. Since using a larger PFD frequency allows users to use a smaller N, the in-band phase noise is reduced to as low as possible, –99 dBc/Hz. The 40 kHz bandwidth is chosen to be just greater than the point at which the open-loop phase noise of the VCO is –99 dBc/Hz, thus giving the best possible integrated noise. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 0.3°. The reference frequency is from a 16 MHz TCXO from Fox, thus an R value of 2 is programmed. Taking into account the high PFD frequency and its effect on the band select logic, the band select clock divider is enabled. In this case, a value of 8 is chosen. A very simple pull-up resistor and dc blocking capacitor complete the RF output stage. Figure 18 shows the interface between the ADF4360 family and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4360 family needs a 24-bit word, which is accomplished by writing three 8bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. 6 10µF FOX 801BE-160 16MHz 2 23 620Ω 51Ω 13 RSET 1 51Ω 100pF RFOUTA 4 4.7kΩ AGND 3 8 9 10 DGND RF OUTB 5 11 22 15 04414-0-024 ADSP-2181 Interface 100pF 04414-0-023 SPI COMPATIBLE SERIAL BUS VVCO CPGND MUXOUT (Lock Detect) I/O port lines on the ADuC812 are also used to control powerdown (CE input) and detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the described mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. 15.0nF 3.3nF ADF4360-1 12 CC 1nF ADF4360-x CE Figure 18. ADuC812 to ADF4360-x Interface 17 CLK 19 LE SCLK SDATA LE I/O Ports 20 VVCO DVDD AVDD CE MUXOUT VTUNE 7 14 CN CP 24 1nF 1nF 16 REFIN 51Ω 18 DATA ADuC812 LOCK DETECT VVDD 21 MOSI Figure 17. Fixed Frequency LO POWER-UP Figure 19 shows the interface between the ADF4360 family and the ADSP-21xx digital signal processor. The ADF4360 family needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. After power-up, the part needs three writes for normal operation. The correct sequence is to the R counter latch, followed by the control latch, and N counter latch. SCLOCK MOSI INTERFACING TFS ADSP-21xx The ADF4360 family has a simple SPI® compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that have been clocked into the appropriate register on each rising edge of CLK will get transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means the maximum update rate possible is 833 kHz or one update every 1.2 microseconds. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. I/O Ports SCLK SDATA LE ADF4360-x CE MUXOUT (Lock Detect) 04414-0-025 VVCO SCLOCK Figure 19. ADSP-21xx to ADF4360-x Interface Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. Rev. A | Page 19 of 24 ADF4360-1 VVCO The bottom of the chip-scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. 47nH 1.5pF 3.9nH RFOUT 50Ω Figure 21. Optimum ADF4360-1 Output Stage If the user does not need the differential outputs available on the ADF4360, the user may either terminate the unused output or combine both outputs using a balun. The circuit in Figure 22 shows how best to combine the outputs. VVCO The user should connect the printed circuit thermal pad to AGND. This is internally connected to AGND. 1nH RFOUTA OUTPUT MATCHING 3.6nH 47nH 1.5pF 10pF 3.6nH There are a number of ways to match the output of the ADF4360-1 for optimum operation; the most basic is to use a 50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series as shown Figure 20. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in the circuit below typically gives−6 dBm output power into a 50 Ω load. VVCO 51Ω 50Ω 04414-0-020 100pF RFOUT Figure 20. Simple ADF4360-1 Output Stage A better solution is to use a shunt inductor (acting as an RF choke) to VVCO. This gives a better match and hence more output power. Additionally, a series inductor is added after the dc bypass capacitor to provide a resonant LC circuit. This tunes the oscillator output and provides approximately 10 dB additional rejection of the second harmonic. The shunt inductor needs to be a relatively high value (>40 nH). RFOUTB 50Ω 1nH 1.5pF 04414-0-022 The leads on the chip-scale package (CP-24) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. The lead should be centered on the pad to ensure that the solder joint size is maximized. Experiments have shown that Figure 21 provides an excellent match to 50 Ω over the operating range of the ADF4360-1. This gives approximately −4 dBm output power across the frequency range of the ADF4360-1. Both single-ended architectures can be examined using the EVAL_ADF4360-1EB1 evaluation board. 04414-0-021 PCB DESIGN GUIDELINES FOR CHIP-SCALE PACKAGE Figure 22. Balun for Combining ADF4360-1 RF Outputs The circuit in Figure 22 is a lumped lattice type LC balun. It is designed for a center frequency of 2.2 GHz and outputs 1.0 dBm at this frequency. The series 1 nH inductor is used to tune out any parasitic capacitance due to the board layout from each input, and the remainder of the circuit is used to shift the output of one RF input by 90° and the second by −90°, thus combining the two. The action of the 3.6 nH inductor and the 1.5 pF capacitor accomplish this. The 47 nH is used to provide an RF choke in order to feed the supply voltage, and the 10 pF capacitor provides the necessary dc block. To ensure good RF performance, the circuits in Figure 21 and Figure 22 were implemented with Coilcraft 0402/0603 inductors and AVX 0402 thin-film capacitors. Alternatively, instead of the LC balun shown above, both outputs may be combined using a 180° rat-race coupler. Rev. A | Page 20 of 24 ADF4360-1 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ PIN 1 INDICATOR 0.60 MAX 0.50 BSC 3.75 BSC SQ TOP VIEW 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE PIN 1 INDICATOR 24 1 19 18 2.25 2.10 SQ 1.95 EXPOSED PAD (BOTTOM VIEW) 13 12 7 6 0.25 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 23. 24-Lead Lead Frame Chip-Scale Package [LFCSP] (CP-24-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Frequency Range Package Option ADF4360-1BCP ADF4360-1BCPRL ADF4360-1BCPRL7 EVAL-ADF4360-1EB1 −40°C to +85°C −40°C to +85°C −40°C to +85°C 2050 MHz to 2450 MHz 2050 MHz to 2450 MHz 2050 MHz to 2450 MHz CP-24-1 CP-24-1 CP-24-1 Evaluation Board Rev. A | Page 21 of 24 ADF4360-1 NOTES Rev. A | Page 22 of 24 ADF4360-1 NOTES Rev. A | Page 23 of 24 ADF4360-1 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04414–0–6/04(A) Rev. A | Page 24 of 24