6-Channel, Low Noise, Low Power, 24-/16-Bit ∑-Δ ADC with On-Chip In-Amp and Reference AD7794/AD7795 FEATURES Industrial process control Instrumentation Blood analysis Smart transmitters Liquid/gas chromatography 6-digit DVM Up to 23 effective bits RMS noise: 40 nV @ 4.17 Hz, 85 nV @ 16.7 Hz Current: 400 μA typical Power-down: 1 μA maximum Low noise, programmable gain, instrumentation amp Band gap reference with 4 ppm/°C drift typical Update rate: 4.17 Hz to 470 Hz Six differential analog inputs Internal clock oscillator Simultaneous 50 Hz/60 Hz rejection Reference detect Programmable current sources On-chip bias voltage generator Burnout currents Low-side power switch Power supply: 2.7 V to 5.25 V Temperature range: B grade: –40°C to +105°C C grade: –40°C to +125°C Independent interface power supply 24-lead TSSOP 3-wire serial interface SPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK GENERAL DESCRIPTION The AD7794/AD7795 are low power, low noise, complete analog front ends for high precision measurement applications. They contain a low noise, 24-/16-bit ∑-Δ ADC with six differential inputs. The on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the ADC. Each device contains a precision, low noise, low drift internal band gap reference, and can also accept up to two external differential references. Other on-chip features include programmable excitation current sources, burnout currents, and a bias voltage generator that is used to set the commonmode voltage of a channel to AVDD/2. The low-side power switch can be used to power down bridge sensors between conversions, minimizing the system’s power consumption. The AD7794/AD7795 can operate with either an internal clock or an external clock. The output data rate from each part can vary from 4.17 Hz to 470 Hz. Both parts operate with a power supply from 2.7 V to 5.25 V. The B-grade parts (AD7794 and AD7795) are specified for a temperature range of −40°C to +105°C while the C-grade part (AD7794) is specified for a temperature range of −40°C to +125°C. They consume a current of 400 μA typical and are housed in a 24-lead TSSOP. APPLICATIONS Temperature measurement Pressure measurement Weigh scales Strain gage transducers Gas analysis FUNCTIONAL BLOCK DIAGRAM GND AVDD AIN4(+)/REFIN2(+) REFIN1(+) AIN4(–)/REFIN2(–) REFIN1(–) VBIAS VDD AIN1(+) AIN1(–) AIN2(+) AIN2(–) AIN3(+) AIN3(–) AIN5(+)/IOUT2 AIN5(–)/IOUT1 AIN6(+)/P1 AIN6(–)/P2 REFERENCE DETECT BAND GAP REFERENCE GND BUF Σ-Δ ADC IN-AMP MUX SERIAL INTERFACE AND LOGIC CONTROL DOUT/RDY DIN SCLK CS GND TEMP SENSOR INTERNAL CLOCK DVDD AD7794/AD7795 VDD PSW GND CLK 04854-001 AD7794: 24-BIT ADC AD7795: 16-BIT ADC Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved. AD7794/AD7795 TABLE OF CONTENTS Features .............................................................................................. 1 Full-Scale Register...................................................................... 25 Applications....................................................................................... 1 ADC Circuit Information.............................................................. 26 General Description ......................................................................... 1 Overview ..................................................................................... 26 Functional Block Diagram .............................................................. 1 Digital Interface.......................................................................... 28 Revision History ............................................................................... 2 Circuit Description......................................................................... 31 Specifications..................................................................................... 3 Analog Input Channel ............................................................... 31 Timing Characteristics..................................................................... 8 Instrumentation Amplifier........................................................ 31 Timing Diagrams.............................................................................. 9 Bipolar/Unipolar Configuration .............................................. 31 Absolute Maximum Ratings.......................................................... 10 Data Output Coding .................................................................. 32 ESD Caution................................................................................ 10 Burnout Currents ....................................................................... 32 Pin Configuration and Function Descriptions........................... 11 Excitation Currents .................................................................... 32 RMS Noise and Resolution Specifications .................................. 13 Bias Voltage Generator .............................................................. 32 Chop Enabled.............................................................................. 13 Reference ..................................................................................... 32 Chop Disabled ............................................................................ 15 Reference Detect......................................................................... 33 Typical Performance Characteristics ........................................... 16 Reset ............................................................................................. 33 On-Chip Registers .......................................................................... 17 AVDD Monitor ............................................................................. 33 Communications Register......................................................... 17 Calibration................................................................................... 33 Status Register ............................................................................. 18 Grounding and Layout .............................................................. 34 Mode Register ............................................................................. 19 Applications Information .............................................................. 35 Configuration Register .............................................................. 22 Flowmeter.................................................................................... 35 Data Register ............................................................................... 24 Outline Dimensions ....................................................................... 36 ID Register................................................................................... 24 Ordering Guide .......................................................................... 36 IO Register................................................................................... 24 Offset Register............................................................................. 25 REVISION HISTORY 3/07—Rev. C to Rev. D Changes to Specifications Endnote 1............................................. 7 Changes to Status Register Section .............................................. 18 Changes to Ordering Guide .......................................................... 36 10/06—Rev. B to Rev. C Updated Format..................................................................Universal Added AD7794 C-Grade Part...........................................Universal Changes to Specifications ................................................................ 3 Changes to Ordering Guide .......................................................... 36 4/05—Rev. 0 to Rev. A Changes to Absolute Maximum Ratings........................................9 Changes to Figure 21...................................................................... 25 Changes to Data Output Coding Section.................................... 28 Changes to Calibration Section .................................................... 30 Changes to Ordering Guide .......................................................... 33 10/04—Revision 0: Initial Version 6/06—Rev. A to Rev. B Added AD7795 ...................................................................Universal Changes to Features.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to RMS Noise and Resolution Specifications Section..................................................................... 12 Changes to Table 19........................................................................ 20 Changes to ADC Circuit Information Section ........................... 25 Changes to Ordering Guide .......................................................... 35 Rev. D | Page 2 of 36 AD7794/AD7795 SPECIFICATIONS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 CHOP ENABLED Output Update Rate No Missing Codes 2 AD7794 AD7795 Resolution RMS Noise and Update Rates Integral Nonlinearity Offset Error 3 Offset Error Drift vs. Temperature 4 Full-Scale Error3, 5 Gain Drift vs. Temperature4 Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode In-Amp Active Common-Mode Voltage, VCM Analog Input Current Buffered Mode or In-Amp Active Average Input Current2 AD7794B/AD7795B AD7794C Average Input Current Drift Unbuffered Mode Average Input Current Average Input Current Drift Normal Mode Rejection2, 6 Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz AD7794/AD7795 Unit Test Conditions/Comments 4.17 to 470 Hz nom Settling time = 2/output update rate 24 16 Bits min Bits min fADC ≤ 242 Hz See the RMS Noise and Resolution Specifications section See the RMS Noise and Resolution Specifications section ±15 ±1 ±10 ±10 ±1 ±3 100 ppm of FSR max μV typ nV/°C typ μV typ ppm/°C typ ppm/°C typ dB min ±VREF/gain V nom VREF = REFIN(+) − REFIN(−), or internal reference, gain = 1 to 128 GND − 30 mV AVDD + 30 mV GND + 100 mV AVDD − 100 mV GND + 300 mV AVDD − 1.1 0.5 V min V max V min V max V min V max V min Gain = 1 or 2 ±1 ±250 ±1 ±3 ±2 ±3 ±2 nA max pA max nA max nA max nA max nA max pA/°C typ ±400 ±50 nA/V typ pA/V/°C typ 65 80 90 dB min dB min dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 80 94 90 dB min dB min dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 Rev. D | Page 3 of 36 Gain = 1 to 16, external reference Gain = 32 to 128, external reference AIN = 1 V/gain, gain ≥ 4, external reference Gain = 1 or 2 Gain = 4 to 128 VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 Gain = 1 or 2, update rate < 100 Hz Gain = 4 to 128, update rate < 100 Hz AIN6(+)/AIN6(−) Gain = 1 or 2, update rate < 100 Hz Gain = 4 to 128, update rate < 100 Hz AIN6(+)/AIN6(−) Gain = 1 or 2 Input current varies with input voltage AD7794/AD7795 Parameter 1 Common-Mode Rejection AD7794B/AD7795B @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 AD7794C @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 CHOP DISABLED Output Update Rate No Missing Codes2 AD7794 AD7795 Resolution RMS Noise and Update Rates Integral Nonlinearity Offset Error3 Offset Error Drift vs. Temperature4 Full-Scale Error3, 5 Gain Drift vs. Temperature4 Power Supply Rejection ANALOG INPUTS Differential Input Voltage Ranges Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode In-Amp Active Common-Mode Voltage, VCM Analog Input Current Buffered Mode or In-Amp Active Average Input Current2 AD7794B/AD7795B AD7794C Average Input Current Drift Unbuffered Mode Average Input Current Average Input Current Drift AD7794/AD7795 Unit Test Conditions/Comments 100 100 100 dB min dB min dB min AIN = 1 V/gain, gain ≥ 4 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 97 97 97 dB min dB min dB min AIN = 1 V/gain, gain ≥ 4 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 4.17 to 470 Hz nom Settling time = 1/output update rate 24 16 Bits min Bits min fADC ≤ 123 Hz See the RMS Noise and Resolution Specifications section See the RMS Noise and Resolution Specifications section ±15 ±100/gain ±100/gain 10 ±10 ±1 ±3 100 ppm of FSR max μV typ nV/°C typ nV/°C typ μV typ ppm/°C typ ppm/°C typ dB typ ±VREF/gain V nom VREF = REFIN(+) − REFIN(−), or internal reference, gain = 1 to 128 GND − 30 mV AVDD + 30 mV GND + 100 mV AVDD − 100 mV GND + 300 mV AVDD − 1.1 0.2 + (gain/2 × (AIN(+) − AIN(−))) AVDD − 0.2 − (gain/2 × (AIN(+) − AIN(−))) V min V max V min V max V min V max V min Gain = 1 or 2 ±1 ±250 ±1 ±3 ±2 ±3 ±2 nA max pA max nA max nA max nA max nA max pA/°C typ ±400 ±50 nA/V typ pA/V/°C typ Without calibration Gain = 1 to 16 Gain = 32 to 128 Gain = 1 to 16, external reference Gain = 32 to 128, external reference AIN = 1 V/gain, gain ≥ 4, external reference Gain = 1 or 2 Gain = 4 to 128 AMP − CM = 1, VCM = (AIN(+) + AIN(–))/2, gain = 4 to 128 V max Rev. D | Page 4 of 36 Gain = 1 or 2 Gain = 4 to 128 AIN6(+)/AIN6(−) Gain = 1 or 2 Gain = 4 to 128 AIN6(+)/AIN6(−) Gain = 1 or 2 Input current varies with input voltage AD7794/AD7795 Parameter 1 Normal Mode Rejection2, 6 Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Common-Mode Rejection AD7794B/AD7795B @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 AD7794C @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 CHOP ENABLED or DISABLED REFERENCE INPUT Internal Reference Internal Reference Initial Accuracy Internal Reference Drift2 Power Supply Rejection External Reference External REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels EXCITATION CURRENT SOURCES (IEXC1 and IEXC2) Output Current Initial Tolerance at 25°C Drift Current Matching Drift Matching Line Regulation (AVDD) Load Regulation Output Compliance AD7794/AD7795 Unit Test Conditions/Comments 60 78 86 dB min dB min dB min 70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 60 94 90 dB min dB min dB min 70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000 100 100 100 dB min dB min dB min AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 97 97 97 dB min dB min dB min AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000 1.17 ± 0.01% V min/max AVDD = 4 V, TA = 25°C 4 15 85 ppm/°C typ ppm/°C max dB typ 2.5 0.1 AVDD V nom V min V max GND − 30 mV AVDD + 30 mV 400 V min V max nA/V typ ±0.03 nA/V/°C typ 100 0.3 0.65 dB typ V min V max 10/210/1000 ±5 200 ±0.5 50 2 0.2 AVDD − 0.65 AVDD − 1.1 GND − 30 mV μA nom % typ ppm/°C typ % typ ppm/°C typ %/V typ %/V typ V max V max V min REFIN = REFIN(+) − REFIN(−) When VREF = AVDD, the differential input must be limited to 0.9 × VREF/gain if the in-amp is active Same as for analog inputs Rev. D | Page 5 of 36 NOXREF bit active if VREF < 0.3 V Matching between IEXC1 and IEXC2, VOUT = 0 V AVDD = 5 V ± 5% Current sources programmed to 10 μA or 210 μA Current sources programmed to 1 mA AD7794/AD7795 Parameter 1 BIAS VOLTAGE GENERATOR VBIAS VBIAS Generator Start-Up Time TEMPERATURE SENSOR Accuracy Sensitivity LOW-SIDE POWER SWITCH RON Allowable Current2 DIGITAL OUTPUTS (P1 and P2) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 INTERNAL/EXTERNAL CLOCK Internal Clock Frequency2 Duty Cycle External Clock Frequency Duty Cycle LOGIC INPUTS CS2 VINL, Input Low Voltage VINH, Input High Voltage SCLK (Schmitt-Triggered Input), CLK, and DIN2 AD7794B/AD7795B VT(+) VT(−) VT(+) to VT(−) VT(+) VT(−) VT(+) to VT(−) AD7794C VT(+) VT(−) VT(+) to VT(−) VT(+) VT(−) VT(+) to VT(−) Input Currents Input Capacitance AD7794/AD7795 Unit AVDD/2 V nom ms/nF typ Test Conditions/Comments Dependent on the capacitance connected to AIN; See Figure 11 ±2 0.81 °C typ mV/°C typ Applies if user calibrates the temperature sensor 7 9 30 Ω max Ω max mA max AVDD = 5 V AVDD = 3 V Continuous current AVDD − 0.6 0.4 4 0.4 V min V max V min V max AVDD = 3 V, ISOURCE = 100 μA AVDD = 3 V, ISINK = 100 μA AVDD = 5 V, ISOURCE = 200 μA AVDD = 5 V, ISINK = 800 μA 64 ± 3% 50:50 kHz min/max % typ 64 kHz nom 45:55 to 55:45 % typ 0.8 0.4 2.0 V max V max V min DVDD = 5 V DVDD = 3 V DVDD = 3 V or 5 V 1.4/2 0.8/1.7 0.1/0.17 0.9/2 0.4/1.35 0.06/0.13 V min/max V min/max V min/max V min/max V min/max V min/max DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V 1.35/2.05 0.8/1.9 0.1/0.19 0.9/2 0.4/1.35 0.06/0.15 ±10 10 V min/max V min/max V min/max V min/max V min/max V min/max μA max pF typ DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V VIN = DVDD or GND All digital inputs Rev. D | Page 6 of 36 A 128 kHz external clock can be used if the divide-by-2 function is used (Bit CLK1 = CLK0 = 1) Applies for external 64 kHz clock, a 128 kHz clock can have a less stringent duty cycle AD7794/AD7795 Parameter 1 LOGIC OUTPUT (INCLUDING CLK) VOH, Output High Voltage2 VOL, Output Low Voltage2 VOH, Output High Voltage2 VOL, Output Low Voltage2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD to GND DVDD to GND Power Supply Currents IDD Current IDD (Power-Down Mode) AD7794/AD7795 Unit Test Conditions/Comments DVDD − 0.6 0.4 4 0.4 ±10 10 Offset binary V min V max V min V max μA max pF typ DVDD = 3 V, ISOURCE = 100 μA DVDD = 3 V, ISINK = 100 μA DVDD = 5 V, ISOURCE = 200 μA DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY), 800 μA (CLK) 1.05 × FS −1.05 × FS 0.8 × FS 2.1 × FS V max V min V min V max 2.7/5.25 2.7/5.25 V min/max V min/max 140 μA max 185 μA max 400 μA max 500 μA max 1 2 μA max μA max 1 110 μA typ @ AVDD = 3 V, 125 μA typ @ AVDD = 5 V, unbuffered mode, external reference 130 μA typ @ AVDD = 3 V, 165 μA typ @ AVDD = 5 V, buffered mode, gain = 1 or 2, external reference 300 μA typ @ AVDD = 3 V, 350 μA typ @ AVDD = 5 V, gain = 4 to 128, external reference 400 μA typ @ AVDD = 3 V, 450 μA typ @ AVDD = 5 V, gain = 4 to 128, internal reference AD7794B, AD7795B AD7794C Temperature range: B Grade: −40°C to +105°C, C Grade: −40°C to +125°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), commonmode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AVDD – 1.6 V typically. In addition, the offset error and offset error drift degrade at these update rates when chopping is disabled. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AVDD − 1.6 V. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale, and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled. Rev. D | Page 7 of 36 AD7794/AD7795 TIMING CHARACTERISTICS AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. Parameter 1, 2 t3 t4 Read Operation t1 t2 3 t5 5, 6 t6 t7 Write Operation t8 t9 t10 t11 Limit at TMIN, TMAX (B Version) 100 100 Unit ns min ns min Conditions/Comments SCLK high pulse width SCLK low pulse width 0 60 80 0 60 80 10 80 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge 0 30 25 0 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, therefore, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. 2 ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) Figure 2. Load Circuit for Timing Characterization Rev. D | Page 8 of 36 04854-002 50pF AD7794/AD7795 TIMING DIAGRAMS CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 04854-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. D | Page 9 of 36 04854-004 DIN (I) AD7794/AD7795 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND DVDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND AIN/Digital Input Current Operating Temperature Range B Grade C Grade Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +105°C −40°C to +125°C −65°C to +150°C 150°C 97.9°C/W 14°C/W 215°C 220°C Rev. D | Page 10 of 36 AD7794/AD7795 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 24 DIN CLK 2 23 DOUT/RDY CS 3 NC 4 AIN6(+)/P1 5 AD7794/ AD7795 21 AVDD 20 GND 19 PSW TOP VIEW AIN1(+) 7 (Not to Scale) 18 AIN4(–)/REFIN2(–) AIN1(–) 8 17 AIN4(+)/REFIN2(+) AIN2(+) 9 16 AIN5(–)/IOUT1 AIN2(–) 10 15 AIN5(+)/IOUT2 AIN3(+) 11 14 REFIN1(–) AIN3(–) 12 13 REFIN1(+) NC = NO CONNECT 04854-005 AIN6(–)/P2 6 22 DVDD Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 CLK 3 CS 4 5 NC AIN6(+)/P1 6 AIN6(−)/P2 7 8 9 10 11 12 13 AIN1(+) AIN1(−) AIN2(+) AIN2(−) AIN3(+) AIN3(−) REFIN1(+) 14 15 REFIN1(−) AIN5(+)/IOUT2 16 AIN5(−)/IOUT1 17 AIN4(+)/REFIN2(+) Description Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. No Connect. Analog Input/Digital Output Pin. AIN6(+) is the positive terminal of the differential analog input pair, AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AVDD and GND. Analog Input/Digital Output Pin. AIN6(−) is the negative terminal of the differential analog input pair, AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AVDD and GND. Analog Input. AIN1(+) is the positive terminal of the differential analog input pair, AIN1(+)/AIN1(−). Analog Input. AIN1(−) is the negative terminal of the differential analog input pair, AIN1(+)/AIN1(−). Analog Input. AIN2(+) is the positive terminal of the differential analog input pair, AIN2(+)/AIN2(−). Analog Input. AIN2(−) is the negative terminal of the differential analog input pair, AIN2(+)/AIN2(−). Analog Input. AIN3(+) is the positive terminal of the differential analog input pair, AIN3(+)/AIN3(−). Analog Input. AIN3(−) is the negative terminal of the differential analog input pair, AIN3(+)/AIN3(−). Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between GND and AVDD − 0.1 V. Analog Input/Output of Internal Excitation Current Source. AIN5(+) is the positive terminal of the differential analog input pair AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. Analog Input/Output of Internal Excitation Current Source. AIN5(−) is the negative terminal of the differential analog input pair, AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be switched to this output. Analog Input/Positive Reference Input. AIN4(+) is the positive terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin also functions as a positive reference input for REFIN2. REFIN2(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Rev. D | Page 11 of 36 AD7794/AD7795 Pin No. 18 Mnemonic AIN4(−)/REFIN2(−) 19 20 21 22 PSW GND AVDD DVDD 23 DOUT/RDY 24 DIN Description Analog Input/Negative Reference Input. AIN4(−) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(−). This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere between GND and AVDD − 0.1 V. Low-Side Power Switch to GND. Ground Reference Point. Supply Voltage, 2.7 V to 5.25 V. Serial Interface Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, the serial interface operates at 3 V with AVDD at 5 V or vice versa. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC with the register selection bits of the communications register identifying the appropriate register. Rev. D | Page 12 of 36 AD7794/AD7795 RMS NOISE AND RESOLUTION SPECIFICATIONS The AD7794/AD7795 can be operated with chop enabled or chop disabled, allowing the ADC to be optimized for switching time or drift performance. With chop enabled, the settling time is two times the conversion time. However, the offset is continuously removed by the ADC leading to low offset and low offset drift. With chop disabled, the allowable update rates are the same as in chop enable mode. However, the settling time now equals the conversion time. With chop disabled, the offset is not removed by the ADC, so periodic offset calibrations can be required to remove offset due to drift. CHOP ENABLED External Reference Table 5 shows the AD7794/AD7795 rms noise for some update rates and gain settings. The numbers given are for the bipolar input range with an external 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 6 and Table 7 show the effective resolution, while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest LSB. Table 5. RMS Noise (μV) vs. Gain and Output Update Rate Using an External 2.5 V Reference with Chop Enabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 0.64 1.04 1.55 2.3 2.95 4.89 11.76 11.33 Gain of 2 0.6 0.96 1.45 2.13 2.85 4.74 9.5 9.44 Gain of 4 0.29 0.38 0.54 0.74 0.92 1.49 4.02 3.07 Gain of 8 0.22 0.26 0.36 0.5 0.58 1 1.96 1.79 Gain of 16 0.1 0.13 0.18 0.23 0.29 0.48 0.88 0.99 Gain of 32 0.065 0.078 0.11 0.17 0.2 0.32 0.45 0.63 Gain of 64 0.039 0.057 0.087 0.124 0.153 0.265 0.379 0.568 Gain of 128 0.041 0.055 0.086 0.118 0.144 0.283 0.397 0.593 Table 6. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an External 2.5 V Reference with Chop Enabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 23 (20.5) 22 (19.5) 21.5 (19) 21 (18.5) 20.5 (18) 20 (17.5) 18.5 (16) 18.5 (16) Gain of 2 22 (19.5) 21.5 (19) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 18 (15.5) 18 (15.5) Gain of 4 22 (19.5) 21.5 (19) 21 (18.5) 20.5 (18) 20.5 (18) 19.5 (17) 18 (15.5) 18.5 (16) Gain of 8 21.5 (19) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 19 (16.5) 18 (15.5) 18.5 (16) Gain of 16 21.5 (19) 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16) 18 (15.5) Gain of 32 21 (18.5) 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) Gain of 64 21 (18.5) 20.5 (18) 20 (17.5) 19 (16.5) 19 (16.5) 18 (15.5) 17.5 (15) 17 (14.5) Gain of 128 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 16.5 (14) 16 (13.5) Table 7. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an External 2.5 V Reference with Chop Enabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) Gain of 2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15.5) Gain of 4 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (16) Gain of 8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (16) Rev. D | Page 13 of 36 Gain of 16 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) Gain of 32 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) Gain of 64 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (14.5) Gain of 128 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (14) 16 (13.5) AD7794/AD7795 Internal Reference Table 8 shows the AD7794/AD7795 rms noise for some of the update rates and gain settings. The numbers given are for the bipolar input range with the internal 1.17 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 9 and Table 10 show the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and rounded to the nearest LSB. Table 8. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Enabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 0.81 1.18 1.96 2.99 3.6 5.83 11.22 12.46 Gain of 2 0.67 1.11 1.72 2.48 3.25 5.01 8.64 10.58 Gain of 4 0.32 0.41 0.55 0.83 1.03 1.69 2.69 4.58 Gain of 8 0.2 0.25 0.36 0.48 0.65 0.96 1.9 2 Gain of 16 0.13 0.16 0.25 0.33 0.46 0.67 1.04 1.27 Gain of 32 0.065 0.078 0.11 0.17 0.2 0.32 0.45 0.63 Gain of 64 0.04 0.058 0.088 0.13 0.15 0.25 0.35 0.50 Gain of 128 0.039 0.059 0.088 0.12 0.15 0.26 0.34 0.49 Table 9. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Enabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) 19.5 (17) 18.5 (16) 17.5 (15) 17.5 (15) Gain of 2 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 17 (14.5) Gain of 4 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 17.5 (15) 17 (14.5) Gain of 8 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 19 (16.5) 18 (15.5) 17 (14.5) 17 (14.5) Gain of 16 20 (17.5) 20 (17.5) 19 (16.5) 19 (16.5) 18.5 (16) 17.5 (15) 17 (14.5) 17 (14.5) Gain of 32 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 18.5 (16) 18 (15.5) 17.5 (15) 17 (14.5) Gain of 64 20 (17.5) 19 (16.5) 18.5 (16) 18 (15.5) 18 (15.5) 17 (14.5) 16.5 (14) 16 (13.5) Gain of 128 19 (16.5) 18 (15.5) 17.5 (15) 17 (14.5) 17 (14.5) 16 (13.5) 15.5 (13) 15 (12.5) Table 10. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Enabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (15) Gain of 2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (14.5) Gain of 4 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5) Gain of 8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (14.5) Rev. D | Page 14 of 36 Gain of 16 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5) 16 (14.5) Gain of 32 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (14.5) Gain of 64 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15.5) 16 (14.5) 16 (14) 16 (13.5) Gain of 128 16 (16) 16 (15.5) 16 (15) 16 (14.5) 16 (14.5) 16 (13.5) 15.5 (13) 15 (12.5) AD7794/AD7795 CHOP DISABLED With chop disabled, the switching time or settling time is reduced by a factor of two. However, periodic offset calibrations may now be required to remove offset and offset drift. When chop is disabled, the AMP-CM bit in the mode register should be set to 1. This limits the allowable common-mode voltage that can be used. However, the common-mode rejection degrades if the bit is not set. Table 11 shows the rms noise of the AD7794/AD7795 for some of the update rates and gain settings with chop disabled. The numbers given are for the bipolar input range with the internal 1.17 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 12 and Table 13 show the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and rounded to the nearest LSB. Table 11. RMS Noise (μV) vs. Gain and Output Update Rate Using an Internal 1.17 V Reference with Chop Disabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 1.22 1.74 2.64 4.55 5.03 8.13 15.12 17.18 Gain of 2 0.98 1.53 2.44 3.52 4.45 7.24 13.18 14.63 Gain of 4 0.33 0.49 0.79 1.11 1.47 2.27 3.77 8.86 Gain of 8 0.18 0.29 0.48 0.66 0.81 1.33 2.09 2.96 Gain of 16 0.13 0.21 0.33 0.46 0.58 0.96 1.45 1.92 Gain of 32 0.062 0.1 0.16 0.21 0.27 0.48 0.64 0.89 Gain of 64 0.053 0.079 0.13 0.17 0.2 0.36 0.5 0.69 Gain of 128 0.051 0.07 0.12 0.16 0.22 0.37 0.47 0.7 Table 12. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7794 Using an Internal 1.17 V Reference with Chop Disabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 21 (18.5) 20.5 (18) 20 (17.5) 19 (16.5) 19 (16.5) 18 (15.5) 17 (14.5) 17 (14.5) Gain of 2 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 17.5 (15) 16.5 (14) 16.5 (14) Gain of 4 21 (18.5) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 16 (13.5) Gain of 8 20.5 (18) 20 (17.5) 19 (16.5) 19 (16.5) 18.5 (16) 17.5 (15) 17 (14.5) 16.5 (14) Gain of 16 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 16.5 (14) 16 (13.5) Gain of 32 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 17 (14.5) 16.5 (14) Gain of 64 19.5 (17) 19 (16.5) 18 (15.5) 17.5 (15) 17.5 (15) 16.5 (14) 16 (13.5) 15.5 (13) Gain of 128 18.5 (16) 18 (15.5) 17 (14.5) 17 (14.5) 16.5 (14) 15.5 (13) 15 (12.5) 14.5 (12) Table 13. Effective Resolution (Bits) vs. Gain and Output Update Rate for the AD7795 Using an Internal 1.17 V Reference with Chop Disabled Update Rate (Hz) 4.17 8.33 16.7 33.2 62 123 242 470 Gain of 1 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (14.5) Gain of 2 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (14) 16 (14) Gain of 4 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (13.5) Gain of 8 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5) 16 (14) Rev. D | Page 15 of 36 Gain of 16 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (14) 16 (13.5) Gain of 32 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 16 (14.5) 16 (14) Gain of 64 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (15) 16 (14) 16 (13.5) 15.5 (13) Gain of 128 16 (16) 16 (15.5) 16 (14.5) 16 (14.5) 16 (14) 15.5 (13) 15 (12.5) 14.5 (12) AD7794/AD7795 14 8388750 12 8388700 10 8388650 8388600 8 6 8388550 4 8388500 2 8388450 0 200 400 600 800 04854-009 OCCURRENCE 8388800 04854-006 CODE READ TYPICAL PERFORMANCE CHARACTERISTICS 0 8388068 8388100 1000 8388150 8388200 8388250 8388300 8388350 8388396 CODE READING NUMBER Figure 6. Typical Noise Plot for the AD7794 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz, Chop Enabled) Figure 9. Noise Distribution Histogram for the AD7794 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz, Chop Disabled, AMP-CM = 1) 16 14 20 10 (%) OCCURRENCE 12 8 10 6 04854-007 2 0 8388482 8388520 8388560 8388600 8388640 8388680 8388720 04854-010 4 0 –2.0 8388750 –1.2 –0.8 CODE 0.4 0.8 1.2 1.6 2.0 Figure 10. Excitation Current Matching (210 μA) at Ambient Temperature 90 8388400 80 8388350 70 POWER-UP TIME (ms) 8388450 8388300 8388250 8388200 8388150 60 50 BOOST = 0 40 30 0 200 400 600 800 10 0 1000 READING NUMBER Figure 8. Typical Noise Plot for the AD7794 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz, AMP-CM = 1, Chop Disabled) 04854-011 20 8388100 04854-008 CODE READ 0 MATCHING (%) Figure 7. Noise Distribution Histogram for the AD7794 (Internal Reference, Gain = 64, Update Rate = 16.7 Hz, Chop Enabled) 8388050 –0.4 BOOST = 1 0 200 400 600 800 1000 LOAD CAPACITANCE (nF) Figure 11. Bias Voltage Generator Power-Up Time vs. Load Capacitance Rev. D | Page 16 of 36 AD7794/AD7795 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described in the following sections. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. COMMUNICATIONS REGISTER RS2, RS1, RS0 = 0, 0, 0 The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface CR7 WEN(0) CR6 R/W(0) CR5 RS2(0) CR4 RS1(0) returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 14 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, with CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. CR3 RS0(0) CR2 CREAD(0) CR1 0(0) CR0 0(0) Table 14. Communications Register Bit Designations Bit No. CR7 Mnemonic WEN CR6 R/W CR5 to CR3 CR2 RS2 to RS0 CR1 to CR0 0 CREAD Description Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. Register Address Bits. These address bits are used to select which registers of the ADC are being selected during this serial interface communication. See Table 15. Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be read continuously, that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communications register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so it can receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is written to the device. These bits must be programmed to Logic 0 for correct operation. Table 15. Register Selection RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications Register During a Write Operation Status Register During a Read Operation Mode Register Configuration Register Data Register ID Register IO Register Offset Register Full-Scale Register Rev. D | Page 17 of 36 Register Size 8-bit 8-bit 16-bit 16-bit 24-bit (AD7794)/16-Bit (AD7795) 8-bit 8-bit 24-bit (AD7794)/16-Bit (AD7795) 24-bit (AD7794)/16-Bit (AD7795) AD7794/AD7795 STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7795)/0x88 (AD7794) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. SR7 RDY(1) SR6 ERR(0) SR5 NOXREF(0) SR4 0(0) Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in brackets indicates the poweron/reset default status of that bit. SR3 0/1 SR2 CH2(0) SR1 CH1(0) SR0 CH0(0) Table 16. Status Register Bit Designations Bit No. SR7 Mnemonic RDY SR6 ERR SR5 NOXREF SR4 SR3 SR2 to SR0 0 0/1 CH2 to CH0 Description Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register has been read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, underrange, or the absence of a reference voltage. Cleared by a write operation to start a conversion. No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. Cleared to indicate that a valid reference is applied to the selected reference pins. The NOXREF bit is enabled by setting the REF_DET bit in the configuration register to 1. The ERR bit is also set if the voltage applied to the selected reference input is invalid. This bit is automatically cleared. This bit is automatically cleared on the AD7795 and is automatically set on the AD7794. These bits indicate which channel is being converted by the ADC. Rev. D | Page 18 of 36 AD7794/AD7795 MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A The mode register is a 16-bit read/write register that is used to select the operating mode, the update rate, and the clock source. denoting that the bits are in the mode register. MR15 is the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit. Table 17 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations with MR MR15 MD2(0) MR7 CLK1(0) MR14 MD1(0) MR6 CLK0(0) MR13 MD0(0) MR5 0(0) MR12 PSW(0) MR4 CHOP-DIS(0) MR11 0(0) MR3 FS3(1) MR10 0(0) MR2 FS2(0) MR9 AMP-CM(0) MR1 FS1(1) MR8 0(0) MR0 FS0(0) Table 17. Mode Register Bit Designations Bit No. MR15 to MR13 MR12 Mnemonic MD2 to MD0 PSW MR11 to MR10 MR9 0 AMP-CM MR8 MR7 to MR6 0 CLK1 to CLK0 MR5 MR4 0 CHOP-DIS MR3 to MR0 FS3 to FS0 Description Mode Select Bits. These bits select the operating mode of the AD7794/AD7795 (see Table 18). Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down mode, the power switch is opened. These bits must be programmed with a Logic 0 for correct operation. Instrumentation Amplifier Common-Mode Bit. This bit is used in conjunction with the CHOP-DIS bit. With chop disabled, the user can operate with a wider range of common-mode voltages when AMP-CM is cleared. However, the dc common-mode rejection degrades. With AMP-CM set, the span for the commonmode voltage is reduced (see the Specifications section). However, the dc common-mode rejection is significantly better. This bit must be programmed with a Logic 0 for correct operation. These bits are used to select the clock source for the AD7794/AD7795. Either the on-chip 64 kHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7794/AD7795 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7794/AD7795. CLK1 CLK0 ADC Clock Source 0 0 Internal 64 kHz clock. Internal clock is not available at the CLK pin. 0 1 Internal 64 kHz clock. This clock is made available at the CLK pin. 1 0 External 64 kHz. The external clock can have a 45:55 duty cycle (see the Specifications section for the external clock). 1 1 External clock. The external clock is divided by 2 within the AD7794/AD7795. This bit must be programmed with a Logic 0 for correct operation. This bit is used to enable or disable chop. On power-up or following a reset, CHOP-DIS is cleared so chop is enabled. When CHOP-DIS is set, chop is disabled. This bit is used in conjunction with the AMP-CM bit. When chop is disabled, the AMP-CM bit should be set. This limits the common-mode voltage that can be used by the ADC, but the dc common-mode rejection does not degrade. Filter Update Rate Select Bits (see Table 19). Rev. D | Page 19 of 36 AD7794/AD7795 Table 18. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous Conversion Mode (Default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on, the first conversion is available after a period of 2/fADC when chop is enabled or 1/fADC when chop is disabled. Subsequent conversions are available at a frequency of fADC with chop either enabled or disabled. Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/fADC when chop is enabled, or 1/fADC when chop is disabled. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. Power-Down Mode. In power-down mode, all the AD7794/AD7795 circuitry is powered down including the current sources, power switch, burnout currents, bias voltage generator, and clock circuitry. Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration. When the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. For higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled and 2 conversion cycles when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. System Zero-Scale Calibration. User should connect the system zero-scale input to the channel input pins as selected by the CH2 bit, CH1 bit, and CH0 bit. A system offset calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. System Full-Scale Calibration. User should connect the system full-scale input to the channel input pins as selected by the CH2 bit, CH1 bit, and CH0 bit. A calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. Rev. D | Page 20 of 36 AD7794/AD7795 Table 19. Update Rates Available (Chop Enabled) 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fADC (Hz) x 470 242 123 62 50 39 33.2 19.6 16.7 16.7 12.5 10 8.33 6.25 4.17 TSETTLE (ms) x 4 8 16 32 40 48 60 101 120 120 160 200 240 320 480 Rejection @ 50 Hz/60 Hz (Internal Clock) 90 dB (60 Hz only) 80 dB (50 Hz only) 65 dB (50 Hz and 60 Hz) 66 dB (50 Hz and 60 Hz) 69 dB (50 Hz and 60 Hz) 70 dB (50 Hz and 60 Hz) 72 dB (50 Hz and 60 Hz) 74 dB (50 Hz and 60 Hz) With chop disabled, the update rates remain unchanged, but the settling time for each update rate is reduced by a factor of 2. The rejection at 50 Hz/60 Hz for a 16.6 Hz update rate degrades to 60 dB. Rev. D | Page 21 of 36 AD7794/AD7795 CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 The configuration register is a 16-bit read/write register that is used to configure the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel. Table 20 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations. CON denotes that the bits are in the configuration register. CON15 is the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CON15 VBIAS1(0) CON14 VBIAS0(0) CON13 BO(0) CON12 U/B(0) CON11 BOOST(0) CON10 G2(1) CON9 G1(1) CON8 G0(1) CON7 REFSEL1(0) CON6 REFSEL0(0) CON5 REF_DET(0) CON4 BUF(1) CON3 CH3(0) CON2 CH2(0) CON1 CH1(0) CON0 CH0(0) Table 20. Configuration Register Bit Designations Bit No. CON15 to CON14 Mnemonic VBIAS1 to VBIAS0 CON13 BO CON12 U/B CON11 BOOST CON10 to CON8 G2 to G0 CON7 to CON6 REFSEL1/REFSEL0 Description Bias Voltage Generator Enable. The negative terminal of the analog inputs can be biased up to AVDD/2. These bits are used in conjunction with the BOOST bit. VBIAS1 VBIAS0 Bias Voltage 0 0 Bias voltage generator disabled 0 1 Bias voltage generator connected to AIN1(−) 1 0 Bias voltage generator connected to AIN2(−) 1 1 Bias voltage generator connected to AIN3(−) Burnout Current Enable Bit. This bit must be programmed with a Logic 0 for correct operation. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer or in-amp is active. Unipolar/Bipolar Bit. Set by user to enable unipolar coding, that is, zero differential input results in 0x000000 output and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable bipolar coding. Negative full-scale differential input results in an output code of 0x000000, zero differential input results in an output code of 0x800000, and positive full-scale differential input results in an output code of 0xFFFFFF. This bit is used in conjunction with the VBIAS1 and VBIAS0 bits. When set, the current consumed by the bias voltage generator is increased, which reduces its power-up time. Gain Select Bits. Written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (2.5 V Reference) 0 0 0 2.5 V 1 (in-amp not used) 0 0 1 1.25 V 2 (in-amp not used) 0 1 0 4 625 mV 0 1 1 8 312.5 mV 1 0 0 16 156.2 mV 1 0 1 32 78.125 mV 1 1 0 64 39.06 mV 1 1 1 128 19.53 mV Reference Select Bits. The reference source for the ADC is selected using these bits. REFSEL1 REFSEL0 Reference Source 0 0 External reference applied between REFIN1(+) and REFIN1(−) 0 1 External reference applied between REFIN2(+) and REFIN2(−) 1 0 Internal 1.17 V reference 1 1 Reserved Rev. D | Page 22 of 36 AD7794/AD7795 Bit No. CON5 Mnemonic REF_DET CON4 BUF CON3 to CON0 CH3 to CH0 Description Enables the reference detect function. When set, the NOXREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.5 V. When cleared, the reference detect function is disabled. Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered mode, allowing the user to place source impedances on the front end without contributing gain errors to the system. For gains of 1 and 2, the buffer can be enabled or disabled. For higher gains, the buffer is automatically enabled. With the buffer disabled, the voltage on the analog input pins can be from 30 mV below GND to 30 mV above AVDD. When the buffer is enabled, it requires some headroom so the voltage on any input pin must be limited to 100 mV within the power supply rails. Channel Select Bits. Written by the user to select the active analog input channel to the ADC. CH3 CH2 CH1 CH0 Channel Calibration Pair 0 0 0 0 AIN1(+)/AIN1(−) 0 0 0 0 1 AIN2(+)/AIN2(−) 1 0 0 1 0 AIN3(+)/AIN3(−) 2 0 0 1 1 AIN4(+)/AIN4(−) 3 0 1 0 0 AIN5(+)/AIN5(−) 3 0 1 0 1 AIN6(+)/AIN6(−) 3 0 1 1 0 Temp Sensor Automatically selects the internal 1.17 V reference and sets the gain to 1 0 1 1 1 AVDD Monitor Automatically selects the internal 1.17 V reference and sets the gain to 1/6 1 0 0 0 AIN1(−)/AIN1(−) 0 1 0 0 1 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Rev. D | Page 23 of 36 AD7794/AD7795 DATA REGISTER IO REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(AD7795), 0x000000 (AD7794) RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 The IO register is an 8-bit read/write register that is used to enable the excitation currents and select the value of the excitation currents. The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xXF The identification number for the AD7794/AD7795 is stored in the ID register. This is a read-only register. IO7 0(0) IO6 IOEN(0) IO5 IO2DAT(0) IO4 IO1DAT(0) Table 21 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations. IO denotes that the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. IO3 IEXCDIR1(0) IO2 IEXCDIR0(0) IO1 IEXCEN1(0) IO0 IEXCEN0(0) Table 21. IO Register Bit Designations Bit No. IO7 IO6 Mnemonic 0 IOEN IO5 to IO4 IO2DAT/IO1DAT IO3 to IO2 IEXCDIR1 to IEXCDIR0 IO3 to IO2 IEXCEN1 to IEXCEN0 Description This bit must be programmed with a Logic 0 for correct operation. Configures Pin AIN6(+)/P1 and Pin AIN6(−)/P2 as analog input pins or digital output pins. When this bit is set, the pins are configured as Digital Output Pin P1 and Digital Output Pin P2. When this bit is cleared, these pins are configured as Analog Input Pin AIN6(+) and Analog Input Pin AIN6(−). P2/P1 Data. When IOEN is set, the data for Digital Output Pin P1 and Digital Output Pin P2 is written to Bit IO2DAT and Bit IO1DAT. Direction of Current Sources Select Bits. IEXCDIR1 IEXCDIR0 Current Source Direction 0 0 Current Source IEXC1 connected to Pin IOUT1. Current Source IEXC2 connected to Pin IOUT2. 0 1 Current Source IEXC1 connected to Pin IOUT2. Current Source IEXC2 connected to Pin IOUT1. 1 0 Both current sources connected to Pin IOUT1. Permitted only when the current sources are set to 10 μA or 210 μA. 1 1 Both current sources connected to Pin IOUT2. Permitted only when the current sources are set to 10 μA or 210 μA. These bits are used to enable and disable the current sources. They also select the value of the excitation currents. IEXCEN1 IEXCEN0 Current Source Value 0 0 Excitation currents disabled 0 1 10 μA 1 0 210 μA 1 1 1 mA Rev. D | Page 24 of 36 AD7794/AD7795 OFFSET REGISTER FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7795), 0x800000 (AD7794)) RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7795), 0x5XXX00 (AD7794) The offset register is a 16-bit register on the AD7795 and a 24-bit register on the AD7794. The offset register holds the offset calibration coefficient for the ADC and its power-on reset value is 0x8000/0x800000, for the AD7794/AD7795, respectively. The AD7794/AD7795 each have four offset registers. Channel AIN1 to Channel AIN3 have dedicated offset registers while the AIN4, AIN5, and AIN6 channels share an offset register. Each of these registers is a read/write register. The register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7794/AD7795 must be placed in power-down mode or idle mode when writing to the offset register. The full-scale register is a 16-bit register on the AD7795 and a 24-bit register on the AD7794. The full-scale register holds the full-scale calibration coefficient for the ADC. The AD7794/ AD7795 each have four full-scale registers. The AIN1, AIN2, and AIN3 channels have dedicated full-scale registers, while the AIN4, AIN5, and AIN6 channels share a register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured on power-on with factory calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The coefficients are different, depending on whether the internal reference or an external reference is selected. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or the full-scale register is written to. Rev. D | Page 25 of 36 AD7794/AD7795 ADC CIRCUIT INFORMATION 50 Hz and 60 Hz rejection is optimized when the update rate equals 16.7 Hz or less, as notches are placed at both 50 Hz and 60 Hz with these update rates (see Figure 14). OVERVIEW The AD7794/AD7795 are low power ADCs that incorporate a ∑-Δ modulator, buffer, reference, in-amp, and on-chip digital filtering, which are intended for the measurement of wide dynamic range, low frequency signals (such as those in pressure transducers), weigh scales, and temperature measurement applications. The AD7794/AD7795 use slightly different filter types, depending on the output update rate, so that the rejection of quantization noise and device noise is optimized. When the update rate is 4.17 Hz to 12.5 Hz, a Sinc3 filter along with an averaging filter is used. When the update rate is 16.7 Hz to 39 Hz, a modified Sinc3 filter is used. This filter gives simultaneous 50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A Sinc4 filter is used when the update rate is 50 Hz to 242 Hz. Finally, an integrate-only filter is used when the update rate equals 470 Hz. Figure 13 to Figure 16 show the frequency response of the different filter types for some of the update rates when chop is enabled. In this mode, the settling time equals twice the update rate. Figure 17 to Figure 20 show the filter response with chop disabled. Each part has six differential inputs that can be buffered or unbuffered. The devices operate with an internal 1.17 V reference or by using an external reference. Figure 12 shows the basic connections required to operate the parts. The output rate of the AD7794/AD7795 (fADC) is user programmable. The allowable update rates, along with the corresponding settling times, are listed in Table 19 for chop enabled. With chop disabled, the allowable update rates remain unchanged, but the settling time equals 1/fADC. Normal mode rejection is the major function of the digital filter. Simultaneous VDD REFIN1(+) GND IN+ OUT– AD7794/AD7795 AIN1(+) AIN1(–) IN+ OUT– OUT+ AVDD VDD IN– OUT+ AIN2(+) AIN2(–) IN– AIN3(+) MUX BUF IN-AMP Σ-Δ ADC SERIAL INTERFACE AND LOGIC CONTROL DOUT/RDY DIN SCLK CS AIN3(–) GND REFIN2(+) VDD REFIN2(–) IOUT1 INTERNAL CLOCK DVDD REFIN1(–) PSW 04854-012 RCM GND CLK Figure 12. Basic Connection Diagram Rev. D | Page 26 of 36 AD7794/AD7795 0 0 –10 –20 –20 (dB) (dB) –40 –30 –60 –40 –80 0 20 40 60 80 –60 120 100 04854-020 04854-017 –100 –50 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Filter Response with Update Rate = 4.17 Hz (Chop Enabled) Figure 16. Filter Response with Update Rate = 470 Hz (Chop Enabled) –20 –20 –40 –40 –60 –80 –80 –100 04854-018 –60 0 20 40 60 80 100 120 140 160 180 –100 200 04854-021 (dB) 0 (dB) 0 0 20 40 FREQUENCY (Hz) 60 80 100 120 FREQUENCY (Hz) Figure 14. Filter Response with Update Rate = 16.7 Hz (Chop Enabled) Figure 17. Filter Response with Update Rate = 4.17 Hz (Chop Disabled) –20 –20 –40 –40 –60 –80 –80 –100 04854-019 –60 0 500 1000 1500 2000 2500 –100 3000 FREQUENCY (Hz) 04854-022 (dB) 0 (dB) 0 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz) Figure 15. Filter Response with Update Rate = 242 Hz (Chop Enabled) Figure 18. Filter Response with Update Rate = 16.7 Hz (Chop Disabled) Rev. D | Page 27 of 36 AD7794/AD7795 to transfer data into the on-chip registers, while DOUT/RDY is used for accessing data from the on-chip registers. SCLK is the serial clock input for the devices, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. The DOUT/RDY pin also operates as a data ready signal; the line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7794/AD7795 in systems where several components are connected to the serial bus. 0 –20 (dB) –40 –60 –100 04854-023 –80 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7794/AD7795 with CS, which is being used to decode the parts. Figure 3 shows the timing for a read operation from the output shift register of the AD7794/AD7795, while Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times, even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that the read operations have been completed before the next output update occurs. In continuous read mode, the data register can be read only once. Figure 19. Filter Response at 242 Hz Update Rate (Chop Disabled) 0 –10 (dB) –20 –30 –40 The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7794/AD7795. The end of the conversion can be monitored using the RDY bit in the status register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. –60 04854-024 –50 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 FREQUENCY (Hz) Figure 20. Filter Response at 470 Hz Update Rate (Chop Disabled) DIGITAL INTERFACE As previously outlined in the On-Chip Registers section, the programmable functions of the AD7794/AD7795 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface. Read access to the on-chip registers is also provided by this interface. All communications with the parts must start with a write to the communications register. After power-on or reset, each device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation, and determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the parts begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. The serial interface of the AD7794/AD7795 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used The AD7794/AD7795 can be operated with CS being used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS, because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s on the DIN input. If a Logic 1 is written to the AD7794/AD7795 line for at least 32 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it is expecting a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface. The AD7794/AD7795 can be configured to continuously convert or perform a single conversion (see Figure 21 through Figure 23). Rev. D | Page 28 of 36 AD7794/AD7795 CS DIN 0x08 0x200A 0x58 DATA 04854-014 DOUT/RDY SCLK Figure 21. Single Conversion CS 0x58 0x58 DIN DATA DATA 04854-015 DOUT/RDY SCLK Figure 22. Continuous Conversion CS 0x5C DIN DATA DATA DATA 04854-016 DOUT/RDY SCLK Figure 23. Continuous Read Rev. D | Page 29 of 36 AD7794/AD7795 Single Conversion Mode Continuous Read In single conversion mode, the AD7794/AD7795 are placed in shutdown mode between conversions. When a single conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 to 1 in the mode register, the AD7794/AD7795 power up, perform a single conversion, and then return to shutdown mode. The on-chip oscillator requires 1 ms to power up. A conversion requires a time period of 2 × tADC. DOUT/RDY goes low to indicate the completion of a conversion. When the dataword has been read from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY remains high until another conversion is initiated and completed. The data register can be read several times, if required, even when DOUT/RDY has gone high. Rather than write to the communications register each time a conversion is complete to access the data, the AD7794/AD7795 can be configured so that the conversions are placed on the DOUT/RDY line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC. The 24-bit word is automatically placed on the DOUT/RDY line when a conversion is complete. The ADC should be configured for continuous conversion mode. Continuous Conversion Mode This is the default power-up mode. The AD7794/AD7795 continuously convert with the RDY pin in the status register going low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. The digital conversion is placed on the DOUT/RDY pin as soon as SCLK pulses are applied to the ADC. DOUT/RDY returns high when the conversion is read. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion, or else the new conversion word is lost. When DOUT/RDY goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC, and the data conversion is placed on the DOUT/RDY line. When the conversion is read, DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7794/AD7795 to read the word, the serial output register is reset when the next conversion is complete. The new conversion is then placed in the output serial register. To exit the continuous read mode, the instruction 01011000 must be written to the communications register while the RDY pin is low. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. Rev. D | Page 30 of 36 AD7794/AD7795 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL INSTRUMENTATION AMPLIFIER The AD7794/AD7795 have six differential analog input channels. These are connected to the on-chip buffer amplifier when the devices are operated in buffered mode. When in unbuffered mode, the channels connect directly to the modulator. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gages or resistance temperature detectors (RTDs). Amplifying the analog input signal by a gain of 1 or 2 is performed digitally within the AD7794/AD7795. However, when the gain equals 4 or higher, the output from the buffer is applied to the input of the on-chip instrumentation amplifier. This low noise in-amp means that signals of small amplitude can be gained within the AD7794/AD7795 while still maintaining excellent noise performance. For example, when the gain is set to 64, the rms noise is 40 nV typically, which is equivalent to 21 bits effective resolution or 18.5 bits peak-topeak resolution. When BUF = 0, the parts operate in unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. Table 22 shows the allowable external resistance/capacitance values for unbuffered mode so that no gain error at the 20-bit level is introduced. Each AD7794/AD7795 can be programmed to have a gain of 1, 2, 4, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 20 mV to 0 V to 2.5 V and the bipolar ranges are from ±20 mV to ±2.5 V. When the in-amp is active (gain ≥ 4), the common-mode voltage ((AIN(+) + AIN(−))/2) must be greater than or equal to 0.5 V when chop is enabled. With chop disabled, and with the AMP-CM bit set to 1 to prevent degradation in the commonmode rejection, the allowable common-mode voltage is limited to between Table 22. External R-C Combination for 20-Bit No Gain Error Capacitance (pF) 50 100 500 1000 5000 Resistance (Ω) 9k 6k 1.5 k 900 200 0.2 + (Gain/2 × (AIN(+) − AIN(−))) and AVDD − 0.2 − (Gain/2 × (AIN(+) − AIN(−))) The AD7794/AD7795 can be operated in unbuffered mode only when the gain equals 1 or 2. At higher gains, the buffer is automatically enabled. The absolute input voltage range in buffered mode is restricted to a range between GND + 100 mV and AVDD − 100 mV. When the gain is set to 4 or higher, the in-amp is enabled. The absolute input voltage range when the inamp is active is restricted to a range between GND + 300 mV and AVDD − 1.1 V. Care must be taken in setting up the commonmode voltage so that these limits are not exceeded. Otherwise, there is degradation in linearity and noise performance. The absolute input voltage in unbuffered mode includes the range between GND − 30 mV and AVDD + 30 mV as a result of being unbuffered. The negative absolute input voltage limit does allow the possibility of monitoring small, true bipolar signals with respect to GND. If the AD7794/AD7795 are operated with an external reference that has a value equal to AVDD, for correct operation, the analog input signal must be limited to 90% of VREF/gain when the inamp is active. BIPOLAR/UNIPOLAR CONFIGURATION The analog input to the AD7794/AD7795 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the parts can tolerate negative voltages with respect to system GND. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the AIN(−) input. For example, if AIN(−) is 2.5 V and the ADC is configured for unipolar mode with a gain of 1, the input voltage range on the AIN(+) pin is 2.5 V to 5 V. If the ADC is configured for bipolar mode, the analog input range on the AIN(+) input is 0 V to 5 V. The bipolar/unipolar option is chosen by programming the U/B bit in the configuration register. Rev. D | Page 31 of 36 AD7794/AD7795 DATA OUTPUT CODING EXCITATION CURRENTS When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a miscalled voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as The AD7794/AD7795 also contain two matched, software configurable, constant current sources that can be programmed to equal 10 μA, 210 μA, or 1 mA. Both source currents from AVDD are directed to either the IOUT1 or IOUT2 pin of the device. These current sources are controlled via bits in the IO register. The configuration bits enable the current sources and direct the current sources to IOUT1 or IOUT2, along with selecting the value of the current. These current sources can be used to excite external resistive bridge or RTD sensors. Code = (2N × AIN × GAIN)/VREF When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N – 1 × [(AIN × GAIN/VREF) + 1] where: AIN is the analog input voltage. GAIN is the in-amp setting (1 to 128). N = 24. BURNOUT CURRENTS The AD7794/AD7795 contain two 100 nA constant current generators, one sourcing current from AVDD to AIN(+), and one sinking current from AIN(−) to GND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (BO) bit in the configuration register. These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. Once the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resulting voltage measured is full scale, the user needs to verify why this is the case. A full-scale reading could mean that the front-end sensor is open circuit. It could also mean that the front-end sensor is overloaded and is justified in outputting full scale, or that the reference may be absent and the NOXREF bit is set, thus clamping the data to all 1s. When reading all 1s from the output, the user needs to check these three cases before making a judgment. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit in the configuration register. The current sources work over the normal absolute input voltage range specifications with buffers on. BIAS VOLTAGE GENERATOR A bias voltage generator is included on the AD7794/AD7795. It biases the negative terminal of the selected input channel to AVDD/2. This function is available on inputs AIN1(−) to AIN3(−). It is useful in thermocouple applications, as the voltage generated by the thermocouple must be biased about some dc voltage if the gain is greater than 2. This is necessary because the instrumentation amplifier requires headroom. If there is no headroom, signals close to GND or AVDD do not convert accurately. The bias voltage generator is controlled using the VBIAS1 and VBIAS0 bits in conjunction with the BOOST bit in the configuration register. The power-up time of the bias voltage generator is dependent on the load capacitance. To accommodate higher load capacitances, each AD7794/AD7795 has a BOOST bit. When this bit is set to 1, the current consumed by the bias voltage generator is increased so that power-up time is reduced considerably. Figure 11 shows the power-up times when BOOST equals 0 and BOOST equals 1 for different load capacitances. The current consumption of the AD7794/AD7795 increases by 40 μA when the bias voltage generator is enabled, and BOOST equals 0. With the BOOST function enabled, the current consumption increases by 250 μA. REFERENCE The AD7794/AD7795 have embedded 1.17 V references. These references can be used to supply the ADC or external references can be applied. The embedded references are low noise, low drift references with 4 ppm/°C drift typically. For external references, the ADC has a fully differential input capability for the channel. In addition, the user has the option of selecting one of two external reference options (REFIN1 or REFIN2). The reference source for the AD7794/AD7795 is selected using the REFSEL1 and REFSEL0 bits in the configuration register. When the internal reference is selected, it is internally connected to the modulator (it is not available on the REFIN pins). The common-mode range for these differential inputs is from GND to AVDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is 2.5 V nominal, but the AD7794/AD7795 are functional with reference voltages from 0.1 V to AVDD. In applications where the excitation (voltage or current) for the transducer on the analog Rev. D | Page 32 of 36 AD7794/AD7795 input also drives the reference voltage for the parts, the effect of the low frequency noise in the excitation source is removed, because the application is ratiometric. If the AD7794/AD7795 are used in nonratiometric applications, a low noise reference should be used. Recommended 2.5 V reference voltage sources for the AD7794/AD7795 include the ADR381 and ADR391, which are low noise, low power references. Also, note that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source driving the reference inputs. Reference voltage sources (for example, the ADR391) typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFIN pins is not recommended in this type of circuit configuration. REFERENCE DETECT The AD7794/AD7795 include on-chip circuitry to detect if they have a valid reference for conversions or calibrations when the user selects an external reference as the reference source. This feature is enabled when the REF_DET bit in the configuration register is set to 1. If the voltage between the selected REFIN(+) and REFIN(–) pins goes below 0.3 V, or either the REFIN(+) or REFIN(–) inputs are open circuit, the AD7794/AD7795 detect that they no longer have valid references. In this case, the NOXREF bit of the status register is set to 1. If the AD7794/ AD7795 are performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s. Therefore, it is not necessary to continuously monitor the status of the NOXREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7794/AD7795 are performing either offset or full-scale calibrations and the NOXREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle. RESET The circuitry and serial interface of the AD7794/AD7795 can be reset by writing 32 consecutive 1s to the device. This resets the logic, the digital filter, and the analog modulator, and all onchip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the on-chip registers. A reset is useful if the serial interface becomes asynchronous due to noise on the SCLK line. AVDD MONITOR Along with converting external voltages, the ADC can be used to monitor the voltage on the AVDD pin. When Bit CH2 to Bit CH0 equals 1, the voltage on the AVDD pin is internally attenuated by 6, and the resulting voltage is applied to the ∑-Δ modulator using an internal 1.17 V reference for analogto-digital conversion. This is useful because variations in the power supply voltage can be monitored. CALIBRATION The AD7794/AD7795 provide four calibration modes that can be programmed via the mode bits in the mode register. These are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration, which effectively reduce the offset error and full-scale error to the order of the noise. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. To start a calibration, write the relevant value to the MD2 to MD0 bits in the mode register. After the calibration is completed, the contents of the corresponding calibration registers are updated, the RDY bit in the status register is set, the DOUT/RDY pin goes low (if CS is low), and the AD7794/AD7795 revert to idle mode. During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, external ADC errors are removed. From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration, if required, should always be performed before a full-scale calibration. System software should monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of calibration via a polling sequence or an interrupt-driven routine. With chop enabled, both an internal offset calibration and a system offset calibration take two conversion cycles. With chop enabled, an internal offset calibration is not needed because the ADC itself removes the offset continuously. With chop disabled, an internal offset calibration or system offset calibration takes one conversion cycle to complete. Internal offset calibrations are required with chop disabled and should occur before the full-scale calibration. To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. When the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and Rev. D | Page 33 of 36 AD7794/AD7795 one conversion cycle when chop is disabled. For higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled, and two conversion cycles when chop is disabled. DOUT/RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the fullscale register of the selected channel. Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a system full-scale calibration can be performed. A full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. An internal full-scale calibration can be performed at specified update rates only. For gains of 1, 2, and 4, an internal full-scale calibration can be performed at any update rate. However, for higher gains, internal full-scale calibrations can be performed only when the update rate is less than or equal to 16.7 Hz, 33.3 Hz, and 50 Hz. However, the full-scale error does not vary with update rate, so a calibration at one update is valid for all update rates (assuming the gain or reference source is not changed). A system full-scale calibration takes two conversion cycles to complete, irrespective of the gain setting when chop is enabled and one conversion cycle when chop is disabled. A system fullscale calibration can be performed at all gains and all update rates. With chop disabled, the offset calibration (internal or system offset) should be performed before the system full-scale calibration is initiated. GROUNDING AND LAYOUT Because the analog inputs and reference inputs of the ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part removes common-mode noise on these inputs. The digital filter provides rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7794/AD7795 are more immune to noise interference than conventional high resolution converters. However, because the resolution of the AD7794/AD7795 is so high, and the noise levels from the AD7794/AD7795 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7794/AD7795 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it gives the best shielding. It is recommended that the GND pin of the AD7794/AD7795 be tied to the AGND plane of the system. In any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. The ground plane of the AD7794/AD7795 should be allowed to run under the AD7794/AD7795 to prevent noise coupling. The power supply lines to the AD7794/AD7795 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. In addition, clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. AVDD should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to GND. DVDD should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to the system’s DGND plane, with the system’s AGND to DGND connection being close to the AD7794/AD7795. To achieve the best from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 μF ceramic capacitors to DGND. Rev. D | Page 34 of 36 AD7794/AD7795 APPLICATIONS INFORMATION The AD7794/AD7795 offer low cost, high resolution analog-todigital functions. Because the analog-to-digital function is provided by a ∑-Δ architecture, it makes the parts more immune to noisy environments, making them ideal for use in sensor measurement, and industrial and process control applications. A second advantage of using the AD7794/AD7795 in transducerbased applications is that the low-side power switch can be fully utilized in low power applications. The low-side power switch is connected in series with the cold side of the bridges. In normal operation, the switch is closed and measurements can be taken. In applications where power is of concern, the AD7794/AD7795 can be placed in standby mode, thus significantly reducing the power consumed in the application. In addition, the low-side power switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducers. When the parts are taken out of standby mode, and the low-side power switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the AD7794/AD7795. FLOWMETER Figure 24 shows the AD7794/AD7795 being used in a flowmeter application that consists of two pressure transducers, with the rate of flow being equal to the pressure difference. The pressure transducers shown are the BP01 from Sensym. The pressure transducers are arranged in a bridge network and give a differential output voltage between its OUT+ and OUT– terminals. With rated full-scale pressure (in this case 300 mmHg) on the transducer, the differential output voltage is 3 mV/V of the input voltage (that is, the voltage between the IN(+) and IN(–) terminals). In the diagram, temperature compensation is performed using a thermistor. The on-chip excitation current supplies the thermistor. In addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. This allows a ratiometric measurement so that variation of the excitation current has no effect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance that is measured). Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 15 mV. The excitation voltage for the bridge can be used to directly provide the reference for the ADC, as the reference input range includes the supply voltage. VDD REFIN1(+) GND IN+ OUT– AD7794/AD7795 AIN1(+) AIN1(–) IN+ OUT– OUT+ AVDD VDD IN– OUT+ AIN2(+) AIN2(–) IN– AIN3(+) MUX BUF IN-AMP Σ-Δ ADC SERIAL INTERFACE AND LOGIC CONTROL DOUT/RDY DIN SCLK CS AIN3(–) GND REFIN2(+) VDD REFIN2(–) IOUT1 INTERNAL CLOCK DVDD REFIN1(–) PSW 04854-025 RCM GND CLK Figure 24. Typical Application (Flowmeter) Rev. D | Page 35 of 36 AD7794/AD7795 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 25. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model AD7794BRU AD7794BRU-REEL AD7794BRUZ 1 AD7794BRUZ-REEL1 AD7794CRUZ1 AD7794CRUZ-REEL1 AD7795BRUZ1 AD7795BRUZ-REEL1 EVAL-AD7794EB EVAL-AD7795EB 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +125°C –40°C to +125°C –40°C to +105°C –40°C to +105°C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Evaluation Board Z = RoHS Compliant Part. ©2004-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04854-0-3/07(D) Rev. D | Page 36 of 36 Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24