FAIRCHILD FDS9435A

May 1999
FDS9435A
Single P-Channel Enhancement Mode Field Effect Transistor
GeneralDescription
Features
SO-8 P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
SuperSOTTM-6
SOT-23
D
D
D
D
SO-8
S
F D 5A
3
94
pin 1
Absolute Maximum Ratings
Symbol
Parameter
VDSS
Drain-Source Voltage
SuperSOTTM-8
VGSS
Gate-Source Voltage
ID
Drain Current - Continuous
PD
Maximum Power Dissipation
S
S
S
G
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely
used surface mount package.
SO-8
SOT-223
SOIC-16
5
4
6
3
7
2
8
1
TA = 25oC unless otherwise noted
(Note 1a)
- Pulsed
FDS9435A
Units
-30
V
-20
V
- 5.3
A
-50
(Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG
-5.3 A, -30 V, RDS(ON) = 0.045 Ω @ VGS = -10 V,
RDS(ON) = 0.075 Ω @ VGS = - 4.5 V.
Operating and Storage Temperature Range
2.5
W
1.2
1
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
50
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
25
°C/W
© 1999 Fairchild Semiconductor Corporation
FDS9435A Rev.C
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, I D = -250 µA
-30
V
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = -250 µA, Referenced to 25 C
IDSS
Zero Gate Voltage Drain Current
VDS = -24 V, VGS = 0 V
-1
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
-100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100
nA
-3
V
ON CHARACTERISTICS
VGS(th)
o
mV/ oC
-25
(Note 2)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-1
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp. Coefficient
ID = -250 µA, Referenced to 25 C
RDS(ON)
Static Drain-Source On-Resistance
VGS = -10 V, I D = -5.3 A
o
-1.5
mV/oC
-3.2
TJ =125°C
VGS = -4.5 V, I D = -4.0 A
0.035
0.045
0.052
0.072
0.059
0.075
-25
Ω
ID(ON)
On-State Drain Current
VGS = -10 V, VDS = -5 V
gFS
Forward Transconductance
VDS = -10 V, I D = -4 A
9.5
A
S
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
730
pF
400
pF
90
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 2)
tD(on)
Turn - On Delay Time
VDS = -10 V, I D = -1 A
11
20
tr
Turn - On Rise Time
VGS = -10 V , RGEN = 6 Ω
10
18
ns
tD(off)
Turn - Off Delay Time
90
125
tf
Turn - Off Fall Time
55
80
Qg
Total Gate Charge
VDS = -10 V, I D = -4 A,
19
27
nC
Qgs
Gate-Source Charge
VGS = -10 V
3.5
Qgd
Gate-Drain Charge
-2.1
A
-1.2
V
3.6
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, I S = -2.1 A
(Note 2)
-0.77
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is
guaranteed by design while RθCA is determined by the user's board design.
a. 50OC/W on a 1 in2 pad
of 2oz copper.
b. 105OC/W on a 0.04 in2
pad of 2oz copper.
c. 125OC/W on a 0.006 in2 pad
of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDS9435A Rev.C
Typical Electrical Characteristics
3
40
R DS(on) , NORMALIZED
VGS = -10V
-7.0V
-6.0V
-5.0V
30
-4.5V
20
-4.0V
-3.5V
10
DRAIN-SOURCE ON-RESISTANCE
- ID , DRAIN-SOURCE CURRENT (A)
50
VGS = -3.5 V
2.5
-4.5V
2
4
6
8
-6.0V
-8.0V
-10V
1
0.5
2
-5.0V
1.5
0
0
-4.0V
10
0
10
20
0.2
R DS(ON) , ON-RESISTANCE (OHM)
ID = -5.3A
DRAIN-SOURCE ON-RESISTANCE
R DS(ON) , NORMALIZED
1.6
V GS = -10V
1.2
1
0.8
0.6
-50
0
25
50
75
100
125
I D = -2.7A
0.15
0.125
0.1
TJ = 125°C
0.075
0.05
TJ = 25°C
0.025
0
-25
Figure 3. On-Resistance Variation
Temperature.
50
0.175
150
2
4
6
8
10
-VGS , GATE TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (°C)
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
with
60
V DS = -5V
-I S , REVERSE DRAIN CURRENT (A)
50
- ID , DRAIN CURRENT (A)
40
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 1. On-Region Characteristics.
1.4
30
- I D , DRAIN CURRENT (A)
-VDS , DRAIN-SOURCE VOLTAGE (V)
TJ = -55°C
25°C
125°C
40
30
20
10
0
0
2
4
6
8
-VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
10
VGS = 0V
10
TJ = 125°C
1
25°C
0.1
-55°C
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-VSD , BODY DIODE FORWARD VOLTAGE (V)
Figure 6 . Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDS9435A Rev.C
Typical Electrical Characteristics (continued)
2000
I D = -5.3A
VDS = -5V
-10V
-15V
8
1000
CAPACITANCE (pF)
-V GS , GATE-SOURCE VOLTAGE (V)
10
6
4
2
Ciss
500
Coss
200
Crss
f = 1 MHz
VGS = 0 V
100
0
0
5
10
15
20
50
0.1
Q g , GATE CHARGE (nC)
0.3
1
3
10
30
-VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
50
RD
S(O
L
N)
IMI
100
us
1m
s
10m
s
10
0m
s
1s
10s
DC
T
1
VGS = -10V
SINGLE PULSE
R θJA = 125°C/W
TA A = 25°C
0.1
0.01
0.1
0.2
SINGLE PULSE
R θJA= 125°C/W
TA = 25°C
40
POWER (W)
10
30
20
10
0
0.0001
0.5
1
2
5
10
20
0.001
0.01
50
0.1
1
10
100 300
SINGLE PULSE TIME (SEC)
-VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
-ID, DRAIN CURRENT (A)
100
0.5
D = 0.5
R θJA (t) = r(t) * R θJA
R θJA = 125 °C/W
0.3
0.2
0.1
0.2
0.1
P(pk)
0.05
t1
0.05
0.03
0.02
0.01
0.0001
0.02
t2
TJ - TA = P * R θJA (t)
0.01
Single Pulse
0.001
0.01
0.1
1
Duty Cycle, D = t 1 / t
2
10
100
300
t 1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS9435A Rev.C
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
Packaging Description:
EL ECT ROST AT IC
SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___gms
MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Customized
Label
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
Pin 1
SOIC (8lds) Packaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Standard
(no flow code)
TNR
2,500
L86Z
F011
D84Z
Rail/Tube
TNR
TNR
95
4,000
500
13" Dia
-
13" Dia
7" Dia
343x64x343
530x130x83
343x64x343
184x187x47
Max qty per Box
5,000
30,000
8,000
1,000
Weight per unit (gm)
0.0774
0.0774
0.0774
0.0774
Weight per Reel (kg)
0.6060
-
0.9696
0.1182
Reel Size
Box Dimension (mm)
SOIC-8 Unit Orientation
Note/Comments
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
F63TNLabel
F63TN Label
LOT: CBVK741B019
QTY: 2500
FSID: FDS9953A
SPEC:
D/C1: D9842
D/C2:
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
ESD Label
(F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape
640mm minimum or
80 empty pockets
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
P0
D0
T
E1
F
K0
Wc
W
E2
B0
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
A0
B0
SOIC(8lds)
(12mm)
6.50
+/-0.10
5.30
+/-0.10
W
12.0
+/-0.3
D0
D1
E1
E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
F
10.25
min
5.50
+/-0.05
P1
P0
8.0
+/-0.1
4.0
+/-0.1
K0
2.1
+/-0.10
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
T
Wc
0.450
+/0.150
9.2
+/-0.3
0.06
+/-0.02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
Tc
0.5mm
maximum
20 deg maximum component rotation
Typical
component
center line
Sketch A (Side or Front Sectional View)
A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SOIC(8lds) Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7" Diameter Option
B Min
Dim C
See detail AA
W3
13" Diameter Option
Dim D
min
W2 max Measured at Hub
DETAIL AA
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 – 0.606
11.9 – 15.4
12mm
7" Dia
7.00
177.8
12mm
13" Dia
13.00
330
 1998 Fairchild Semiconductor Corporation
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
TinyLogic™
UHC™
VCX™
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.