www.fairchildsemi.com FMS6408 Triple Video Filter Driver for RGB and YUV Signals Features Description • 7.6MHz 5th order RGB/YUV/YC CV filters • 50dB stopband attenuation at 27MHz on all outputs • Better than 0.5dB flatness to 4.2MHz on all outputs • No external frequency selection components or clocks • AC coupled inputs and AC or DC coupled outputs • Supports both NTSC and PAL luminance bandwidth • Continuous time low pass filters for video anti-aliasing or reconstruction applications • <1% differential gain with 0.5° differential phase on all channels • Integrated DC restore circuitry with low tilt The FMS6408 provides three video signal paths including a two-input mux, a video filter and a 6dB gain output driver. The filter bandwidth supports RGB and YUV signals in either NTSC or PAL formats. The video filters approximate a 5th order Butterworth low pass characteristic optimized for minimum overshoot and flat group delay to provide excellent image quality. Four different peaking options are available. The video filters can be bypassed if desired. In a typical application, the RGB or YUV DAC outputs are AC coupled into the filters through the input mux. All channels have DC restore circuitry to clamp the DC input levels during video sync. The clamp pulse derived from the selected Y input controls three independent feedback clamps. All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single (150Ω) or dual (75Ω) video load. The FMS6408 clamp levels can be factory programmed for YUV /RGB (250mV for all channels), YC / YPbPr (250mV on channel 1 and 1.125V on channels 2 and 3) or YC CV (250mV on channels 1 and 3 and 1.125V on channel 2). Applications • Cable set top boxes • Satellite set top boxes • Terrestrial set top boxes • DVD players • Personal Video Recorders (PVR) • Video On Demand (VOD) Functional Block Diagram INMUX (A/B) BYPASS (BYPASS/FILTER) YINA 6dB YOUT 8MHz* YINB gM 250mV Sync Processing UINA 6dB UOUT 6dB VOUT 8MHz* UINB gM 250mV or 1.125V * VINA 8MHz* VINB gM * Factory Selected Clamp and Peaking Levels 250mV or 1.125V * REV. 2C August 31, 2004 DATA SHEET FMS6408 Electrical Specifications (TC = 25˚C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz, 0dB peaking option; unless otherwise noted) Symbol Parameter Conditions Current1 Min VCC no load Typ ICC Supply Vi Input Voltage Max Vil Digital Input Low1 Bypass, A_NB 0 0.8 V Vih High1 Bypass, A_NB 2.0 VCC V VCLAMP Digital Input Clamp 52 Max Units 1.4 Voltage2 YUV/RGB/CV Inputs PbPr/C Inputs PSRR 86 DC Power Supply Rejection Ratio mA Vpp 250 mV 1.125 V -40 dB AC Electrical Specifications (TC = 25˚C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz, 0dB peaking option; unless otherwise noted) Symbol Parameter Conditions Min Typ APB Passband Response1 4.2MHz -0.5 0 5.6 5.9 1 Max Units dB AVLF Low Frequency Gain (All Channels) at 400kHz ∆AVHF Delta High Frequency at 5MHz (All Channels)3 0dB Peaking Option 0.3 dB 0.4dB Peaking Option 0.7 dB 0.9dB Peaking Option 1.2 dB 1.3dB Peaking Option 1.6 dB All Channels 7.6 MHz fC -3dB Bandwidth 1 48 6.2 dB fSBh Stopband Rejection (All Channels) at 27MHz 52 dB dG Differential Gain All Channels 0.2 % dθ Differential Phase All Channels 0.5 ° THD Total Harmonic Distortion at 3.58MHz 0.2 % SNR SNR All Channels (NTC7 Weighted) 4.2MHz Lowpass, 100kHz Highpass 75 dB HDIST Line-Time Distortion 18µs, 100 IRE Bar TBD % VDIST Field-Time Distortion 130 Lines, 18µs, 100 IRE Bar TBD % tpd Propagation Delay (All Channels) 400kHz 65 ns GD Group Delay (All Channels) to 3.58MHz (NTSC) 14 ns tSKEW tpdSkew Between Any 2 Channels at 400kHz 2 AV(match) Channel Gain Matching1 400kHz 0 TCLAMP Clamp Response Time (All Channels) Settled to 10mV, Initial Condition 0V XTALK Crosstalk (Channel-to-Channel) INMUXISO f1dBWB ns 5 % 5 ms at 1.0MHz -65 dB Input Mux Isolation at 1.0MHz -85 dB Bypass Mode -1dB Bandwidth 1.4Vpp Output All Channels 25 MHz Notes 1. 100% tested at 25°C. 2. Mode selection for YUV/RGB vs. PbPr/YC vs. YC CV operation based on factory programming 3. Peaking Options boost gain by 0dB, 0.4dB, 0.9dB, or 1.3dB from 4.2MHz to 5MHz based on factory programming 2 REV. 2C August 31, 2004 FMS6408 DATA SHEET Factory Programming Options (See Ordering Information Table on Page 9 for current options) Part Name Part Number Clamping Mode Peaking Mode (dB) YOUT Level (mV) UOUT Level (V) VOUT Level (V) FMS6408-1 FMS6408MTC141_NL YPbPr/YC 0 250 1.125 1.125 FMS6408-2 FMS6408MTC142_NL YPbPr/YC 0.4 250 1.125 1.125 FMS6408-3 FMS6408MTC143_NL YPbPr/YC 0.9 250 1.125 1.125 FMS6408-4 FMS6408MTC144_NL YPbPr/YC 1.3 250 1.125 1.125 FMS6408-5 FMS6408MTC145_NL YUV/RGB 0 250 250 250 FMS6408-6 FMS6408MTC146_NL YUV/RGB 0.4 250 250 250 FMS6408-7 FMS6408MTC147_NL YUV/RGB 0.9 250 250 250 FMS6408-8 FMS6408MTC148_NL YUV/RGB 1.3 250 250 250 FMS6408-9 FMS6408MTC149_NL YC/CV 0 250 1.125 250 FMS6408-10 FMS6408MTC1410_NL YC/CV 0.4 250 1.125 250 FMS6408-11 FMS6408MTC1411_NL YC/CV 0.9 250 1.125 250 FMS6408-12 FMS6408MTC1412_NL YC/CV 1.3 250 1.125 250 Note These factory programming options allow a single die to be configured for multiple operating modes. Absolute Maximum Ratings (beyond which the device may be damaged) Parameter Min Max Units VCC -0.3 6 V Analog and Digital -0.3 VCC + 0.3 V Output Current Any One Channel (Do not exceed) 50 mA Input Source Resistance (RS) 300 Ω Note Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded. Reliability Information Parameter Min Typ Junction Temperature Storage Temperature Range -65 Lead Temperature (Soldering, 10s) Thermal Resistance (θJA), JEDEC Standard Multi-layer Test Boards, Still Air Max Units +150 °C +150 °C +300 °C 90 °C/W Recommended Operating Conditions Parameter Temperature Range VCC Range REV. 2C August 31, 2004 Min Typ 0 +4.75 +5.0 Max Units 70 °C +5.25 V 3 DATA SHEET FMS6408 Typical Performance Characteristics (TC = 25˚C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz, 0dB peaking option; unless otherwise noted) SD Group Delay vs. Frequency SD Frequency Response 10 0 40 1 -10 Delay (ns) Gain (10dB/div) 60 2 -20 Mkr Freq. Gain Ref 400kHz 6dB 1 6.91MHz -1dB BW -30 2 3 -40 7.8MHz 27MHz -3dB BW -43.24dB 10 -20 1 = 7.6MHz (31.88ns) 3 -50 5 0 -40 fSBSD = Gain(ref) – Gain(3) = 49.24dB 400kHz 1 20 15 20 25 -60 30 400kHz 5 10 Frequency (MHz) 15 20 25 30 Frequency (MHz) SD Differential Gain SD Noise vs. Frequency -50 0.2 NTSC Differential Gain (%) -60 Noise (dB) -70 -80 -90 -100 -110 0 -0.2 -0.4 -0.6 Min = -0.61 Max = 0.00 ppMax = 0.61 -0.8 -120 0 1.0 2.0 3.0 4.0 5.0 1st 6.0 2nd 3rd 4th 5th 6th Frequency (MHz) SD Differential Phase Bypass Mode Frequency Response 0.05 7 Gain (1dB/div) Differential Phase (deg) VO = 1.4pp 6 0 -0.05 -0.10 -0.15 Min = -0.13 Max = 0.00 ppMax = 0.13 5 1 4 2 3 2 1 Mkr Ref 1 2 Frequency 400kHz 28.75MHz 36.94MHz Gain 6dB -1dB BW -3dB BW 10 20 0 -0.20 1st 2nd 3rd 4th 5th 6th 400kHz 5 15 25 30 35 40 45 Frequency (MHz) Bypass Mode Group Delay vs. Freq. 16 14 Delay (ns) 12 10 8 1 6 4 2 1 = 25MHz (8.99ns) 0 400kHz 5 10 15 20 25 30 35 40 45 Frequency (MHz) 4 REV. 2C August 31, 2004 FMS6408 DATA SHEET Pin Configuration YINA 1 14 VCC UINA 2 13 YOUT VINA 3 12 BYPASS GND 4 11 UOUT Y INB 5 10 GND UINB 6 9 VOUT VINB 7 8 INMUX (A/B) FMS6408 14-pin TSSOP Pin# Pin Type Description 1 YINA Input Y (Luminance) or Green input A, must be connected to a signal which includes sync 2 UINA Input U or Blue input A 3 VINA Input V or Red input A 4 GND Input Must be tied to ground, do not float 5 YINB Input Y (Luminance) or Green input B, must be connected to a signal which includes sync 6 UINB Input U or Blue input B 7 VINB Input V or Red input B 8 INMUX (A/B) Input Mux select, A = ‘1’, B = ‘0’, must be externally tied high or low 9 VOUT Output 10 GND Input 11 UOUT Output 12 BYPASS (Bypass/Filter) Input 13 YOUT Output 14 VCC Input Functional Description Introduction This product is a three channel monolithic continuous time video filter designed for reconstructing YUV, YC CV or RGB signals from a video D/A source. Inputs should be AC coupled while outputs can be either AC or DC coupled. The reconstruction filters approximate a 5th order Butterworth response optimized for minimum overshoot and flat group delay. This provides a maximally flat response in terms of delay and amplitude. Each of the three outputs is capable of driving 2Vpp into 75Ω loads. All channels are clamped during the sync interval to set the appropriate dc output level. Sync tip clamping greatly reduces the effective input time constant allowing the use of small low cost input coupling capacitors. The input will settle to 10mV in 2ms for typical DC shifts present in the video signal. In most applications the input coupling capacitors are 0.1µF. The inputs typically sink 1uA of current during active video. For YUV signals, this translates into a 2mV tilt in a horizontal line at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20µA over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per line. Any reduction in tilt will come with an increase in settling time. REV. 2C August 31, 2004 V or Red output Must to be tied to ground, do not float U or Blue output Filter bypass, BYPASS = ‘1’, FILTER = ‘0’, must be externally tied high or low Y or Green output +5V supply Sync processing is based on the Y/G input channel in all operating modes. Inputs The inputs will typically be driven by either a low impedance source of 1Vpp or the output of a 75Ω terminated line driven by the output of a current DAC. In either case, the inputs must be capacitively coupled to allow the sync-detect and DC restore circuitry to operate properly. Outputs The outputs are low impedance voltage drivers which can handle either a single or dual load. A single load consists of a 75Ω series termination resistor feeding a 75Ω terminated line for a total load at the part of 150Ω. Even when two loads are present (75Ω) the driver will produce a full 2Vpp signal at its output pin. The driver can also be used to drive an AC coupled single or dual load. When driving a dual load either output will still function if the other output connection is inadvertently shorted providing these loads are AC coupled. 5 DATA SHEET FMS6408 Typical Application Diagrams +5V 0.1 uF 1.0 uF 0.1uF 14 1 YINA YINA V CC FMS6408 14L TSSOP 0.1uF 220uF 13 2 UINA UINA YOUT VINA BYPASS GND UOUT 0.1uF 12 3 VINA 220uF 11 4 300k 0.1uF 10 5 YINB YINB GND UINB VOUT 220uF 0.1uF 9 6 UINB 10k 0.1uF 8 7 VINB INMUX (A/B) VINB Figure 1. AC-Coupled YUV Line Driver with Single Video Loads +5V 0.1 uF 0.1uF YINA 0.1uF 1 1.0 uF YINA UINA UINA 75 13 75 12 75 75 Video Cables 75 FMS6408 14L TSSOP 2 14 V CC YOUT 75 0.1uF VINA 3 VINA BYPASS 75 4 GND UOUT 75 11 75 300kΩ 0.1uF YINB 5 Y INB GND 10 75 9 75 75 0.1uF UINB 6 UINB VOUT 75 0.1uF VINB 10kΩ 7 VINB 8 INMUX (A/B) Figure 2. DC-Coupled YUV Line Driver with Dual Video Loads 6 REV. 2C August 31, 2004 FMS6408 DATA SHEET Application Notes Pdiss (Y) = (5V - 1.55V) * 20.6mA = 71mW Output Drive Capability The FMS6408 can drive dual 75Ω loads where each load consists of a 75Ω resistor in series with a 75Ω termination resistor in the driven device. This presents a 150Ω load to the output so two similar loads in parallel look like 75Ω from the output to ground. In some cases it may be desirable to drive a single load on one or more outputs with a dual load on the remaining outputs. This is an acceptable loading condition but might cause a slight degradation in gain matching. Device Power Dissipation The FMS6408 specifications provide a quiescent no-load supply current of 52mA (typical). With a nominal 5V supply, this results in a power dissipation of 260mW. The overall power dissipation can be significantly affected by the applied load, particularly in DC-coupled applications. In order to calculate the total power dissipation the typical output voltages and the loading must be known. The highest power dissipation will occur for YUV video signals that are DC-coupled into dual video loads. Refer to the the diagram in Figure 3 below. Assume a video signal on the Y channel that averages 50% luminance with an output voltage of 1.55V then calculate the load current: Iload (Y) = 1.55V/75Ω = 20.6mA The average DC level for the U and V channels is set by the clamp circuit to 1.125V. The signal will be symmetrical about this voltage so: Iload (U) = 1.125V/75Ω = 15mA The device dissipation due to this load will be the internal voltage drop multiplied by the load current: Pdiss (U) = (5V - 1.125V) * 15mA = 58.125mW Since the U and V power dissipation are approximately the same, the total dissipation due to the load can be estimated by: Pdiss (load) = P (Y) + 2 * P (U) = 71mW + (2 * 58.125mW) = 187.55mW This will bring the typical total device power dissipation to 260mW (quiescent power) + 187.55mW (load power) or 447.55mW. It is advisable to calculate the highest possible power dissipation using worst-case quiescent supply current and the maximum allowable power supply voltage. This result should be used when calculating the die temperature rise with the supplied θJA, thermal resistance value. Field Time Distortion In applications with AC-coupled outputs, the AC-coupling capacitors will dominate the field time distortion. Performance is specified with 220µF coupling capacitors; if better performance is desired, the capacitors may be increased or the outputs may be DC-coupled. The device dissipation due to this load will be the internal voltage drop multiplied by the load current: +5V VCC 2.25V 75Ω 1.55V IY Driver YOUT 75Ω 0.85V 0.25V 75Ω 1.825V 75Ω 75Ω + VIY - 1.125V IU Driver 0.425V UOUT 75Ω 75Ω 75Ω + VIU 1.825V 75Ω 1.125V IV Driver + VIV - 75Ω Video Cables 0.425V VOUT 75Ω 75Ω 75Ω Figure 3. YUV Video Signals that are DC-Coupled into Dual Video Loads REV. 2C August 31, 2004 7 DATA SHEET FMS6408 Package Dimensions MTC-14 6 e –B– 7 N 5 (b) 2X E/2 1.0 DIA MTC-14 8 E1 E c c1 1.0 b1 ddd C B A 2X N/2 TIPS 1 2 3 6 SECTION AA e /2 9 1.0 ccc 7 –A– A2 D 8 3 aaa C A –C– b NX A1 (02) (0.20) bbb M C B A R1 –H– R GAGE PLANE 10 A 0.25 (03) A L (L1) 01 SYMBOL A A1 A2 L R R1 b b1 c c1 01 L1 aaa bbb ccc ddd e 02 03 D E1 E e N MIN – 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 4.90 4.30 NOM – – 0.90 0.60 – – – 0.22 – – – 1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF 5.00 4.40 6.4 BSC 0.65 BSC 14 MAX 1.10 0.15 0.95 0.75 – – 0.30 0.25 0.20 0.16 8 5.10 4.50 NOTES: 1 All dimensions are in millimeters (angle in degrees). 2 Dimensioning and tolerancing per ASME Y14.5–1994. 3 Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side . 4 Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side. 5 Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. 6 Terminal numbers are shown for reference only. 7 Datums – A – and – B – to be determined at datum plane – H – . 8 Dimensions "D" and "E1" to be determined at datum plane – H – . 9 This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center" lead must be coincident with the package centerline, Datum A. 10 Cross sections A – A to be determined at 0.10 to 0.25mm from the leadtip. 8 REV. 2C August 31, 2004 FMS6408 DATA SHEET Ordering Information Mode Output Peaking Package Container Pack Qty FMS6408MTC141_NL YUV/RGB 0dB TSSOP-14 Tube 94 FMS6408 FMS6408MTC141X_NL YUV/RGB 0dB TSSOP-14 Tape and Reel 2500 FMS6408 FMS6408MTC143_NL YUV/RGB 0.9dB TSSOP-14 Tube 94 FMS6408 FMS6408MTC143X_NL YUV/RGB 0.9dB TSSOP-14 Tape and Reel 2500 Model Part Number FMS6408 Lead Free Temperature range for all parts: 0°C to +70°C. Contact Fairchild for ordering information regarding other clamping and peaking options. Refer to the Factory Programming Options Table on page 3 for a detailed description of available options. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to per form when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2004 Fairchild Semiconductor Corporation