TM FQD18N20V2 / FQU18N20V2 200V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as automotive, high efficiency switching for DC/DC converters, and DC motor control. • • • • • • 15A, 200V, RDS(on) = 0.14Ω @VGS = 10 V Low gate charge ( typical 20 nC) Low Crss ( typical 25 pF) Fast switching 100% avalanche tested Improved dv/dt capability D ! D " ! " " " G! G S I-PAK D-PAK FQD Series G D S ! FQU Series S Absolute Maximum Ratings Symbol VDSS ID TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current FQD18N20V2 / FQU18N20V2 200 Units V 15 A - Continuous (TC = 100°C) IDM Drain Current - Pulsed (Note 1) 9.75 A 60 A ± 30 V 340 mJ VGSS Gate-Source Voltage EAS Single Pulsed Avalanche Energy (Note 2) IAR Avalanche Current (Note 1) 15 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) * (Note 1) 8.3 6.5 2.5 mJ V/ns W 83 0.67 -55 to +150 W W/°C °C 300 °C dv/dt PD (Note 3) Power Dissipation (TC = 25°C) TJ, TSTG TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJC Parameter Thermal Resistance, Junction-to-Case Typ -- Max 1.5 Units °C/W RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W * When mounted on the minimum pad size recommended (PCB Mount) ©2002 Fairchild Semiconductor Corporation Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 QFET Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 200 -- -- V -- 0.25 -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C IDSS IGSSF IGSSR VDS = 200 V, VGS = 0 V -- -- 1 µA VDS = 160 V, TC = 125°C -- -- 10 µA Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA 3.0 -- 5.0 V -- 0.12 0.14 Ω -- 11 -- S -- 830 1080 pF -- 200 260 pF -- 25 33 pF -- 70 -- pF -- 135 -- pF ns Zero Gate Voltage Drain Current On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 7.5 A gFS Forward Transconductance VDS = 40 V, ID = 7.5 A (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance Coss eff. Effective Output Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz VDS = 160 V, VGS = 0 V, f = 1.0 MHz VDS = 0V to 160 V, VGS = 0 V Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 100 V, ID = 18 A, RG = 25 Ω (Note 4, 5) VDS = 160 V, ID = 18 A, VGS = 10 V (Note 4, 5) -- 16 40 -- 133 275 ns -- 38 85 ns -- 62 135 ns -- 20 26 nC -- 5.6 -- nC -- 10 -- nC A Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 15 ISM -- -- 60 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 15 A Drain-Source Diode Forward Voltage -- -- 1.5 V trr Reverse Recovery Time -- 158 -- ns Qrr Reverse Recovery Charge -- 1.0 -- µC VGS = 0 V, IS = 18 A, dIF / dt = 100 A/µs (Note 4) Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 1.58mH, IAS = 18A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 18A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2002 Fairchild Semiconductor Corporation Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 Electrical Characteristics VGS Top : 15.0 V 10.0 V 10 8.0 V 1 1 ID , Drain Current [A] ID, Drain Current [A] 7.0 V 6.5 V 6.0 V Bottom : 10 5.5 V 0 ※ Notes : 10 -1 150℃ 10 25℃ -55℃ 0 10 1. 250μ s Pulse Test ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test 2. TC = 25℃ 10 -1 10 0 10 1 -1 10 4 VDS, Drain-Source Voltage [V] 5 6 7 8 9 10 VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.4 IDR , Reverse Drain Current [A] R DS(ON) [Ω ], Drain-Source On-Resistance 0.5 VGS = 10V VGS = 20V 0.3 0.2 0.1 1 10 0 10 150℃ 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test ※ Note : TJ = 25℃ 0.0 0 10 20 30 40 50 60 -1 10 ID, Drain Current [A] 0.2 0.4 0.6 0.8 Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage 1.2 1.4 1.6 Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12 2500 Ciss = C gs + Cgd (Cds = shorted) VDS = 40V Coss = Cds + Cgd ※ Notes : 1500 1. VGS = 0 V 2. f = 1 MHz Ciss 1000 Coss 500 Crss VGS , Gate-Source Voltage [V] 10 Crss = C gd 2000 Capacitance [pF] 1.0 VSD , Source-Drain Voltage [V] VDS = 100V VDS = 160V 8 6 4 2 ※ Note : ID = 18A 0 -1 10 10 0 10 1 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2002 Fairchild Semiconductor Corporation 0 0 5 10 15 20 25 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 Typical Characteristics (Continued) 3.0 2.5 R DS(ON) , (Normalized) 1.1 1.0 ※ Notes : 0.9 1. VGS = 0 V 2. ID = 250 μ A Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 1.2 2.0 1.5 1.0 ※ Notes : 0.5 1. VGS = 10 V 2. ID = 7.5 A 0.8 -100 -50 0 50 100 150 0.0 -100 200 -50 0 50 100 o TJ, Junction Temperature [ C] 150 200 o TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 20 Operation in This Area 10 is Limited by R DS(on) 2 10 ID, Drain Current [A] ID , Drain Current [A] 15 100 us 1 ms 1 10 ms DC 10 0 ※ Notes : o 1. TC = 25 C 10 5 o 2. TJ = 150 C 3. Single Pulse -1 0 25 10 0 1 10 10 10 2 50 75 D = 0 .5 0 .2 ※ 0 .1 10 -1 N o te s : 1. Z 0 .0 5 θ JC (t) = 1 .5 ℃ /W M a x . 2 . D u ty F a c to r, D = t1 /t2 3. T 0 .0 2 0 .0 1 JM - T C = P * Z D M θ JC (t) PDM JC (t) , T h e r m a l R e s p o n s e 150 0 s in g le p u ls e t1 θ Z 125 Figure 10. Maximum Drain Current vs. Case Temperature Figure 9. Maximum Safe Operating Area 10 100 TC, Case Temperature [℃] VDS, Drain-Source Voltage [V] 10 -2 10 t2 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t1 , S q u a r e W a v e P u ls e D u r a t io n [s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 Typical Characteristics FQD18N20V2 / FQU18N20V2 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2002 Fairchild Semiconductor Corporation ID (t) VDS (t) VDD tp Time Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2002 Fairchild Semiconductor Corporation Rev. B1, August 2002 DPAK MIN0.55 0.91 ±0.10 9.50 ±0.30 0.50 ±0.10 0.76 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30TYP [2.30±0.20] (1.00) (3.05) (2XR0.25) (0.10) 2.70 ±0.20 6.10 ±0.20 9.50 ±0.30 6.60 ±0.20 (5.34) (5.04) (1.50) (0.90) 2.30 ±0.20 (0.70) 2.30TYP [2.30±0.20] (0.50) 2.30 ±0.10 0.89 ±0.10 MAX0.96 (4.34) 2.70 ±0.20 0.80 ±0.20 0.60 ±0.20 (0.50) 6.10 ±0.20 5.34 ±0.30 0.70 ±0.20 6.60 ±0.20 0.76 ±0.10 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 Package Dimensions (Continued) IPAK 2.30 ±0.20 6.60 ±0.20 5.34 ±0.20 0.76 ±0.10 2.30TYP [2.30±0.20] 0.50 ±0.10 16.10 ±0.30 6.10 ±0.20 0.70 ±0.20 (0.50) 9.30 ±0.30 MAX0.96 (4.34) 1.80 ±0.20 0.80 ±0.10 0.60 ±0.20 (0.50) 2.30TYP [2.30±0.20] 0.50 ±0.10 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. B1, August 2002 FQD18N20V2 / FQU18N20V2 Package Dimensions TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ Bottomless™ FAST® CoolFET™ FASTr™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ EnSigna™ I2C™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2002 Fairchild Semiconductor Corporation Rev. I1