FAIRCHILD FST3306

Revised February 2001
FST3306
2-Bit Low Power Bus Switch
General Description
Features
The FST3306 is a 2-bit ultra high-speed CMOS FET bus
switch with TTL-compatible active LOW control inputs. The
low on resistance of the switch allows inputs to be connected to outputs with minimal propagation delay and without generating additional ground bounce noise. The device
is organized as a 2-bit switch with independent bus enable
(BE) controls. When BE is LOW, the switch is ON and
Port A is connected to Port B. When BE is HIGH, the
switch is OPEN and a high-impedance state exists
between the two ports. Control inputs tolerate voltages up
to 5.5V independent of VCC.
■ Typical 3Ω switch resistance at 5.0V VCC
■ Minimal propagation delay through the switch
■ Power down high impedance input/output
■ Zero bounce in flow through mode.
■ TTL compatible active LOW control inputs
■ Control inputs are overvoltage tolerant
Ordering Code:
Order Number
Package Number
FST3306MTC
MTC08
Package Description
8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
(Top View)
Pin Descriptions
Function Table
Pin Name
Description
Bus Enable Input BE
Function
A
Bus A
L
B Connected to A
H
Disconnected
B
Bus B
BE
Bus Enable Input
© 2001 Fairchild Semiconductor Corporation
DS500479
H = HIGH Logic Level
L = LOW Logic Level
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FST3306 2-Bit Low Power Bus Switch
February 2001
FST3306
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC)
−0.5V to +7.0V
DC Switch Voltage (VS)
−0.5V to +7.0V
Supply Operating (VCC)
DC Output Voltage (VIN) (Note 2)
−0.5V to +7.0V
Control Input Voltage (VIN)
0V to 5.5V
Switch Input Voltage (VIN)
0V to 5.5V
DC Input Diode Current
(IIK) VIN < 0V
DC Output (IOUT) Current
Storage Temperature Range (TSTG)
−50 mA
Output Voltage (VOUT)
128 mA
Operating Temperature (TA)
±100 mA
DC VCC or Ground Current (ICC/GND)
0V to 5.5V
−40°C to +85°C
Input Rise and Fall Time (tr, tf)
−65°C to +150°C
Control Input
+150°C
Junction Lead Temperature under Bias (TJ)
4.0V to 5.5V
0 ns/V to 5 ns/V
Switch I/O
0 ns/V to DC
Thermal Resistance (θJA)
Lead Temperature (TL)
250°C/W
+260°C
(Soldering, 10 seconds)
Power Dissipation (PD) @ +85°C
250 mW
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused logic inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
Parameter
TA = −40°C to +85°C
VCC
(V)
Min
Typ
Max
−1.2
VIK
Clamp Diode Voltage
VIH
HIGH Level Input Voltage
4.0–5.5
VIL
LOW Level Input Voltage
4.0–5.5
VOH
HIGH Level Output Voltage
4.5–5.5
IIN
Input Leakage Current
5.5
IOFF
Switch OFF Leakage Current
5.5
RON
Switch On Resistance
4.5
3
7
(Note 4)
4.5
3
7
4.5
6
15
4.0
10
20
4.5
ICC
Quiescent Supply Current
5.5
∆ICC
Increase in ICC per Input
5.5
2.0
Units
V
Conditions
IIN = −18 mA
V
0.8
V
±1.0
µA
0 ≤ VIN ≤ 5.5V
±1.0
µA
0 ≤ A, B, ≤ VCC
see Figure 3
V
VIN = VCC
VIN = 0V, IIN = 64 mA
Ω
VIN = 0V, IIN = 30 mA
VIN = 2.4V, IIN = 15 mA
VIN = 2.4V, IIN = 15 mA
3
µA
VIN = VCC or GND,
2.5
mA
VIN = 3.4V, IO = 0,
IOUT = 0
1
(Note 5)
Control Input Only
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins.
Note 5: Per TTL driven input (VIN = 3.4V, control input only). A and B pins do not contribute to ICC.
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TA = −40°C to +85°C
Symbol
Parameter
CL = 50 pF, RU = RD = 500Ω
VCC
(V)
tPHL,
Prop Delay Bus to Bus
tPLH
(Note 6)
tPZL,
Output Enable Time
tPZH
tPLZ,
Output Disable Time
tPHZ
Min
Typ
4.0–5.5
Units
Conditions
Figure
Number
Max
0.25
4.5–5.5
0.8
2.5
4.2
4.0
0.8
3.0
4.6
4.5–5.5
0.8
3.1
4.8
4.0
0.8
2.9
4.4
ns
ns
VI = OPEN
Figures
1, 2
VI = 7V for tPZL
Figures
1, 2
VI = 0V for tPZH
VI = 7V for tPLZ
ns
Figures
1, 2
VI = 0V for tPHZ
Note 6: This parameter is guaranteed. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch
and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). The specified limit is calculated on this basis.
Capacitance
Symbol
Parameter
Typ
Max
2.5
Units
pF
Conditions
VCC = 0V
CIN
Control Pin Input Capacitance
CI/O (OFF)
Port OFF Capacitance
6
pF
VCC = 5.0V = BE
CI/O (ON)
Switch ON Capacitance
12
pF
VCC = 5.0V, BE = 0V
AC Loading and Waveforms
Input driven by 50Ω source terminated in 50Ω.
CL includes load and stray capacitance.
Input PRR = 1.0 MHz tw = 500 ns.
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FST3306
AC Electrical Characteristics
FST3306
DC Characteristics
FIGURE 3. Typical High Level Output Voltage vs. Supply Voltage
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FST3306 2-Bit Low Power Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC08
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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user.
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