G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Features : Description : ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ GLT725608 is high performance 256K bit static random access memory organized as 32K by 8 bits and operate at a single 5 volt supply. Fabricated with G-Link Technology's very advanced CMOS submicron technology, GLT725608 offer a combination of features: very high speed and very low stand-by current. In addition, this device also supports easy memory expansion with an active LOW chip enable ( CE ) as well as an active LOW output enable ( OE ) and three state outputs. Pin Configurations : Function Block Diagram : 32K x 8-bit organization. Very high speed 12,15,20 ns. Low standby power. Fully static operation 5V±10% power supply. TTL compatible I/O. Three state output. Chip enable for simple memory expansion. Available 300 mil SOJ, 28 pin TSOP and 330 mil SOP Packages. ∗ Industrial Grade Available (-40°C ~ 85°C). SOJ and SOP G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Pin Descriptions: Name Function A0 - A14 Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input and Data Output +5V Power Supply Ground CE OE WE I/O0 - I/O7 VCC GND Truth Table: Mode Not Selected (Power Down) Output Disabled Read Write WE CE OE X H X H H L L L L H L X I/O Operation High Z VCC Current ICCSB , ICCSB1 High Z ICC ICC ICC D OUT DIN Operation Range : Absolute Maximum Ratings: Ambient Temperature Under Bias...................................-10°C to +80°C Storage Temperature(plastic)....-55°C to +125°C Voltage Relative to GND.............-0.5V to + 7.0V Data Output Current..................................50mA Power Dissipation......................................1.0W Range Temperature Vcc Commercial 0°C to + 70°C 5V ± 10% Industrial -40°C to 85°C 5V ± 10% Capacitance (1)TA=25°°C,f=1.0MHZ : Sym. 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CIN CI/O Parameter Input Capacitance Input / output Capacitance conditions Max. Unit VIN = 0V 8 pF VI/O = 0V 10 pF G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) DC Characteristics Sym. VIL VIH ILI ILO VOL VOH ICC Parameter Test Conditions Min. Typ(1) Max. Unit -0.3 - +0.8 V 2.2 - VCC+0.3 V -5 -5 - 5 5 µA µA 2.4 - - 0.4 -12 -15 -20 160 150 120 V V mA 40 30 20 mA 10 10 10 mA Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current VCC= Max., VIN=0V to VCC Output Leakage Current V = Max., CE ≥V CC IH Output Low Voltage VCC= Min., IOL =8mA Output High Voltage VCC= Min., IOH =-4mA Operating Power Supply V = Max., CE ≤V , CC IL Current I =0mA., F= F (3) I/O max ICCSB Standby Power Supply Current VCC= Max., CE ≥VIH, II/O=0mA., F= Fmax(3) - ICCSB1 Power Down Power Supply Current VCC= Max., CE ≥VCC.-0.2V, VIN≥VCC. -0.2V or - - 1. Typical characteristics are at VCC=5V, TA=25 2. These are absolute values with reject to device ground and all overshoots due to system or tester noise are included. 3. FMAX=1/tRC. Data Retention Sym. VDR Parameter VCC for Data retention ICCDR(1) Data Retention Current tCDR tR Test Conditions CE ≥ VCC -0.2V, Min. Typ(1) Max. Unit 2.0 - 5.5 V - µA µA ns ns VIN ≥ VCC -0.2V or VIN ≤ 0.2V VDR=2.0V VDR=3.0V Chip Deselect to Data Retention Time See Retention Waveform Operating Recovery Time 0 - 30 50 - tRC(2) - - 1. CE ≥ VDR -0.2V, VIN ≥ VDR -0.2V or VIN ≤ 0.2V. 2. tRC =Read Cycle Time. G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Low VCC Data Retention Waveform ( CE Controlled) AC Test Conditions Input Pulse Levels Input Rise and Fall Times Timing Reference Level 0V to 3.0V 3 ns 1.5V AC Test Loads and Waveforms Ω Ω Ω Ω Ω AC Electrical Characteristics Read Cycle JEDEC Parameter Parameter Name Name tAVAX tRC Read Cycle Time 725608-12 725608-15 725608-20 Parameter Min. Max. tAVQV tE1LQV tAA tACS Address Access Time tGLQV tE1LQX tOE tCLZ tGLQX tOLZ tE1HQZ tCHZ tGHQZ tOHZ Chip Deselect to Output in High Z, CE Output Disable to Output in High Z tAXQX tOH Output Hold from Address Change Chip Select Access Time, CE Output Enable to Output Valid Chip Select to Output Low Z, CE Output Enable to Output in Low Z 12 - 12 12 3 Min. Max. Min. Max. 20 - 20 20 ns ns ns 5 - 3 6 - 3 8 - ns ns 3 - 7 3 - 8 3 - 10 ns ns 3 6 - 3 6 - 3 8 - ns ns G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- Unit 15 - 15 - 15 G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Switching Waveform (Read Cycle) READ CYCLE 1 (1,2,4) READ CYCLE 2 (1,3,4) READ CYCLE 3 (1) Notes: 1. WE is High for READ Cycle. 2. Device is continuously selected CE ≤VIL. 3. Address valid prior to or coincident with CE transition low and/or transition high. 4. OE ≤VIL. 5. Transition is measured ±200mV from steady state with CL=5pF. G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) AC Electrical Characteristics Write Cycle JEDEC Parameter Parameter Name Name tAVAX tWC Write Cycle Time Parameter tE1LWH tAVWL tCW tAS Chip Select to End of Write Address Set up Time tAVWH tWLWH tWHAX tAW tWP tWR1 Address Valid to End of Write Write Pulse Width tE2LAX tWR2 tWLQZ tDVWH tWHDX tWHQX tWHZ tDW tDH tOW Write Recovery Time, WE Write Recovery Time, CE Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Active 725608-12 725608-15 725608-20 Min. Max. Min. Max. Min. Max. Unit 12 10 0 10 10 0 - 15 12 0 12 12 0 - 20 15 0 15 15 0 - ns ns ns ns ns ns 0 - 0 - 0 - ns 6 0 3 7 - 7 0 3 8 - 8 0 3 10 - ns ns ns ns Switching Waveforms(Write Cycle) (1) WRITE CYCLE 1 G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Switching Waveform (Write Cycle) WRITE CYCLE 2(1,6) Note: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap CE low and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state. 6. OE is continuously low ( OE =VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ±200mV from steady state with CL=5pF. 11. tCW is measured from CE going low to the end of write. G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Ordering Information Part Number SPEED POWER PACKAGE GLT725608-12J3 GLT725608-15J3 GLT725608-20J3 GLT725608-12TS GLT725608-15TS GLT725608-20TS GLT725608-12TC GLT725608-15TC GLT725608-20TC GLT725608-12FB GLT725608-15FB GLT725608-20FB 12ns 15ns 20ns 12ns 15ns 20ns 12ns 15ns 20ns 12ns 15ns 20ns Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal SOJ 300mil 28L SOJ 300mil 28L SOJ 300mil 28L TSOP 28L TSOPI 28L TSOPI 28L TSOPII 28L TSOPII 28L TSOPII 28L SOP 330mil 28L SOP 330mil 28L SOP 330mil 28L Parts Numbers (Top Mark) Definition : GLT 7 256 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) 160 : 16M(EDO) 161 : 16M(FPM) 08 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 VOLTAGE Blank : 5V L : 3.3V M : 2.5V N : 2.1V I - 12 TC SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP Temperature Range E : Extended Temperature I : Industrial Temperature Blank : Commercial Temperature G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Package Information 300mil 28 Lead Small Outline J-form Package (SOJ) G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) 28L (8×13.4 mm) Thin Small Outline Package (TSOP) Type I G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) 28L (8×20mm) Thin Small Outline Package (TSOP) Type I G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) 330mil 28 Lead Thin Small Outline (Gull-Wing) Package (SOP) G-Link Technology G-Link Technology Corporation, Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 -