128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark Preliminary 0.1 Initial Draft Jul. 2009 1.0 Release Aug. 2009 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Aug. 2009 1 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series H57V1262GTRDESCRIPTION The Hynix H57V1262GTR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. H57V1262GTR series is organized as 4banks of 2,097,152 x 16. H57V1262GTR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES • Programmable Burst Length and Burst Type • Voltage: VDD, VDDQ 3.3V supply voltage • All device pins are compatible with LVTTL interface - 1, 2, 4, 8 or full page for Sequential Burst • 54 Pin TSOPII (Lead Free Package) - 1, 2, 4 or 8 for Interleave Burst • All inputs and outputs referenced to positive edge of system clock • Data mask function by UDQM, LDQM • Internal four banks operation • Auto refresh and self refresh • 4096 Refresh cycles / 64ms • Programmable CAS Latency; 2, 3 Clocks • Burst Read Single Write operation • Operating Temperature - Commercial Temperature (0oC to 70oC) - Industrial Temperature (-40oC to 85oC) ● This product is in compliance with the directive pertaining of RoHS. ORDERING INFORMATION Part No. Clock Frequency H57V1262GTR-50X 200MHz H57V1262GTR-60X 166MHz H57V1262GTR-70X 143MHz H57V1262GTR-75X 133MHz Organization Interface Package 4Banks x 2Mbits x16 LVTTL 54 Pin TSOPII Note: 1. H57V1262GTR-XXC Series: Normal power, Commercial Temp.(0oC to 70oC) 2. H57V1262GTR-XXI Series: Normal power, Industrial Temp. (-40oC to 85oC) 3. H57V1262GTR-XXL Series: Low power, Commercial Temp.(0oC to 70oC) 4. H57V1262GTR-XXJ Series: Low power, Industrial Temp. (-40oC to 85oC) Rev. 1.0 / Aug. 2009 2 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series PIN ASSIGNMENTS VDD 1 54 VSS DQ0 2 53 DQ15 VDDQ 3 52 VSSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSSQ 6 49 VDDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 VDDQ 9 46 VSSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 VDD 14 41 VSS LDQM 15 40 NC /WE 16 39 UDQM /CAS 17 38 CLK /RAS 18 37 CKE /CS 19 36 NC BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS Rev. 1.0 / Aug. 2009 54 Pin TSOPII 400mil x 875mil 0.8mm pin pitch 3 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series PIN DESCRIPTION SYMBOL TYPE DESCRIPTION CLK Clock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select BA0, BA1 Bank Address A0 ~ A11 Address RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details UDQM, LDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode DQ0 ~ DQ15 Data Input/Output VDD/VSS Power Supply/Ground VDDQ/VSSQ Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8 Auto-precharge flag: A10 Multiplexed data input / output pin Power supply for internal circuits and input buffers Data Output Power/Ground Power supply for output buffers NC Rev. 1.0 / Aug. 2009 No Connection No connection 4 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM Internal Row Counter Self refresh logic & timer 2Mx16 BANK 3 CLK CAS Column Active U/LDQM A0 Address Buffers BA1 DQ0 DQ15 Y-Decoder Column Add Counter Bank Select A11 Memory Cell Array Column Pre Decoder WE A1 2Mx16 BANK 0 I/O Buffer & Logic Refresh 2Mx16 BANK 1 Sense AMP & I/O Gate State Machine RAS 2Mx16 BANK 2 X-Decoder X-Decoder X-Decoder X-Decoder CKE CS Row Pre Decoder Row Active Address Register Mode Register Burst Counter CAS Latency Data Out Control Pipe Line Control BA0 Rev. 1.0 / Aug. 2009 5 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 OP Code 0 0 A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length OP Code A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write Burst Type A3 Burst Type 0 Sequential 1 Interleave CAS Latency A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 1 0 1 Burst Length A2 A1 A0 3 0 0 0 Reserved 0 0 1 Reserved 1 1 0 1 1 1 Rev. 1.0 / Aug. 2009 Burst Length A3 = 0 A3=1 0 1 1 0 1 2 2 0 1 0 4 4 Reserved 0 1 1 8 8 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved 6 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series ABSOLUTE MAXIMUM RATING Parameter Symbol Commercial Temperature Ambient Temperature Unit 0 ~ 70 TA Industrial Temperature Storage Temperature Rating o C -40 ~ 85 TSTG -55 ~ 125 Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 W TSOLDER 260 / 10 Soldering Temperature / Time o C oC / Sec DC OPERATING CONDITION (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC) Parameter Symbol Min. Typ Max Unit Note VDD, VDDQ 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1, 2 Input Low Voltage VIL -0.3 - 0.8 V 1, 3 Power Supply Voltage Note: 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration AC OPERATING TEST CONDITION (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC, VDD=3.3±0.3V, VSS=0V) Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V CL 50 pF AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Vtt = 1.4V Vtt = 1.4V RT = 50Ω RT = 500 Ω Output Output Z0 = 50Ω 50pF DC Output Load Circuit Rev. 1.0 / Aug. 2009 Note 50pF AC Output Load Circuit 7 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series CAPACITANCE (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC, f=1MHz, VDD=3.3V) Parameter Input capacitance Pin Symbol Min Max Unit CLK CI1 2.0 4.0 pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM CI2 2.5 5.0 pF CI/O 3.0 5.5 pF Data input / output capacitance DQ0 ~ DQ15 DC CHARACTERISTICS I (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC) Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -2mA Output Low Voltage VOL - 0.4 V IOL = +2mA Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Rev. 1.0 / Aug. 2009 8 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series DC CHARACTERISTICS II Parameter Operating Current (Commercial: TA = 0oC to 70oC, Industrial: TA = -40oC to 85oC) Symbol IDD1 Test Condition Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA Speed (MHz) 200 166 143 133 100 80 70 CKE ≤ VIL(max), tCK = 15ns Precharge Standby Current IDD2P in Power Down Mode IDD2PS CKE ≤ VIL(max), tCK = ∞ Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode mA 2 mA 18 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 15 IDD3P CKE ≤ VIL(max), tCK = 15ns 5 IDD3NS 1 mA IDD3PS CKE ≤ VIL(max), tCK = ∞ IDD3N mA 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V IDD2N 70 Unit Note mA 5 CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 40 CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 35 mA Burst Mode Operating CurIDD4 rent tCK ≥ tCK(min), IOL=0mA All banks active 120 100 100 100 mA 1 Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 210 200 190 190 mA 2 Self Refresh Current IDD6 CKE ≤ 0.2V Normal 2 mA Low power 800 uA 3 Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. H57V1262GTR-XXC Series: Normal Power H57V1262GTR-XXL Series: Low Power Rev. 1.0 / Aug. 2009 9 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Speed (MHz) Parameter 200 166 143 133 Min Max Min Max Min Max Min Max CL = 3 tCK3 5.0 6.0 7.0 CL = 2 tCK2 - Clock High Pulse Width tCHW 1.75 - 2.0 - 2.0 - Clock Low Pulse Width tCLW 1.75 - 2.0 - 2.0 CL = 3 tAC3 - 4.5 - 5.4 CL = 2 tAC2 - - - Data-out Hold Time tOH 2.0 - Data-Input Setup Time tDS 1.5 Data-Input Hold Time tDH Address Setup Time 7.5 Unit Note 100 0 ns 2.5 - ns 1 - 2.5 - ns 1 - 5.4 - 5.4 ns - - - - 6.0 ns 2.0 - 2.5 - 2.7 - ns - 1.5 - 1.5 - 1.5 - ns 1 0.8 - 0.8 - 0.8 - 0.8 - ns 1 tAS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Address Hold Time tAH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 Command Setup Time tCS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Command Hold Time tCH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - 1.5 - 1.5 - ns System Clock Cycle Time Access Time From Clock CLK to Data Output in High-Z Time 1000 - 1000 - 1000 10 ns CL = 3 tOHZ3 - 4.5 - 5.4 - 5.4 - 5.4 ns CL = 2 tOHZ2 - - - - - - - 6.0 ns 2 Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev. 1.0 / Aug. 2009 10 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Speed (MHz) 200 166 143 Min Max Min Max Min 133 Max Min Max Unit Note RAS Cycle Time Operation tRC 55 - 60 - 63 - 63 - ns RAS Cycle Time Auto Refresh tRRC 55 - 60 - 63 - 63 - ns RAS to CAS Delay tRCD 15 - 18 - 20 - 20 - ns RAS Active Time tRAS 42 100K 42 100K 42 120 K ns RAS Precharge Time tRP 15 - 18 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 10 - 12 - 14 - 15 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - CLK Data-in to Precharge Command tDPL 2 - 2 - 2 - 2 - CLK Data-In to Active Command tDAL DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - 2 - CLK CL = 3 tPROZ3 3 - 3 - 3 - 3 - CLK CL = 2 tPROZ2 - - - - - - 2 - CLK Power Down Exit Time tDPE 1 - 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 - 64 ms Precharge to Data Output High-Z 38.7 100K tDPL + tRP 1 Note: 1. A new command can be given tRRC after self refresh exit. Rev. 1.0 / Aug. 2009 11 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X RA Read Read with charge A10/AP BA V L Autopre- H X L H L H X CA Write H V L H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-SingleWRITE H X L L L L X A9 ball High (Other balls OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Write with charge Autopre- Precharge All Banks Precharge selected Bank Self Refresh X Precharge power down Clock Suspend Note Exit L H Entry H L Exit L H Rev. 1.0 / Aug. 2009 X X H V H X L V MRS Mode X X X X X X X 12 Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GTR Series PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 0.80(0.0315)BSC Rev. 1.0 / Aug. 2009 0.400(0.016) 0.300(0.012) 1.194(0.0470) 0.991(0.0390) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 13