HCF4541B PROGRAMMABLE TIMER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 16 STAGE BINARY COUNTER LOW SYMMETR. OUTPUT RESISTANCE, TYPICALLY 100Ω at VDD = 15V OSCILLATOR FREQUENCY RANGE : DC to 100KHz AUTO OR MASTER RESET DISABLES OSCILLATOR DURING RESET TO REDUCE POWER DISSIPATION OPERATES WITH VERY SLOW CLOCK RISE AND FALL TIMES BUILT-IN LOW-POWER RC OSCILLATOR EXTERNAL CLOCK (applied to pin 3) CAN BE USED INSTEAD OF OSCILLATOR OPERATES AS 2n FREQUENCY DIVIDER OR AS A SINGLE-TRANSITION TIMER Q/Q SELECT PROVIDES OUTPUT LOGIC LEVEL FLEXIBILITY CAPABLE OF DRIVING SIX LOW POWER TTL LOADS, THREE LOW POWER SCHOTTKY LOADS, OR SIX HTL LOADS OVER THE RATED TEMP. RANGE 5V, 10V AND 15V PARAMETRIC RATINGS 100% TESTED FOR QUIESCENT CURRENT AT 20V MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4541BEY HCF4541BM1 HCF4541M013TR DESCRIPTION The HCF4541B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. This device is composed of a 16-stages binary counter, an oscillator controlled by 2 external resistors and a capacitor, an output control logic and an automatic power-on reset circuit. The counter varies on positive-edge clock transition and it can be cleared by the MASTER RESET input. The output from this timer is the Q or Q output from the 8th, 13th, or 16th counter stage. The choice of the stage depends on the time PIN CONNECTION September 2002 1/10 HCF4541B select inputs A or B (see frequency selection table). The output is available in one of the two modes that can be selected via the MODE input pin 10 (see truth table). The output turns out as a continuos square wave, with a frequency equal to the oscillator frequency divided by 2N when this MODE input is a logic "1". When it is a logic "0" and after a MASTER RESET is started, and Q output has been selected, the output goes up to a high state after 2 N-1 counts. It remains in that state till another MASTER RESET pulse is apply or the mode input is a logic "1". The process starts by setting the AUTO RESET input (pin 5) to logic INPUT EQUIVALENT CIRCUIT "0" and switching power on. If pin 5 is set to logic "1", the AUTO RESET circuit is not enabled and counting cannot start till a positive MASTER RESET pulse is applied, returning to a low level. The AUTO RESET consumes a remarkable amount of power and should not be used if low power operation is wanted. The frequency of the oscillator depends on the RC network. It can be calculated using the following formula : f = 1 / 2.3 RTC CTC where f is between 1KHz and 100KHz and RS > 10 KΩ and ≈2 RTC PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 12, 13 4, 11 A, B NC 1, 2 RTC, CTC 3 RS 5 6 10 7 AR MR MODE Q/Q SELECT Q VSS Time Select Input Not Connected External Resistor, Capacitor Connection External Resistor Connection or External Clock Input Auto Reset Input Master Reset Input Mode Select Input 14 VDD 9 8 RC OSCILLATOR CIRCUIT 2/10 Output Selector Output Negative Supply Voltage Positive Supply Voltage HCF4541B FUNCTIONAL DIAGRAM FREQUENCY SELECTION TABLE TRUTH TABLE A B N. of Stages N Count 2N L L H H L H L H 13 10 8 16 8192 1024 256 65536 STATE PIN 5 6 9 10 L H Auto Reset On Master Reset Off Output Initially Low After Reset (Q) Single Transition Mode Auto Reset Disable Master Reset On Output Initially High After Reset (Q) Recycle Mode LOGIC DIAGRAM 3/10 HCF4541B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/10 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4541B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.1 -10 -8 -20 3.1 8 20 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 V V 1.5 3 4 -1.08 -4.1 -3.3 -8.4 1.08 3.3 8.4 ±1 µA V 3.5 7 11 -1.08 -3 -3.3 -8.4 1.08 3.3 8.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.55 -5 -4 -10 1.55 4 10 Max. Unit V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 5/10 HCF4541B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter Propagation Delay Time (28) tPHL tPLH (CLOCK to Q) Propagation Delay Time (216) tPHL tPLH (CLOCK to Q) tTHL tTLH Transition Time Transition Time Master Reset, Clock Pulse Width fCL tr, tf Maximum Clock Pulse Input Frequency Maximum Clock Pulse Input Rise or Fall Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. 900 300 225 Unit Typ. Max. 3.5 1.25 0.9 6 3.5 2.5 100 50 40 180 90 65 300 100 85 1.5 4 6 10.5 3.8 2.9 18 10 7.5 200 100 80 360 180 130 Unlimited µs µs ns ns ns MHz µs (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. DIGITAL TIMER APPLICATION A positive MASTER RESET pulse clears the counter and latch. The Output goes high and keeps up till the number of pulses, selected by A and B , are counted. This circuit is retriggerable and is as accurate as the input frequency. If a 6/10 more accurate circuit is desired, an external clock can be used on pin 3. A set-up time equal to the width of the one shot output is required immediately following initial power up, during which time the output will be high HCF4541B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) 7/10 HCF4541B Plastic DIP-14 MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 1.39 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 0.050 0.100 P001A 8/10 HCF4541B SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 8.55 E 5.8 8.75 0.336 6.2 0.228 0.344 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 ˚ (max.) PO13G 9/10 HCF4541B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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