HD74ACT161/HD74ACT163 Synchronous Presettable Binary Counter REJ03D0279–0200Z (Previous ADE-205-402 (Z)) Rev.2.00 Jul.16.2004 Description The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The HD74ACT161 have an asynchronous Master Reset input that overrides all other inputs and forces the outputs Low. The HD74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. Features • Synchronous Counting and Loading • High-Speed Synchronous Expansion • Typical Count Rate of 125 MHz • Outputs Source/Sink 24 mA • HD74ACT161 and HD74ACT163 have TTL-Compatible Inputs • Ordering Information: Ex. HD74ACT161 Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74ACT161FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74ACT161RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement *R 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 CEP 7 10 CET GND 8 9 PE (Top view) Rev.2.00, Jul.16.2004, page 1 of 8 HD74ACT161/HD74ACT163 Logic Symbol PE P0 P1 P2 P3 CEP CET TC CP *R Q0 Q1 Q2 Q3 * MR for HD74ACT161 SR for HD74ACT163 Pin Names CEP CET CP MR (HD74ACT161) SR (HD74ACT163) P0 to P3 PE Q0 to Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output Functional Description The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-toHigh transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (HD74ACT161), synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs – Master Reste (MR, HD74ACT161), Synchronous Reset (SR, HD74ACT163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) – determine the mode of operation, as shown in the Mode Select Table. A Low signal on MR overrides all other inputs and asynchronously forces all outputs Low. A Low signal on SR overrides counting and parallel loading and allows all outputs to go Low on the next rising edge of CP. A Low signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (HD74ACT161) or SR (HD74ACT163) High, CEP and CET permit counting when both are High. Conversely, a Low signal on either CEP or CET inhibits counting. The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is High when CET is High and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP•CET•PE TC = Q0•Q1•Q2•Q3•CET Rev.2.00, Jul.16.2004, page 2 of 8 HD74ACT161/HD74ACT163 Mode Select Table SR* SR 1 PE CET CEP L H X L X X X X Action on the Rising Clock Edge ( Reset (Clear) Load (Pn → Qn) H H H H H L H X Count (Increment) No change (Hold) H H X L No change (Hold) Note: ) 1. For HD74ACT163 H : High Voltage Level L : Low Voltage Level X : Immaterial State Diagram 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 Block Diagram P0 P1 P2 P3 PE ’161 ’163 CEP CET CP ’163 ONRY TC CP ’161 ONRY CP D CP D CD Q Q Q0 Q0 DETAIL A DETAIL A DETAIL A Q1 Q2 Q3 DETAIL A MR ’161 SR ’163 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Rev.2.00, Jul.16.2004, page 3 of 8 HD74ACT161/HD74ACT163 Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK –0.5 to 7 –20 V mA VI 20 –0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C VI = –0.5V Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 4.5V VCC = 5.5V DC Characteristics Item Symbol Ta = 25°°C VCC (V) min. Input voltage Output voltage typ. max. Ta = –40 to +85°°C min. max. Unit Condition VIH 4.5 5.5 2.0 2.0 1.5 1.5 — — 2.0 2.0 — — VIL 4.5 5.5 — — 1.5 1.5 0.8 0.8 — — 0.8 0.8 VOH 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 4.5 5.5 3.94 4.94 — — — — 3.80 4.80 — — VIN = VIL 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 VIN = VIL or VIH IOUT = 50 µA 4.5 5.5 — — — — 0.32 0.32 — — 0.37 0.37 VIN = VIL VOL V VOUT = 0.1 V or Vcc–0.1 V VOUT = 0.1 V or Vcc–0.1 V V VIN = VIL or VIH IOUT = –50 µA IOH = –24 mA IOH = –24 mA IOL = 24 mA IOL = 24 mA Input current ICC/input current IIN ICCT 5.5 5.5 — — — 0.6 ±0.1 — — — ±1.0 1.5 µA mA VIN = VCC or GND VIN = VCC–2.1 V Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. Rev.2.00, Jul.16.2004, page 4 of 8 HD74ACT161/HD74ACT163 AC Characteristics: HD74ACT161 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF fmax VCC (V)*1 Min 5.0 115 Typ 125 Max — 100 — MHz Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to Qn (PE Input HIGH or LOW) tPLH 5.0 1.0 5.5 9.5 1.0 10.5 ns tPLH 5.0 1.0 6.0 10.5 1.0 11.5 ns Propagation delay CP to TC Propagation delay CP to TC tPLH 5.0 1.0 7.0 11.0 1.0 12.5 ns tPHL 5.0 1.0 8.0 12.5 1.0 13.5 ns Propagation delay CET to TC Propagation delay CET to TC tPLH 5.0 1.0 5.5 8.5 1.0 10.0 ns tPHL 5.0 1.0 6.0 9.5 1.0 10.5 ns Propagation delay MR to Qn Propagation delay MR to TC tPHL 5.0 1.0 6.0 10.0 1.0 11.0 ns tPHL 5.0 1.0 8.0 13.5 1.0 14.5 ns Item Maximum count frequency Note: Symbol Min Max Unit 1. Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74ACT161 Ta = +25°C CL = 50 pF Item Set-up time, HIGH or LOW Pn to CP Symbol VCC (V)*1 Typ 5.0 4.0 tsu Hold time, HIGH or LOW Pn to CP Setup time, HIGH or LOW MR to CP th 5.0 tsu Hold time, HIGH or LOW MR to CP Setup time, HIGH or LOW PE to CP Hold time, HIGH or LOW PE to CP Setup time, HIGH or LOW CEP or CET to CP Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 9.5 11.5 ns –5.0 0 0 ns 5.0 4.0 8.5 9.5 ns th 5.0 –5.5 –0.5 –0.5 ns tsu 5.0 4.0 8.5 9.5 ns th 5.0 –5.5 –0.5 –0.5 ns tsu 5.0 2.5 5.5 6.5 ns Hold time, HIGH or LOW CEP or CET to CP Clock pulse width (Load) HIGH or LOW th 5.0 –3.0 0 0 ns tw 5.0 2.0 3.0 3.5 ns Clock pulse width (Count) HIGH or LOW MR pulse width, LOW tw 5.0 2.0 3.0 3.5 ns tw 5.0 3.0 3.0 7.5 ns Recovery time MR to CP trec 5.0 0 0 0.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 5 of 8 Unit HD74ACT161/HD74ACT163 Capacitance Item Symbol Input capacitance Power dissipation capacitance CIN CPD Typ Unit 4.5 45.0 pF pF Condition VCC = 5.5 V VCC = 5.0 V AC Characteristics: HD74ACT163 Ta = +25°C CL = 50 pF Item Maximum count frequency Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to TC Propagation delay CP to TC Propagation delay CET to TC Propagation delay CET to TC Note: Ta = –40°C to +85°C CL = 50 pF fmax VCC (V)*1 Min 5.0 120 Typ 128 Max — 105 — MHz tPLH 5.0 1.0 5.5 10.0 1.0 11.0 ns tPHL 5.0 1.0 6.0 11.0 1.0 12.0 ns tPLH 5.0 1.0 7.0 11.5 1.0 13.5 ns tPHL 5.0 1.0 8.0 13.5 1.0 15.0 ns tPLH 5.0 1.0 5.5 9.0 1.0 10.5 ns tPHL 5.0 1.0 6.0 10.0 1.0 11.0 ns Symbol Min Max Unit 1. Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74ACT163 Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Set-up time, HIGH or LOW 5.0 tsu Pn to CP Hold time, HIGH or LOW 5.0 th Pn to CP Setup time, HIGH or LOW 5.0 tsu SR to CP Hold time, HIGH or LOW 5.0 th SR to CP Setup time, HIGH or LOW 5.0 tsu PE to CP Hold time, HIGH or LOW 5.0 th PE to CP Setup time, HIGH or LOW tsu 5.0 CEP or CET to CP Hold time, HIGH or LOW 5.0 th CEP or CET to CP Clock pulse width (Load) tw 5.0 HIGH or LOW Clock pulse width (Count) 5.0 tw HIGH or LOW Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 6 of 8 Typ Ta = –40°C to +85°C CL = 50 pF 4.0 Guaranteed Minimum 10.0 12.0 ns Unit –5.0 0.5 0.5 ns 4.0 10.0 11.5 ns –5.5 –0.5 –0.5 ns 4.0 8.5 10.5 ns –5.5 –0.5 0 ns 2.5 5.5 6.5 ns –3.0 0 0.5 ns 2.0 3.5 3.5 ns 2.0 3.5 3.5 ns HD74ACT161/HD74ACT163 Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 7 of 8 Symbol CIN CPD Typ 4.5 45.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74ACT161/HD74ACT163 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 8 of 8 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Sales Strategic Planning Div. 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