INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4013B flip-flops Dual D-type flip-flop Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4013B flip-flops Dual D-type flip-flop DESCRIPTION FUNCTION TABLES The HEF4013B is a dual D-type flip-flop which features independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the D or CP inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. INPUTS OUTPUTS SD CD CP D O O H L X X H L L H X X L H H H X X H H INPUTS OUTPUTS D On + 1 On + 1 L L L H L H H L SD CD L L CP Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING Fig.1 Functional diagram. D data inputs CP clock input (L to H edge-triggered) SD asynchronous set-direct input (active HIGH) CD asynchronous clear-direct input (active HIGH) O true output O complement output HEF4013BP(N): 14-lead DIL; plastic (SOT27-1) HEF4013BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4013BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS Fig.2 Pinning diagram. January 1995 See Family Specifications 2 Philips Semiconductors Product specification HEF4013B flip-flops Fig.3 Logic diagram (one flip-flop). Dual D-type flip-flop January 1995 3 Philips Semiconductors Product specification HEF4013B flip-flops Dual D-type flip-flop AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 110 220 ns 83 ns + (0,55 ns/pF) CL 45 90 ns 34 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 95 190 ns 68 ns + (0,55 ns/pF) CL 40 80 ns 29 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 100 200 ns 73 ns + (0,55 ns/pF) CL 40 80 ns 29 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 75 150 ns 48 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 25 50 ns 17 ns + (0,16 ns/pF) CL 100 200 ns 73 ns + (0,55 ns/pF) CL 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL 5 60 120 ns 33 ns + (0,55 ns/pF) CL 30 60 ns 19 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL Propagation delays CP → O, O HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 SD → O HIGH to LOW 5 10 tPHL 15 SD → O LOW to HIGH 5 10 tPLH 15 CD → O HIGH to LOW CD → O LOW to HIGH 5 10 10 tPHL tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 January 1995 4 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF4013B flip-flops Dual D-type flip-flop AC CHARACTERISTI CS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Set-up time 5 D → CP 10 Hold time D → CP Minimum clock pulse width; LOW Minimum SD pulse width; HIGH Minimum CD pulse width; HIGH Recovery time for SD Recovery time for CD Maximum clock pulse frequency package (P) 40 20 MAX. ns 10 ns 15 5 ns 5 20 0 ns thold 20 0 ns 15 15 0 ns 5 60 30 ns 10 tWCPL 30 15 ns 15 20 10 ns 5 50 25 ns 24 12 ns 15 20 10 ns 5 50 25 ns 10 tWSDH 24 12 ns 15 20 10 ns 5 15 −5 ns 15 0 ns 10 10 tWCDH tRSD see also waveforms Figs 4 and 5 15 15 0 ns 5 40 25 ns 25 10 ns 15 25 10 ns 5 7 14 MHz 14 28 MHz 20 40 MHz 10 10 VDD V dissipation per TYP. 25 10 tsu MIN. 15 15 Dynamic power SYMBOL tRCD fmax TYPICAL FORMULA FOR P (µW) 5 850 fi + ∑ (foCL) × VDD 2 10 3 600 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) 15 9 000 fi + ∑ (foCL) × VDD fo = output freq. (MHz) 2 where CL = total load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification HEF4013B flip-flops Dual D-type flip-flop Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values. Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths. January 1995 6 Philips Semiconductors Product specification HEF4013B flip-flops Dual D-type flip-flop APPLICATION INFORMATION Some examples of applications for the HEF4013B are: • Counters/dividers • Registers • Toggle flip-flops Fig.6 Typical application of the HEF4013B in an n-stage shift register. Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2n. Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1). January 1995 7