INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4505B LSI 64-bit, 1-bit per word random access read/write memory Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 64-bit, 1-bit per word random access read/write memory HEF4505B LSI DESCRIPTION The HEF4505B is a 64-bit, 1-bit per word, fully decoded and completely static, random access memory. The memory is strobed for reading or writing only when the strobe input (ST), chip enable inputs (CE1 and CE2) are HIGH simultaneously. The output data is available at the data output (DOUT) only when the memory is strobed, the read/write input (R/W) is HIGH and after the read access time has passed. Note that the three-state output is initially disabled and always goes to the LOW state before data is valid. The output is disabled in the high-impedance OFF-state, when the memory is not strobed or R/W is LOW. R/W may remain HIGH during a read cycle or LOW during a write cycle. The output data has the same polarity as the input data. Fig.1 Pinning diagram. HEF4505BP(N): 14-lead DIL; plastic HEF4505BD(F): 14-lead DIL; ceramic (cerdip) (SOT27-1) (SOT73) ( ): Package Designator North America PINNING SUPPLY VOLTAGE A0 to A5 address inputs CE1, CE2 chip enable inputs R/W read/write input ST strobe input DIN data input DOUT data output 4,5 to 15 V 1. Minimum standby voltage for data retention is 3 V. FAMILY DATA, IDD LIMITS category LSI DOUT Z MODE disabled H L Z write L H Z disabled H H equal to memory data read Note 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) Z = high-impedance OFF-state January 1995 −0,5 to +15 See Family Specifications ST, CE1, CE2 R/W L OPERATING Note FUNCTION TABLE L RATING 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 64-bit, 1-bit per word random access read/write memory January 1995 3 Product specification HEF4505B LSI Fig.2 Functional diagram. Philips Semiconductors Product specification 64-bit, 1-bit per word random access read/write memory HEF4505B LSI AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Minimum strobe pulse width; LOW SYMBOL 5 10 tSTL 15 75 35 ns 45 22 ns 30 15 ns 5 Read cycle time Write cycle time Read access time 10 tRC Write recovery time 700 ns 250 500 ns 210 420 ns 5 220 440 ns 10 tWC 125 250 ns 15 75 150 ns 5 330 660 ns 303 ns + (0,55 ns/pF) CL 10 tACC 5 Read recovery time 350 15 15 Address recovery time TYPICAL EXTRAPOLATION FORMULA MIN. TYP. MAX. 135 270 ns 124 ns + (0,23 ns/pF) CL 100 200 ns 92 ns + (0,16 ns/pF) CL 80 40 ns 40 20 ns 15 25 10 ns 5 180 90 ns 120 60 ns 15 90 45 ns 5 75 35 ns 45 25 ns 40 20 ns 10 10 10 tAR tRR tWR 15 3-state propagation delays 5 Output disable times 10 15 Set-up times 5 An → ST 10 R/W → ST DIN → ST R/W → ST 105 210 ns 60 125 ns 55 115 ns −20 −40 ns −10 −20 ns 15 −5 −10 ns 5 −30 −60 ns tsuA −15 −30 ns 15 −5 −10 ns 5 160 80 ns 75 35 ns 10 10 tsuR tsuD 15 45 20 ns 5 240 120 ns 100 50 ns 75 35 ns 10 15 January 1995 tPHZ, tPLZ tsuW 4 Philips Semiconductors Product specification 64-bit, 1-bit per word random access read/write memory VDD V Hold time DIN → ST SYMBOL 5 10 15 tholdD HEF4505B LSI −20 −40 ns 5 −10 ns 10 0 ns (1) Output in high impedance OFF-state. (2) tSTHmin = tRCmax − tSTLmin. Fig.3 Read cycle timing diagram. January 1995 TYPICAL EXTRAPOLATION FORMULA MIN. TYP. MAX. 5 Philips Semiconductors Product specification 64-bit, 1-bit per word random access read/write memory HEF4505B LSI (1) tSTHmin = tWCmax − tSTLmin. Fig.4 Write cycle timing diagram. January 1995 6 Philips Semiconductors Product specification 64-bit, 1-bit per word random access read/write memory HEF4505B LSI APPLICATION INFORMATION Fig.5 256-word by n-bit static read/write memory using HEF4505B ICs. January 1995 7 Philips Semiconductors Product specification 64-bit, 1-bit per word random access read/write memory HEF4505B LSI Figure 5 shows a 256-word by n-bit static RAM system. The outputs of the four HEF4505B circuits are tied together to form 256 words by 1-bit. Additional bits are attained by paralleling the inputs in groups of four. Memories of larger words can be attained by decoding the most significant bits of the address and AND-ing them with the strobe input. The memory system shown in Fig.5 can be interfaced directly with other ICs of the LOCMOS HE family. No external components are required. Non-volatile information storage is allowed due to very low power dissipation when the memory is powered by a small standby battery. Figure 6 shows an optional standby power supply circuit for making a LOCMOS memory ‘non-volatile’. When the usual power fails, a battery is used to sustain operation or maintain stored information. While normal power supply voltage is present, the battery is trickle-charged through a resistor (R) which sets the charging rate. In Fig.6 the sustaining voltage is VB, and + V is the ordinary voltage from a power supply. VDD is connected to the power supply pin of the memory. Low-leakage diodes are recommended to conserve battery power. Fan-in and fan-out of the memory are limited only by speed requirements. The extremely low input and output leakage currents keep the output voltage levels from changing significantly as more outputs are tied together. With the output levels independent of fan-out, most of the power supply range is available as logic swing, regardless of the number of units wired together. As a result, high noise immunity is maintained under all conditions. Fig.6 Standby battery circuit. January 1995 8