INTEGRATED CIRCUITS DATA SHEET SAA4978H Picture Improved Combined Network (PICNIC) Product specification Supersedes data of 1998 Oct 07 File under Integrated Circuits, IC02 1999 May 03 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 Analog input blocks Gain elements for automatic gain control (9 dB range) Clamp circuit, clamping Y to digital level 32 and UV to 0 (2’s complement) Analog anti-aliasing prefilter 9-bit analog-to-digital conversion Digital processing blocks Overflow detection Y delay Transient noise suppression Non-linear phase filter after ADC 4 MHz notch Digital clamp correction for UV 4 : 4 : 4 downsampled to 4 : 2 : 2 or 4 : 1 : 1 Bus A format: interface formatting, timed with enabling signal (see Table 1 and Fig.9) Bus B format (see Table 1 and Fig.9) Time base correction and sample rate conversion Noise reduction Histogram Subtitle detection Black bar detection Bus C format (see Table 1) Bus D reformatter: the various input formats are all converted to the internal 9 bits 4 : 2 : 2 (see Table 1) Peaking Non-linear phase filter before DAC DCTI Border blank Analog output blocks Triple 10-bit digital-to-analog conversion Analog anti-aliasing post-filter PLL SNERT PSP Microcontroller Board level testability Power-on reset 7.1.2 7.1.3 7.1.4 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 1999 May 03 2 SAA4978H 8 CONTROL REGISTER DESCRIPTION 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 12 APPLICATION 13 PACKAGE OUTLINE 14 SOLDERING 14.1 14.2 14.3 14.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 17 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) 1 SAA4978H FEATURES • Clamp • Analog AGC • Triple YUV 9-bit Analog-to-Digital Converter (ADC) • Triple bypassable analog anti-alias filter • 4 MHz notch filter • 2D-peaking and coring • Non-linear phase filter after ADC • Non-linear phase filter before DAC • 4 : 1 : 1 or 4 : 2 : 2 digital processing • Coaxial Transceiver Interface (CTI) • 4 : 1 : 1 or 4 : 2 : 2 selectable I/O interface • Triple 10-bit Digital-to-Analog Converter (DAC) • Asynchronous digital input • Triple bypassable analog reconstruction filter • Time base correction • Embedded microcontroller (80C51 core) • Histogram analysis • Programmable signal positioner • Histogram modification • SNERT interface • Subtitle detection • I2C-bus user control interface • Black bar detection • Boundary Scan Test (BST). • Line memory based noise reduction (spatial) • Noise level measurement 2 • Clamp noise reduction The SAA4978H is a monolithic integrated circuit suitable either for 1fH or 2fH applications that contain a large variety of picture improvement functions. It combines analog-to-digital and digital-to-analog conversion for YUV signals, digital processing, line-locked clock regeneration and an 80C51 microcontroller core in one IC. • Dynamic peaking • Energy measurement • Multi Picture-In-Picture (multi PIP) decimation • Differential Pulse Code Modulation (DPCM) data decompression for colour 3 GENERAL DESCRIPTION QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage VDDD digital supply voltage 3.0 3.3 3.6 V IDDA analog supply current VDDA = 3.45 V − 145 180 mA IDDD digital supply current VDDD = 3.6 V − 210 270 mA fclk clock frequency − 16 − MHz S/N signal-to-noise ratio 50 − − dB 4 3.15 default settings 3.3 3.45 V ORDERING INFORMATION TYPE NUMBER SAA4978H 1999 May 03 PACKAGE NAME QFP160 DESCRIPTION plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 × 28 × 3.4 mm; high stand-off height 3 VERSION SOT322-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 62 Ref L YB0 to YB8 WEB CLKAS 43 to 51 84 to 76 75 to 67 66 85 3-STATE various bias controls BAND GAP REFERENCES 21 53 to 61 UVB0 to UVB8 SYNCHRONIZE Ref H DITHER YIN 23 Y DELAY CLAMP UIN VIN TRIPLE AGC 9-BIT TRIPLE ANALOG PREFILTER MAJORITY FOLLOWER FILTER NON-LINEAR PHASE FILTER 4 MHz NOTCH 5 ADC TRIPLE 9-BIT DITHER TIME BASE CORRECTION/ SAMPLE RATE CONVERTER MUX REFORMATTER 25 5 UV CLAMP CORRECTION 26 FORMATTER DOWNSAMPLER 4 VDDA1 to VDDA4 11, 22, 24, 31 VSSA1 to VSSA4 13, 16, 27, 32 10 11 bus A SAA4978H RED MUX BORDER CLP WEC IEC bus B SKEWEN SKEW HA BLANKING WEA B UPSAMPLER DOWNSAMPLER DITHER OVERFLOW DETECTOR CLP A MUX C PIXREP HREF BST/TEST Philips Semiconductors DIFFIN 64, 90, 134, 139 UVA0 to UVA8 Picture Improved Combined Network (PICNIC) BGEXT 17 64, 87, 100, 135 YA0 to YA8 WEA BLOCK DIAGRAM VSSD1 to VSSD4 5 ok, full pagewidth 1999 May 03 VDDD1 to VDDD4 D PSP E F G 36 37 38 39 40 41 18 19 29 30 158 157 10 MHB172 TEST TRST TMS TDI TDO TCK HDFL VDFL VA HREFEXT INT1 INT0 FBL Product specification Fig.1 Block diagram (continued in Fig.2). SAA4978H Standard bus width in data path is 9 bits; exceptions are marked. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SUBTITLE DETECTION NOISE ESTIMATION BLACK BAR DETECTION 112 114 to 122 124 to 132 91 to 99 RED 101 to 109 110 3-STATE SPECTRAL MEASUREMENT UNDITHER DITHER DYNAMIC 10 PEAKING MUX A DOWNSAMPLER DITHER MUX UPSAMPLER DITHER YOUT DPCM CODER 4 TRIPLE ANALOG POST-FILTER 10 4 8 DAC TRIPLE 10-BIT BORDER BLANK REFORMATTER FORMATTER HISTOGRAM MODIFICATION 12 5 5 NOISE REDUCTION NON-LINEAR 10 PHASE FILTER 14 MUX DCTI DPCM DECODER 10 15 B bus C bus D PIXREP BLANKING UOUT VOUT Philips Semiconductors 113 SPECTRAL MEASUREMENT YD0 to YD8 UVD0 to UVD8 Picture Improved Combined Network (PICNIC) book, full pagewidth 1999 May 03 UVC8 to UVC0 YC8 to WEC IEC YC0 5 BORDER SPECIAL FUNCTION REGISTERS VARIOUS REGISTERS AUXILIARY RAM PROGRAM ROM SAA4978H SKEWEN C CL16 D CL16 CL16 WATCHDOG FREQUENCY GUARD HREF CL16 SKEW CL32 DATA8 P1.1 INT1 INT0 P1.4 bone 80C51 MICROCONTROLLER CORE EA PSEN P1.5 P3.5 P3.4 P1.2 P1.3 P1.7 P1.6 RST PLL E F CRYSTAL OSCILLATOR OR G 1 2 140 149 to to 147 156 136 137 138 160 159 8 9 5 4 6 7 42, 63, 86, 111, 133, 3 52, 123, 148 88 89 28 34 35 OSCI OSCO MHB173 SNDA SNCL T0 WDRST VSSO1 to VSSO6 VDDO1 to VDDO3 Standard bus width in data path is 9 bits; exceptions are marked. Fig.2 Block diagram (continued from Fig.1). CLK16 CLK32 HA Product specification RSTR SCL RST RSTW SDA SAA4978H P2.7 P0.7 EA ALE to to T1 PSEN P2.0 P0.0 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) 6 SAA4978H PINNING INFORMATION SYMBOL PIN DESCRIPTION SNDA 1 SNERT data input/output SNCL 2 SNERT clock output VSSO6 3 digital microcontroller I/O ground 6; internally connected to all other VSSO pins SCL 4 I2C-bus serial clock input (P1.6) SDA 5 I2C-bus serial data input/output (P1.7) RST 6 microcontroller reset input WDRST 7 watchdog reset output RSTW 8 reset write signal output/SNERT reset (only PALplus) Port 1.2 RSTR 9 reset read signal output/SNERT reset (SAA4991WP or SAA4992H) Port 1.3 FBL 10 fast blanking input to PSP and Port 1.4 VDDA1 11 analog back-end supply voltage 1 YOUT 12 Y analog output VSSA1 13 analog back-end ground 1 UOUT 14 U analog output VOUT 15 V analog output VSSA2 16 analog input ground 2; internally connected to substrate BGEXT 17 band gap external/reference currents input HDFL 18 horizontal synchronization signal output, deflection part VDFL 19 vertical synchronization signal output, deflection part AGND 20 analog ground DIFFIN 21 differential Y input VDDA2 22 analog input supply voltage 2 YIN 23 Y analog input VDDA3 24 analog input supply voltage 3 UIN 25 U analog input VIN 26 V analog input VSSA3 27 analog input ground 3; internally connected to substrate HA 28 horizontal synchronization input, acquisition part VA 29 vertical synchronization input, acquisition part HREFEXT 30 horizontal reference external output VDDA4 31 analog PLL supply voltage 4 VSSA4 32 analog PLL ground 4; internally connected to substrate VSSX 33 oscillator ground OSCI 34 oscillator input OSCO 35 oscillator output TEST 36 test input/external 32 MHz clock input TRST 37 BST reset input TMS 38 BST test mode select input TDI 39 BST test data input TDO 40 BST test data output 1999 May 03 6 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL SAA4978H PIN DESCRIPTION TCK 41 BST test clock input VSSO1 42 digital bus A/B ground 1; internally connected to all other VSSO pins UVA0 43 bus A output UVL UVA1 44 bus A output UV0 UVA2 45 bus A output UV1 UVA3 46 bus A output UV2 UVA4 47 bus A output UV3 UVA5 48 bus A output UV4 UVA6 49 bus A output UV5 UVA7 50 bus A output UV6 UVA8 51 bus A output UV7 VDDO1 52 digital I/O bus A/B supply voltage 1; internally connected to all other VDDO pins YA0 53 bus A output YL YA1 54 bus A output Y0 YA2 55 bus A output Y1 YA3 56 bus A output Y2 YA4 57 bus A output Y3 YA5 58 bus A output Y4 YA6 59 bus A output Y5 YA7 60 bus A output Y6 YA8 61 bus A output Y7 WEA 62 write enable bus A output VSSO2 63 digital bus A/B ground 2; internally connected to all other VSSO pins VDDD1 64 digital core supply voltage 1; internally connected to all other VDDD pins VSSD1 65 digital core ground 1; internally connected to all other VSSD pins WEB 66 write enable bus B input YB8 67 bus B input Y7 YB7 68 bus B input Y6 YB6 69 bus B input Y5 YB5 70 bus B input Y4 YB4 71 bus B input Y3 YB3 72 bus B input Y2 YB2 73 bus B input Y1 YB1 74 bus B input Y0 YB0 75 bus B input YL UVB8 76 bus B input UV7 UVB7 77 bus B input UV6 UVB6 78 bus B input UV5 UVB5 79 bus B input UV4 UVB4 80 bus B input UV3 UVB3 81 bus B input UV2 1999 May 03 7 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL SAA4978H PIN DESCRIPTION UVB2 82 bus B input UV1 UVB1 83 bus B input UV0 UVB0 84 bus B input UVL CLKAS 85 asynchronous clock input VSSO3 86 digital I/O bus B/clock ground 3; internally connected to all other VSSO pins VDDD2 87 digital core supply voltage 2; internally connected to all other VDDD pins CLK16 88 16 MHz clock output CLK32 89 32 MHz clock output VSSD2 90 digital core ground 2; internally connected to all other VSSD pins UVD0 91 bus D input UVL UVD1 92 bus D input UV0 UVD2 93 bus D input UV1 UVD3 94 bus D input UV2 UVD4 95 bus D input UV3 UVD5 96 bus D input UV4 UVD6 97 bus D input UV5 UVD7 98 bus D input UV6 UVD8 99 bus D input UV7 VDDD3 100 digital core supply voltage 3; internally connected to all other VDDD pins YD0 101 bus D input YL YD1 102 bus D input Y0 YD2 103 bus D input Y1 YD3 104 bus D input Y2 YD4 105 bus D input Y3 YD5 106 bus D input Y4 YD6 107 bus D input Y5 YD7 108 bus D input Y6 YD8 109 bus D input Y7 RED 110 read enable bus D output VSSO4 111 digital I/O bus C/D ground 4; internally connected to all other VSSO pins IEC 112 input enable bus C output WEC 113 write enable bus C output YC8 114 bus C output Y7 YC7 115 bus C output Y6 YC6 116 bus C output Y5 YC5 117 bus C output Y4 YC4 118 bus C output Y3 YC3 119 bus C output Y2 YC2 120 bus C output Y1 YC1 121 bus C output Y0 YC0 122 bus C output YL 1999 May 03 8 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL SAA4978H PIN DESCRIPTION VDDO2 123 digital I/O supply voltage 2 to bus C/D; internally connected to all other VDDO pins UVC8 124 bus C output UV7 UVC7 125 bus C output UV6 UVC6 126 bus C output UV5 UVC5 127 bus C output UV4 UVC4 128 bus C output UV3 UVC3 129 bus C output UV2 UVC2 130 bus C output UV1 UVC1 131 bus C output UV0 UVC0 132 bus C output UVL VSSO5 133 digital I/O ground 5 to bus D and microcontroller; internally connected to all other VSSO pins VSSD3 134 digital core ground 3; internally connected to all other VSSD pins VDDD4 135 digital core supply voltage 4; internally connected to all other VDDD pins EA 136 external access output (active LOW) PSEN 137 program store enable output (active LOW) ALE 138 address latch enable output VSSD4 139 digital core ground 4; internally connected to all other VSSD pins P2.7 140 Port 2 data input/output signal 7 P2.6 141 Port 2 data input/output signal 6 P2.5 142 Port 2 data input/output signal 5 P2.4 143 Port 2 data input/output signal 4 P2.3 144 Port 2 data input/output signal 3 P2.2 145 Port 2 data input/output signal 2 P2.1 146 Port 2 data input/output signal 1 P2.0 147 Port 2 data input/output signal 0 VDDO3 148 microcontroller I/O pad supply voltage 3 P0.7 149 Port 0 data input/output signal 7 P0.6 150 Port 0 data input/output signal 6 P0.5 151 Port 0 data input/output signal 5 P0.4 152 Port 0 data input/output signal 4 P0.3 153 Port 0 data input/output signal 3 P0.2 154 Port 0 data input/output signal 2 P0.1 155 Port 0 data input/output signal 1 P0.0 156 Port 0 data input/output signal 0 INT0 157 interrupt 0, I/O Port 3.2 (active LOW) INT1 158 interrupt 1, I/O Port 3.3 (active LOW) T0 159 timer 0 I/O Port 3.4 T1 160 timer 1 I/O Port 3.5 1999 May 03 9 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) handbook, halfpage 121 160 SAA4978H 120 1 SAA4978H 80 81 41 40 MHB174 Fig.3 Pin configuration. 7 According to this specification, a lift of 6 dB up to a drop of 3 dB may be necessary with respect to the nominal values. The gain setting within the required minimum 9 dB range is performed digitally via the internal microcontroller. For this purpose a gain setting digital-to-analog converter is incorporated. The smallest step in the gain setting should be hardly visible on the picture, this can be met with smaller steps of 0.4%/step. FUNCTIONAL DESCRIPTION The SAA4978H consists of the following main functional blocks: • Analog preprocessing and analog-to-digital conversion • Digital processing at 1fH level • Digital processing at 2fH level • Digital-to-analog conversion Luminance and chrominance gain settings can be separately controlled. The reason for this split is that U and V may have already been gain adjusted by an Automatic Chrominance Control (ACC), whereas luminance is to be adjusted by the SAA4978H AGC. However, for RGB originated sources, Y, U and V should be adjusted with the same AGC gain. • Line-locked clock generation • Crystal oscillator • Control interfacing I2C-bus and SNERT • Register I/O • Programmable Signal Positioner (PSP) • 80C51 microcontroller core • Board level testability provisions. 7.1.2 7.1 A clamp circuit is applied to each input channel, to map the colourless black level in each video line (on the sync back porch) to level 32 at 9 bits for Y and to the centre level of the converters for U and V. During the clamp period, an internally generated clamp pulse is used to switch-on the clamp action. 7.1.1 Analog input blocks GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL (9 dB RANGE) A variable amplifier is used to map the possible YUV input range to the analog-to-digital converter range e.g. as defined for SCART signals. 1999 May 03 10 CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 32 AND UV TO 0 (TWOS COMPLEMENT) Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H A voltage controlled current source construction, which references to voltage reference points in the ladders of the analog-to-digital converters, provides a current on the input of the YUV signals in order to bring the signals to the correct DC value. This current is proportional to the DC error, but is limited to ±150 µA. It is essential that the clamp current becomes zero with a zero error and that the asymmetry between positive and negative clamp currents is limited to within 10%. When the clamping action is off, the residual clamp current should be very low, so that the clamp level will not drift away within a video line. The clamp level in the Y channel has a minimum value of 600 mV to ensure undisturbed clamping for maximum Y input signals with top sync levels up to 600 mV. In order to improve common mode rejection it is recommended to connect the same source impedance as used in the YIN input at the DIFFIN input to ground. 7.1.3 7.2.2 The Y samples can be shifted onto 4 positions with respect to the UV samples. This shift is meant to account for a possible difference in delay prior to the SAA4978H, e.g. from a prefilter in front of an analog-to-digital converter. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. One setting provides one sampleless delay in Y, the other two settings provide more delay in the Y path. 7.2.3 ANALOG ANTI-ALIASING PREFILTER 7.2.4 7.2.1 9-BIT ANALOG-TO-DIGITAL CONVERSION 7.2.5 4 MHZ NOTCH The 4 MHz notch provides a zero on 1⁄4 of the sample frequency. With fs = 16 MHz the notch is thus at 4 MHz. The 3 dB notch width is 2 MHz. The filter coefficients are 1⁄ × [−1; 0; 5; 0; 5; 0; −1]. This filter gives a relative gain of 8 0.75 dB at 1.7 and 6.3 MHz. Digital processing blocks The notch can be bypassed without changing the group delay. OVERFLOW DETECTION A histogram of the three overflow levels is made every field and can be read in a 2-byte accuracy. An input selector defines which ADC is monitored. 7.2.6 DIGITAL CLAMP CORRECTION FOR UV During 32 samples within the active clamping the clamp error is measured and accumulated to determine a low-pass filtered value of the clamp error. A vertical recursive filter is then used to further reduce this error value. This value can be read by the microcontroller or be used directly to correct the clamp error. It is also possible for the microcontroller to give a fixed correction value. In the event of U or V selection the underflow information is also added to the first histogram level, in this way the data can be handled as out-of-range information. The histogram content provides information for the AGC to make an accurate estimate of the decrease in gain, in the event of overflow for luminance or out-of-range detection for U and V. 1999 May 03 NON-LINEAR PHASE FILTER AFTER ADC The non-linear phase filter adjusts for possible group delay differences in the luminance channel. The filter coefficients are [−L × (1 − u); 1 + L; −L × u]; where L determines the strength of the filter and u determines the asymmetry. The effect of the asymmetry is that for higher frequencies the delay is decreased for u ≤ 0.5. Settings are provided for L = 0, 1⁄16, 2⁄16 and 3⁄16 and u = 0, 1⁄4 and 1⁄2. Three identical multi-step type analog-to-digital converters are used to convert the Y, U and V inputs with a 16 MHz data rate. The ADCs have a 2-bit overflow detection, and an underflow detection for U and V, to be used for AGC control. The 2 bits are coded for one in-range level and three overflow levels; 1 dB, 1 to 2 dB and 2 to 3 dB. 7.2 TRANSIENT NOISE SUPPRESSION A circuit is added in the luminance channel to suppress the typical multi-step trip level noise. This majority follower filter compares the neighbouring pixels to a +1 or −1 LSB difference. If the majority of these differences is +1 then 1 is added to the actual pixel. If the majority of these differences is −1 then 1 is subtracted from the actual pixel. The number of pixels included in the filter is selectable; 1 (bypass), 3, 5, 7 or 9. A 3rd-order linear phase filter is applied to each of the Y, U and V channels. It provides a notch on fclk (16 MHz at Y, U and V) to strongly prevent aliasing to low frequencies, which would be the most disturbing. The bandwidth of the filters is designed for −3 dB at 5.6 MHz. The filters can be bypassed if external filtering with other characteristics is desired. In the bypass mode the gain accuracy of the front-end part is 4% instead of 8% for the filter-on mode. 7.1.4 Y DELAY 11 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) 7.2.7 SAA4978H It is possible, in bus B reformatter, to invert the UV data so that the SAA4978H can handle any polarity convention of the UV data. 4 : 4 : 4 DOWNSAMPLED TO 4 : 2 : 2 OR 4 : 1 : 1 4 : 4 : 4 data is downsampled to 4 : 2 : 2, by first filtering with a [1; 0; −7; 0; 38; 64; 38; 0; −7; 0; 1] filter, before being subsampled by a factor of 2. The U and V samples from the 4 : 2 : 2 data are filtered again by a [−1; 0; 9; 16; 9; 0; −1] filter, before being subsampled a second time by a factor of 2. Bypassing this function keeps the data in the 4 : 2 : 2 format. 7.2.8 In the event of an asynchronous input the clock has to be provided externally to pin CLKAS. When applying an external PALplus decoder with 30 ms processing delay, the vertical field start can be set via software in a PSP register. For “CCIR 656” standard data format input, inversion of the MSB of the (synchronized) bus B UV input can be selected. Synchronization signals included in this format will be ignored. BUS A FORMAT: INTERFACE FORMATTING, TIMED WITH ENABLING SIGNAL (see Table 1 and Fig.9) The chosen 4 : 1 : 1 or 4 : 2 : 2 formatted output data is presented to bus A (YUV_A bus), consistent with the WEA data enable signal. After the rising edge of WEA the first, respectively second, data word contains the first phase of the 4 : 1 : 1 or 4 : 2 : 2 format, depending on the qualifier respectively prequalifier mode of WEA. If the data has to be formatted to 8 bits, a choice can be made between rounding and dithered rounding. Dithered rounding may be applied in the sense that every odd output sample has had an addition of 0.25 LSB (relative to 8 bits) before truncation and every even output sample has had an addition of 0.75 LSB before truncation. In this way, on average, correct rounding is realized (no DC shift). Especially for low frequency signals, the resolution is increased by a factor of 2 by the high frequency modulation. The phase of dithering can be switched 180° from line-to-line, field-to-field or frame-to-frame, in order to decrease the visibility of the dithering pattern. 7.2.10 CONVERSION The Time Base Correction (TBC) and Sample Rate Conversion (SRC) block provides a dynamically controlled delay with an accuracy of up to 1⁄64 of a pixel and a range of −0.5 to +0.5 lines (plus processing delay). The time base correction block has an input for skew data. This skew data can be the phase error measured by a HPLL, which is located in the PLL block of the SAA4978H. The skew is used as a shift of the complete active video part of a line. Added with a static (user controlled) shift, up to 1⁄2 video line (32 µs) can be shifted in both directions, related to a nominal 1⁄2 line delay. For sample rate conversion, the delay is also varied along the line with the subpixel accuracy. With a zero-order variation of the delay, a linear compress or expand function can be obtained. The range for the compression factor is 0 to 2, meaning infinite zoom up to a compression with a factor of 2. With a 2nd-order variation of the delay added to the control, the compression factor can be modulated with a parabolic shape, thus giving a panoramic view option to display e.g. 4 : 3 video on a 16 : 9 screen or vice versa. The not connected output pins of bus A, including WEA (depending on the application), can be set to 3-state to allow short-circuiting of these pins at board production. Short-circuiting at not connected outputs can not be tested by Boundary Scan Test (BST). For outputs in 3-state mode it is not allowed to apply voltages higher than VDDO + 0.3 V. 7.2.9 The static shift may also be used to make the delay of the SAA4978H plus periphery equal to an integer number of lines. This is useful for 1fH applications, in which the horizontal sync signal is not delayed with the video data. This will then make the function of time base correction obsolete for 1fH applications. BUS B FORMAT (see Table 1 and Fig.9) Bus B can accommodate the following formats; 4 : 1 : 1 serial, 4 : 2 : 2 parallel, 4 : 2 : 2 double clock UYVY, all synchronous and asynchronous. All external formats are selectable with prequalifier or qualifier WEB. All of the various input formats are converted to the internal 9 bits 4 : 2 : 2. For the 8-bit inputs, the LSB of the input bus should be connected externally to a fixed logic level. In the event of a 4 : 1 : 1 input, the U and V channels are reformatted and upsampled by generating the extra samples with a 1⁄16 × [−1; 9; 9; −1] filter. The other U and V samples remain equal to the original 4 : 1 : 1 sample values. 1999 May 03 TIME BASE CORRECTION AND SAMPLE RATE Another main task for the sample rate converter is to resynchronize external data at a non-system clock sample rate, for instance, MPEG decoder signals at 13.5 MHz. A requirement for these signals is that they are line and frame locked to the SAA4978H. 12 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) 7.2.11 SAA4978H The histogram acquisition uses 32 baskets on the grey scale from (ultra) black to (ultra) white. Pixels that are found around the centre of a basket increase a counter for that basket with the value 8, pixels that come around the edge between two baskets increase the counters in both baskets, such as 3 in the left one and 5 in the right one. By this method, the quantization distortion is overcome from having a discrete set of baskets. NOISE REDUCTION The noise reduction part consists of clamp noise reduction and spatial noise reduction for low frequency noise. Within this ensemble a two dimensional band split is used, enabling also the functions of 2D low passing, adding the multi Picture-In-Picture (multi PIP) function and 2D peaking. The clamp noise reduction is realized with an adaptive temporal recursive filter. This filter will correct the DC level of each line when it is varying from field-to-field in the segments with the least likely movement. This clamp noise filtering is intended to correct for clamp errors in a complete chain, which cannot be removed with traditional clamping on the back porch of the video. Clamp noise is only reduced for luminance. Between acquisition of the histogram and correction of the transfer curves, the microcontroller included in the SAA4978H processes the counter values from the 32 baskets. The outcome of the microcontrollers algorithm defines a differential transfer curve for the luminance. This means that only differences from a 1 : 1 transfer curve are coded. This is done in 32 LUT points, with a linear interpolation for all input values in between the LUT points. The spatial noise reduction is targeted for reduction of the mid frequency noise spectrum, where adaptive filtering combines pixels around the centre pixel and pixels from the lines above in a recursive way. This spatial noise reduction is only realized for luminance. When changes are made to the luminance level of pixels, the saturation has to be restored by using the same relative gain for the U and V channels. The histogram data also provides the information of the minimum and maximum levels of Y, U and V, by which the microcontroller can affect an AGC gain before the video analog-to-digital conversion. The 2D low-pass filter is a [1; 2; 1] filter in both the horizontal and vertical direction. 2D high-pass is realized by taking the centre tap and subtracting the 2D low-pass output from it. Also added in the 2D high-pass is the vertical low-passed data, which is subtracted from the centre tap and multiplied by a user selectable gain (0 to 7⁄8). The 2D high-pass data is multiplied by a user selectable gain of 0 and 2⁄4 to 8⁄4 and cored before adding it to the 2D low-pass branch for the 2D peaking function. The HF signal bypasses both the LF temporal and the spatial noise reduction, therefore sharpness in the high frequencies is not reduced by the noise reduction parts. The factor 0 on the HF signal yields a pure 2D low-passed signal at the output. Multi PIP with pure subsampling of this signal yields a much better result than without the low-pass operation. 7.2.12 Another main part of the histogram is the display-bars block. This block can insert up to 32 horizontal bars in the YUV data path. Size, spacing, luminance, colour and length are fully programmable. This can be used to construct a visual display of the histogram or transfer curve. 7.2.13 Subtitle detection searches in a large area of the video field for patterns that are characteristic for subtitles. The expectation is to encounter in a video line a considerable number of crossings through both a dark grey and a light grey threshold and in its vicinity also crossings in the other direction. This part is realized with valid crossing (event) counting on each line in the target area. This event value is stored for 128 lines in the subtitle RAM, which is located at the top of the auxiliary RAM. The subtitle logic has higher priority to access the subtitle RAM than the microcontroller. HISTOGRAM Histogram modification consists of acquiring the histogram of the luminance levels and correcting the luminance transfer curve in order to provide more perceptual contrast in the picture. The internal microcontroller can filter out this data. In a number of adjacent lines, there must be a similar high count value for the number of events. If this condition holds then the detection of subtitles on that vertical position is more definite. For economy, a subsampling is realized on the video with a factor of 4 before the histogram is produced. From line-to-line, a two pixel offset is used on the subsample pattern. 1999 May 03 SUBTITLE DETECTION 13 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H This information can be used in combination with other information on how to display the video source on the screen. Such decisions are made entirely by the internal microcontroller. 7.2.14 7.2.16 FORMATS ARE ALL CONVERTED TO THE INTERNAL 9 BITS 4 : 2 : 2 (see Table 1) Bus D can handle 4 : 1 : 1 external 8 or 9 bits, 4 : 2 : 2 external 8 or 9 bits, 4 : 2 : 2 internal 9 bits and DPCM 4 : 2 : 2. BLACK BAR DETECTION Black bar detection searches in the upper and in the lower part of the screen to respectively the last black line and the first black line. To avoid disturbances of Logos in the video, measurements can be performed in only the horizontal centre part of the lines. 7.2.15 Bus D is selectable in 1fH and 2fH mode. In 1fH mode the internal input can also be used. For dithered 8-bit luminance signals an undither block is provided that restores the 9th bit for low frequency and low noise. This is needed before the peaking circuit to prevent amplification of the 1⁄2fs dither modulation. BUS C FORMAT (see Table 1) The U and V samples from the 4 : 2 : 2 data are filtered again by a [−1; 0; 9; 16; 9; 0; −1] filter, before being subsampled by a factor of 2. Bypassing this function keeps the data in the 4 : 2 : 2 format. In the event of 8-bit inputs, the LSB of the input bus should be externally connected to a fixed logic level. In the event of a 4 : 1 : 1 input, the U and V channels are reformatted and upsampled by generating the extra samples with a 1⁄16 × [−1; 9; 9; −1] filter. The other U and V samples remain equal to the original 4 : 1 : 1 sample values. Should it be required to format the data to 8 bits, a choice can be made between rounding and dithered rounding. Dithered rounding may be applied in the sense that every odd output sample has had an addition of 0.25 LSB (relative to 8 bits) before truncation and every even output sample has had an addition of 0.75 LSB before truncation. In this way, normally, correct rounding is realized (no DC shift). Especially for low frequency signals, the resolution is increased by a factor of 2 by the high frequency modulation. The phase of dithering is switched 180° from line-to-line, field-to-field or frame-to-frame in order to decrease the visibility of the dithering pattern. 7.2.17 PEAKING Peaking in the SAA4978H can be used in two ways: 1. The first way is to give the luminance a linear boost of the higher frequency ranges, which makes no distinction between small and large details or edges. 2. The second way is to use the peaking dynamically, in order to boost smaller details and provide less gain on large details and edges. The effect is detail enhancement without the creation of unnaturally large overshoots and undershoots on large details and edges. This block also performs the subsampling for multi PIP, with subsampling factors of 1, 2, 3 and 4. Another output format at bus C is Differential Pulse Code Modulation (DPCM) 4 : 2 : 2. This data compression method is applied on the U and V channels, and gives a 50% data reduction. In this way it is possible to convert a 4 : 2 : 2 picture to 2fH using a single 12-bit wide field memory. This format is especially useful for graphics conversion with high amplitude and high saturation input signals. The not connected output pins of bus C including WEC and IEC (depending on the application) can be set to 3-state to allow short-circuiting of these pins at board production. Short-circuiting at not connected outputs can not be tested by BST. For outputs in 3-state mode it is not allowed to apply voltages higher than VDDO + 0.3 V. 1999 May 03 BUS D REFORMATTER: THE VARIOUS INPUT Basically, the three peaking filters (1 high-pass and 2 band-pass) filter the incoming luminance signal. The high-pass filter is made with [−1; 2; −1] coefficients, giving a maximum throughput at 1⁄2fs (equals 8 MHz). The first band-pass filter has [−1; 0; 2; 0; −1] coefficients, giving a maximum throughput at 1⁄4fs (equals 4 MHz). The second band-pass filter has a cascade of [−1; 0; 0; 2; 0; 0; −1] and [1; 2; 1] coefficients, giving a maximum throughput at 2.38 MHz. With a separate gain control on each of the peaking filters [possible gain settings of (0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16 and 8⁄16)], a desired frequency characteristic can be obtained with steps of maximum 2 dB gain difference at the centre frequencies. 14 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H The sum of the filter outputs is fed through a coring circuit with a user definable transfer curve between −7 and +7 LSB at a 12-bit level. The definition of the coring LUT is realized with two control registers. Herein, for each of the points in the transfer curve, the user can define an output between 0 and the input value. For the LUT points +7 (and −7), a choice can be made from (−4) +4 to (−7) +7. By setting control bit CORING to LOW, the coring transfer curve is switched to a coarse coring which is only dependent on the threshold (see Fig.13). 7.2.19 The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, making absolute and again differentiating the U and V signals separately. This signal is used as a pointer to make a time modulation. This results in a 4 : 4 : 4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called ‘over the hill protection’ prevents peak signals from becoming distorted. It is possible to control gain, width, connect U and V and over the hill range via the microcontroller. The so formed peaking signal can be added to the original luminance signal, the sum of which then becomes the 9-bit output signal (black-to-white), with an additional DA shift fitting within 10 bits. At the output of the DCTI a post-filter is situated to make a correction for the simple upsampling in DCTI which is a linear interpolation [1; 2; 1]. The post-filter coefficients are [−1; 2; 6; 2; −1], convolution of both filters gives [−1; 0; 9; 16; 9; 0; −1]. This post-filter should only be used when the DCTI is off, and the source material is 4 : 2 : 2 bandwidth. For dynamic use of the peaking circuit, an additional gain is provided on the peaking signal. This gain is made dependent on the energy in the peaking signal. To overcome an unwanted coring on structured small signals, the output of the low-pass filter is also used to monitor if the high frequency contents are large enough to refrain from coring. Therefore the coring is set off if the HF energy level rises above a user definable threshold. 7.2.20 Spectral measurements are performed with the spectr_meas subpart, by calculating the sum of the absolute values from a chosen one of the three (high-pass and band-pass) filter outputs over a vertical window in a video field. With this window it is possible to disable subtitles. The maximum value of the chosen filter output within a windowed video field is also monitored. For the generally lower HF contents of the video signal, a weighting by a factor 4 can be switched in, while measuring on the High-Pass Filter (HPF). 7.2.18 BORDER BLANK The border and blanking processing is operating at a 4 : 4 : 4 level, just before the analog-to-digital conversion. Here it is possible to generate a blanking window and within this window a border window. The blanking window is used to blank the non-visible part of the output to the clamp level. The border window is the visible part of the video that contains no video, such as the sides in compression mode, this part can be programmed to display any luminance or colour level in an 8-bit accuracy; pixel repetition is also possible here. In case of multi PIP this block can generate separation borders in the horizontal and vertical direction. NON-LINEAR PHASE FILTER BEFORE DAC This non-linear phase filter adjusts for possible group delay differences in the Y, U and V output channels, and for sinus x/x bandwidth loss of the ADCs. The filter coefficients are [−L × (1 − u); 1 + L; −L × u]; where L determines the strength of the filter and u determines the asymmetry. The effect of the asymmetry is that for higher frequencies the delay is decreased for u ≤ 0.5. Settings are provided for L = 0, 1⁄8, 2⁄8, 3⁄8 and u = 0, 1⁄4, 1⁄2. 1999 May 03 DCTI 15 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) 7.3 7.3.1 SAA4978H 7.3.6 Analog output blocks The SAA4978H contains an embedded 80C51 microcontroller core including a 1 kbyte RAM and a 32 kbyte ROM. It also includes an I2C-bus user control interface. For development reasons an external ROM can be accessed with 64 kbyte maximum size. An external emulator can be connected. TRIPLE 10-BIT DIGITAL-TO-ANALOG CONVERSION Three identical DACs are used to convert Y, U and V with a 32 or 16 MHz data rate. 7.3.2 ANALOG ANTI-ALIASING POST-FILTER A 3rd-order linear phase filter is applied to each of the Y, U and V channels. It provides a notch on fclk (32 MHz at Y, U and V) to strongly prevent aliasing to low frequencies, which would be most disturbing. The filters can be bypassed if external filtering with other characteristics is desired. Bandwidth and gain accuracy are given in Chapter 11. 7.3.3 The main difference to most existing 80C51 derivatives is: • 768 byte auxiliary RAM from which 128 bytes can be accessed as subtitle RAM • Interrupt vector address for the I2C-bus is 33H • On-chip ROM code protection • SNERT at 1 or 2 Mbaud with additional Sample Frequency Registers (SFRs) instead of UART PLL • Host interface containing all control registers access e.g. via MOVX instruction. The PLL consists of a ring oscillator, Discrete Time Oscillator (DTO) and digital control loop. The PLL characteristic is controlled by means of the microcontroller. 7.3.4 7.3.7 The digital outputs UVAL, UVA0, UVA1, UVA2, UVA3, YAL, UVCL, UVC0, UVC1, UVC2, UVC3, YCL, WEA, WEC and IEC can be set in 3-state mode if not connected in the application. This means that these outputs with index 0 to 3 are set in 3-state if 4 : 1 : 1 is chosen, and the outputs with index L are set in 3-state if 8 bits output is chosen. The read or write operation must be set by the microcontroller. When writing to the bus, 2 bytes are loaded by the microcontroller; one for the address, the other for the data. When reading from the bus, 1 byte is loaded by the microcontroller for the address, the received byte is the data from the addressed SNERT location. 7.3.8 The SNERT interface replaces the standard UART interface. In contrast to the 80C51 UART interface there are additional control registers, other I/O pads and no byte separation time between address and data. After power-on reset the 1 Mbaud mode is active. Switching baud rate during transmission should be avoided. POWER-ON RESET All digital blocks except PLL are reset by a HIGH level at the reset pin. Only the watchdog counter is reset by the falling edge of the reset pulse. The PLL needs no reset. The frequency guard generates a single reset pulse with a duration of 0.875 ms when the actual frequency enters the desired range of 14 to 18 MHz. If the frequency leaves this range then no reset pulse is generated. PSP For dynamically changing data such as timing signals, the programmable signal positioner generates them on the basis of parameters sent by the microcontroller. For the reset function of the microcontroller, a watchdog timer is also built-in that creates a reset pulse unless it is triggered by a change in the Bone signal within a preset time (1.05 s). 1999 May 03 BOARD LEVEL TESTABILITY Boundary scan test is implemented, according to “IEEE standard 1149.1”. The boundary scan affects all digital pins and will cover all connections from the SAA4978H to other ICs that are also equipped with BST. The connectivity of the analog YUV input/output pins can also be tested with the use of BST. SNERT A SNERT interface is built-in to transform the parallel data from the microcontroller into 1 or 2 Mbaud switchable SNERT data. This interface is also capable of reading data from the SNERT bus should it be required to access read registers. 7.3.5 MICROCONTROLLER 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... NAME ADDRESS HEX READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) DESCRIPTION Clamp registers (clamp position in steps of one pixel, only first quarter of line available) CLAMP_START 300 write X X X X X X X X clamp start position CLAMP_STOP 301 write X X X X X X X X clamp stop position AGC_GAIN_Y 302 write X X X X X X X X X set Y gain (−3 to +6 dB) AGC_GAIN_U 303 write X X X X X X X X X set U gain (−3 to +6 dB) AGC_GAIN_V 304 write X X X X X X X X X set V gain (−3 to +6 dB) YUV_SELECT 305 write OVERFLOW_11_HIGH 300 read E X X X X X X X X read HIGH byte level 11 OVERFLOW_11_LOW 301 read E X X X X X X X X read LOW byte level 11 OVERFLOW_10_HIGH 302 read E X X X X X X X X read HIGH byte level 10 OVERFLOW_10_LOW 303 read E X X X X X X X X read LOW byte level 10 OVERFLOW_01_HIGH 304 read E X X X X X X X X read HIGH byte level 01; underflow/overflow OVERFLOW_01_LOW 305 read E X X X X X X X X read LOW byte level 01; underflow/overflow 306 write AGC Overflow detection control X X select ADC (Y, U, V, V) Philips Semiconductors CONTROL REGISTER DESCRIPTION Picture Improved Combined Network (PICNIC) 1999 May 03 8 17 Digital front-end DFRONTEND_CONTROLS1 X X X X X X X X U_CLAMP_COR_FVAL X X X U clamp correction value (twos complement) used in external correction mode V_CLAMP_COR_FVAL X X X 307 write UV clamp correction mode (internal, external, keep, keep) X X X X X X X UV_TAU Y_DELAY X X select UV clamp time constant (4, 9, 19 and 39 lines) X X select Y delay (−1, 0, 1, 2) Product specification DFRONTEND_CONTROLS2 X X SAA4978H UV_COR_MODE V clamp correction value (twos complement) used in external correction mode This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) MFF_WIDTH DFRONTEND_CONTROLS3 X X X 308 write select MFF width (0, 3, 5, 7, 9, 9, 9 and 9 samples) X X X X X X X input λ settings (0, 1⁄16, 2⁄16, 3⁄16) NLP_L_AD NLP_U_AD input µ settings (0, 1⁄4, 1⁄2, 1⁄2) X X NOTCH ACT_VIDEO_WINDOW_H_START DESCRIPTION X select notch (off, on) 309 write X X X X X X X X ACT_VIDEO_WINDOW_H_LENGTH 30A write X X X X X X X X ACT_VIDEO_WINDOW_V_START write write CLAMP_U_ERROR 306 read 0 X X X X X X X clamp offset in U (twos complement; gain 16) used in internal correction mode CLAMP_V_ERROR 307 read 0 X X X X X X X clamp offset in V (twos complement; gain 16) used in internal correction mode 30D write X X X X X X X X 18 30B ACT_VIDEO_WINDOW_V_LENGTH 30C X X X X X X X X X S X X X X X X X X X not double buffered for PSP (WEA) Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME Bus A output control BUS_A_CONTROL1 Y_BUS_A_8BIT_ROUND X X Y bus A (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit truncated) Y_BUS_A_DITHER X X X SEL_422_OUT X UV_CORING select 4 : 2 : 2 output format (4 : 1 : 1, 4 : 2 : 2) X X 30E write select UV coring mode (off, 0.5, 1.0, 1.5 LSB) X X X X X X X UV_BUS_A_DITHER X X UV bus A (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit rounded) X X X dithering mode on UV bus A (F1L1, F1L2, F1L1, F1L2, F2L1, F2L2, F4L1, F4L2) SAA4978H UV_BUS_A_8BIT_ROUND Product specification BUS_A_CONTROL2 dithering mode on Y bus A (F1L1, F1L2, F1L1,F1L2, F2L1, F2L2, F4L1, F4L2) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) FORCE_BUS_A_TRI X WE_A_QUALIFIER DESCRIPTION force bus A output to 3-state including WEA (off, on) X WEA definition (prequalifier, qualifier) Bus B input control BUS_B_CONTROL 30F write X X X X X X X SEL_INPUT_FORMAT X X select input format (4 : 2 : 2 external, 4 : 1 : 1 external, 4 : 2 : 2 internal, 4 : 2 : 2 internal) SEL_DOUBLE_CLOCK X SEL_ASYNCHRONOUS X UV_INV X WE_B_QUALIFIER X 19 INV656 select double input data rate (single, double clock) select asynchronous input clock (synchronous, asynchronous clock) invert U and V data (not inverted, inverted) WEB definition (prequalifier, qualifier) X invert MSB of bus B input (related to 656 based input) Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME TBC/SRC control write S X X X X X X X X X control of compression/expansion at line centre (twos complement: −256 to +255) C2 311 write S X X X X X X X X control of compression/expansion at line edges (twos complement: −128 to +127) H_SHIFT_HIGH 312 write S X X X X X X X X horizontal shift (bits 15 to 8) H_SHIFT_LOW 313 write S X X X X X X X X horizontal shift (bits 7 to 0) H_DATAPATH_DELAY 314 write S X X X X X X X X horizontal data path delay (bits 7 to 0) H_DATAPATH_DELAY_SKEW 315 write S X X X X X X X H_DATAPATH_DELAY_MSB SKEW_MULT X X X X X horizontal data path delay (bits 12 to 8) X X skew multiply factor (off, 1, undefined, −1) Product specification 310 SAA4978H C0 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... LIMERIC_THR_UP 316 write LIMERIC_WANTED_VALUE 317 write S X X X X X X X X sensitivity of noise estimator LIMERIC_TASTE_AND_COMP 318 write S X X X X X X X X DESCRIPTION Noise estimator X X X X X X X X threshold to define the weight factor of considered pixels TASTE_VALUE X X X X taste value COMPENSATION_VALUE LIMERIC_LB_DETAIL X X X X compensation value (twos complement) 319 write S X X X X X X X X bottom limit of detail counter LIMERIC_UB_DETAIL 31A write S X X X X X X X X top limit of detail counter LIMERIC_YP_AND_OVLPL 31B write S X X X X X X X X OVERLAP_VALUE X X X X overlap level for noise estimator (0 to 15) PREFILTER_SCALING X X 20 SOB_NEGLECT X INPUT8BIT X luminance prefilter scaling (1, 1⁄2, 1⁄4, off) Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME neglects the Sum Over a Block value of those blocks that contain values towards black and white; (use, neglect) = (measure except around black and white level, measure everywhere number of bits at input of NE block (9, 8) read E 0 0 0 0 X X X X noise estimator value NEST_FILT 309 read E X X X X X X X X filtered noise estimator value DETAIL_CNT_H 30A read E X X X X X X X X number of details detected in field (HIGH byte) DETAIL_CNT_L 30B read E X X X X X X X X number of details detected in field (LOW byte) Product specification 308 SAA4978H NEST This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) DESCRIPTION Clamp noise reduction (CLINIC) control CLINIC_CONTROL 31C write S X X X X X X K_SCALE X X X select K scale (4, 2, 1, 1⁄2, 1⁄4, 1⁄8, 1⁄16, 1⁄32) K_ONE X CLINIC_OFF select K is 1 versus adaptive (adaptive, K = 1) X DITHER CLINIC function off (on, off) X dither on (off, on) CLINIC_MAX_DIFF 31D write S X X X X X X X X maximum difference allowed between actual and stored segment value (bits 9 to 2) CLINIC_THRESHOLD 31E write S X X X X X X X X threshold to define motion in segments (bits 9 to 2) CLINIC_DIF_AND_THR_LSB 31F write S X X X X MAX_DIFF_LSB 21 X X maximum difference allowed between actual and stored segment value (bits 1 and 0) THRESHOLD_LSB X X threshold to define motion in segments (bits 1 and 0) 30C read E X X X X X X X X number of events per field with motion above threshold TOT_COR_H 30D read E X X X X X X X X accumulated absolute clamp correction in field (bits 18 to 11) TOT_COR_M 30E read E X X X X X X X X accumulated absolute clamp correction in field (bits 10 to 3) TOT_COR_L 30F read E 0 0 0 0 0 X X X accumulated absolute clamp correction in field (bits 2 to 0) S X X X X X X X X Line memory and noise reduction (LIMERIC) control write N_DIST X X select n_dist (2, 4, 8, 9) PC_DIST PE_DIST X X X X select pc_dist (1, 2, 3, 4) select pe_dist (5, 6, 7, 8) SAA4978H 320 Product specification NBR_EVENTS LIMERIC_CONTROL Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) WEAVE X SEL_N_THR DESCRIPTION weave on (off, on) X select threshold from estimator versus threshold from microcontroller (estimator, microcontroller) Band split peaking and coring PEAKING_CONTROL1 321 write S X X X X 2D_PEAK_COEF X X X 2D peaking coefficient (0, 2⁄4, 3⁄4, 4⁄4, 5⁄4, 6⁄4, 7⁄4, 8⁄4) CORE_THR V_GAINSTR X X X X X X X 322 write S coring threshold (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 LSB) X X X vertical peaking (0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8, 7⁄8) Noise reduction energy measurement 22 VHF_ENERGY_SUM_H 310 read E X X X X X X X X mean vertical energy measured in one field (bits 15 to 8) VHF_ENERGY_SUM_L 311 read E X X X X X X X X mean vertical energy measured in one field (bits 7 to 0) VHF_ENERGY_MAX 312 read E X X X X X X X X maximum vertical peak energy measured in one field BBD_FIRST_VIDEOLINE1 313 read E X X X X X X X X 1⁄ BBD_LAST_VIDEOLINE1 314 read E X X X X X X X X 1⁄ BBD_FIRST_VIDEOLINE2 315 read E X X X X X X X X 1⁄ BBD_LAST_VIDEOLINE2 316 read E X X X X X X X X 1⁄ BBD_WINDOW_H_START 323 write S X X X X X X X X BBD_WINDOW_H_STOP 324 write S X X X X X X X X BBD_WINDOW_V_START 325 write S X X X X X X X X X BBD_WINDOW_V_STOP 326 write S X X X X X X X X X Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME Black bar position and control 2 number of first line after black bar having video 2 number of last line before black bar having video 2(number + 1) of first line after black bar having video Product specification SAA4978H 2(number + 1) of last line before black bar having video This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... BBD_LOGO_LENGTH 327 write S X X X X X X X X number of non-black samples permitted in a black bar line BBD_SLICE_LEVEL1 328 write S X X X X X X X X 1⁄ BBD_SLICE_LEVEL2 329 write S X X X X X X X X 1⁄ BLACK_OFFSET 32A write S X X X X X X X X definition of DC shift in Y (twos complement) LUT_DATA 32B write THRESHOLD_HIS 32C write S X X X X X X X X if Yn − Yn − 1 > threshold then Yn is added to the histogram SPLIT_POSITION 32D write S X X X X X X X X position of split point in steps of 4 pixels (left side unprocessed) HISTOGRAM_CONTROL1 32E write DESCRIPTION 2 threshold to detect black (detector 1) 2 threshold to detect black (detector 2) Histogram control X X X X X X X X transfer of 32 bytes that define the Y transfer LUT from microcontroller to histogram (twos complement). The first write after a field reset resets the write pointer; subsequent write operations increment the write pointer. 23 X X X X X X X not double buffered HISTO_GAIN X X X X histogram gain (0 to 15) NOISE_RED X FILTER_1_ON noise reduction on X FILTER_2_ON 1 : 2 : 1 filter on (off, on) X RESERVED WRITE ADDRESS 32F write YUV_IN_CONTROL 330 write S 1 : 0 : 2 : 0 : 1 filter on (off, on) X X X X X ROUND UV_POS X UV_GAIN X X 331 write S select UV ratio 128 versus 64 (64, 128) follow if dy > 0 versus follow dy (follow dy, follow if dy > 0) UV gain (0, 1⁄2, 1, 2) X X X X X X X X start of horizontal histogram window SAA4978H X Product specification X rounding versus truncating (truncated, rounded) RATIO_LIMIT HGM_WINDOW_H_START Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... HGM_WINDOW_H_STOP 332 write S HGM_WINDOW_V_START 333 write S X X X X X X X X X start of vertical histogram window HGM_WINDOW_V_STOP 334 write S X X X X X X X X X stop of vertical histogram window HISTOGRAM_DATA 317 read Y_MIN 318 read E X X X X X X X X minimum Y value in previous field Y_MAX 319 read E X X X X X X X X maximum Y value in previous field U_MIN 31A read E X X X X X X X X minimum U value in previous field U_MAX 31B read E X X X X X X X X maximum U value in previous field V_MIN 31C read E X X X X X X X X minimum V value in previous field V_MAX 31D read E X X X X X X X X maximum V value in previous field MAX_HISTO_VALUE 31E read E X X X X X X X X maximum value in histogram of previous field SMART_BLACK 31F read E X X X X X X X X black level indication (filtered Y_MIN) THRESHOLD_HIGH 335 write X X X X X X X X maximum level required for valid event THRESHOLD_LOW 336 write X X X X X X X X minimum level required for valid event HIGH_TIME 337 write X X X X X X X X minimum time above HIGH threshold required for valid event LOW_TIME 338 write X X X X X X X X minimum time below LOW threshold required for valid event SUBTITLE_CONTROLS 339 write DESCRIPTION X X X X X X X X stop of horizontal histogram window Histogram outputs X X X X X X X X Histogram read command. The first read after a field reset resets the read pointer; subsequent read operations increment the read pointer. Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME 24 Subtitle control X X X RESET_EVENTS X reset events (cumulative, reset) RESET_PEAK SUBT_WINDOW_H_START X 33A write X X X X X X X X select event versus between thresholds mode (within thresholds, events) select ‘every field’ versus ‘bleed’ (bleed, every field) Product specification X SAA4978H EVENT_MODE This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SUBT_WINDOW_H_STOP 33B write X X X X X X X X SUBT_WINDOW_V_START 33C write X X X X X X X X X SUBT_WINDOW_V_STOP 33D write X X X X X X X X X EVENTS 280 to 2FF read DESCRIPTION X X X X X X X X Events read command. Number of transitions in the 128 lines of the subtitle window. read 321 read BAR_ARRAY 33E write BAR_ARRAY_Y 33F write S X X X X X X X X display bar luminance level BAR_ARRAY_U 340 write S X X X X X X X X display bar U level (twos complement) BAR_ARRAY_V 341 write S X X X X X X X X display bar V level (twos complement) BAR_ARRAY_H_START 342 write S X X X X X X X X horizontal start position of the display bars (see also BAR_ARRAY_RESOLUTION) BAR_ARRAY_V_START 343 write S X X X X X X X X vertical start position of the display bars BAR_ARRAY_WIDTH 344 write S X X X X X X X X the width of each bar in number of lines (see also BAR_ARRAY_RESOLUTION) BAR_ARRAY_SPACE 345 write S X X X X X X X X the number of lines between two bars (see also BAR_ARRAY_RESOLUTION) BAR_ARRAY_CONTROL 346 write S E X X X X X X X X 1⁄ 2 peak value of Y within the event window Bars control 25 BAR_ARRAY_ON X X X X X X X X Bar array write command. The first write after a field reset resets the write pointer; subsequent write operations increment the write pointer (see also BAR_ARRAY_RESOLUTION). X X X X select bar array on (off, on) Product specification 320 PEAK_Y SAA4978H RESERVED READ ADDRESS Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) BAR_ARRAY_RESOLUTION X BAR_ARRAY_TRANS DESCRIPTION select bar array resolution (BAR_ARRAY_H_START × 4, BAR_ARRAY_WIDTH × 2, BAR_ARRAY_SPACE × 2, BAR_ARRAY × 4, BAR_ARRAY_H_START × 2, BAR_ARRAY_WIDTH × 1, BAR_ARRAY_SPACE × 1, BAR_ARRAY × 2) X select mashing versus superimpose (superimpose, mashing) Bus C output control BUS_C_CONTROL1 347 write S X X X X X X X X SEL422OUT X select 4 : 2 : 2 output (4 : 1 : 1, 4 : 2 : 2) overridden by DPCM UV_BUS_C_8BIT_ROUND X X 26 UV bus C (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit truncated) MPIP BUS_C_CONTROL2 multi-PIP mode (off, 2 × 2, 3 × 3, 4 × 4); see also memory write control X X UV_BUS_C_DITHER X X X 348 write S dither line and field phase (f1l1, f1l2, f1l1, f1l2, f2l1, f2l2, f4l1, f4l2) X X X X X X X DPCM X DPCM output (4 : 1 : 1/4 : 2 : 2, DPCM) overrides SEL422OUT FORCE_BUS_C_TRI X Y_BUS_C_8BIT_ROUND X X Y bus C (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit truncated) dither line and field phase (f1l1, f1l2, f1l1, f1l2, f2l1, f2l2, f4l1, f4l2) Product specification X X X force bus C to 3-state including WEC and IEC (off, on) SAA4978H Y_BUS_C_DITHER Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... WE_WINDOW_H_START 349 write X X X X X X X X start of horizontal write enable window WE_WINDOW_H_STOP 34A write X X X X X X X X stop of horizontal write enable window ACQ_EN_WINDOW_V_START 34B write X X X X X X X X X start of vertical write and input enable window ACQ_EN_WINDOW_V_STOP 34C write X X X X X X X X X stop of vertical write and input enable window IE_WINDOW_H_START 34D write X X X X X X X X start of horizontal input enable window IE_WINDOW_H_STOP 34E write X X X X X X X X stop of horizontal input enable window WE_IE_SHIFT 34F write DESCRIPTION Field memory control X X X X WE_C_SHIFT X X fine shift of WEC (0, 1, 2, 3 pixels) IE_C_SHIFT X X fine shift of IEC (0, 1, 2, 3 pixels) 27 CHOP_CYCLE 350 write X X chop cycle of WEC and IEC (1, 1⁄2, 1⁄3, 1⁄4) RE_WINDOW_H_START 351 write X X X X X X X X define start of horizontal read enable window RE_WINDOW_H_STOP 352 write X X X X X X X X define stop of horizontal read enable window RE_WINDOW_V_START 353 write X X X X X X X X X define start of vertical read enable window RE_WINDOW_V_STOP 354 write X X X X X X X X X define stop of vertical read enable window 355 write Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME Bus D input control BUS_D_CONTROL S X SEL_INPUT_FORMAT X X X X select input format (4 : 2 : 2 external, 4 : 1 : 1 external, 4 : 2 : 2 internal, DPCM external) 356 write X X X X X X X X BE_WINDOW_H_STOP 357 write X X X X X X X X BE_WINDOW_V_START 358 write X X X X X X X X X BE_WINDOW_V_STOP 359 write X X X X X X X X X select undither active (off, on) Product specification X BE_WINDOW_H_START SAA4978H UNDITHER This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) 35A write DESCRIPTION CTI control DBACKEND_CONTROLS1 X X X X X X CTI_SEPARATE X CTI_PROTECTION X CTI_GAIN select hill protection (off, on) CTI gain (0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8, 7⁄8) X X X CTI_FILTER_ON DBACKEND_CONTROLS2 X 35B write post-filter on (off, on) X X X X X X X X X X limit CTI range (0, ±4, ±8, ±12) CTI_LIMIT CTI_SUPERHILL X CTI_DDX_SEL select super hill protection (off, on) X CTI_SUPERHILL 28 NLP_DA separate U and V processing (linked, separate) select first differentiating filter (−1 0 0 1, −1 −2 −1 1 2 1) X X X X 35C write hill detection threshold (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) X X X X Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME X X output λ settings (0, 1⁄8, 2⁄8, 3⁄8) NLP_L_DA NLP_U_DA output µ settings (0, 1⁄4, 1⁄2, 1⁄2) X X Dynamic peaking and coring PEAKING_CONTROL2 35D write S X X X X X X X X X X X α value (0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16, 8⁄16) ALPHA BETA DELTA LUTREGA β value (0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16, 8⁄16) X X X δ value (0, 1⁄4, 1⁄2, 1) X X 35E write S X X X X X X X X programmable coring replacement values for luminance levels 1 to 4 LEVEL2 X X LEVEL3 X X LEVEL4 LUTREGB X X X 35F write S level 2 (0, 1, 2, 3) level 3 (0, 1, 2, 3) level 4 (0, 1, 2, 3, 4, 5, 6, 7) X X X X X X X X programmable coring replacement values for luminance levels 5 to 7 Product specification X level 1 (0, 1) SAA4978H LEVEL1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) LEVEL5 DESCRIPTION X X X level 5 (0, 1, 2, 3, 4, 5, 6, 7) LEVEL6 X X X LEVEL7 level 6 (0, 1, 2, 3, 4, 5, 6, 7) X X level 7 (4, 5, 6, 7) COR_THR 360 write S X X X X X X X X local energy above coring-threshold switches off coring PEAKING_CONTROL3 361 write S X X X X X X X X X X X τ value (0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16, 8⁄16) TAU NEGGAIN X X CORING X ENERGY_SEL ENERGY_SELECT_V_START X X 362 write negative gain value (0, 1⁄4, 1⁄2, 1) coring (coarse, fine) in accordance with LUTREGA and LUTREGB; see Fig.13 energy select (high × 4, mid, low, high) X X X X X X X X X start of vertical energy select window 29 ENERGY_SELECT_V_STOP 363 write RESERVED READ ADDRESS 322 read E X X X X X X X X X stop of vertical energy select window X X X X X X X X RESERVED READ ADDRESS 323 read E X X X X X X X X ENERGY_MAX 324 read E X X X X X X X X maximum peak energy measured in one field Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME Blanking control (definition of blanking window) BLANKING_WINDOW_H_START 364 write X X X X X X X X BLANKING_WINDOW_H_STOP 365 write X X X X X X X X BLANKING_WINDOW_V_START 366 write X X X X X X X X X BLANKING_WINDOW_V_STOP 367 write X X X X X X X X X BORDER_SIDE_H_START 368 write X X X X X X X X start of right border BORDER_SIDE_H_STOP 369 write X X X X X X X X end of left border BORDER_SIDE_V_START 36A write X X X X X X X X X start of lower border BORDER_SIDE_V_STOP 36B write X X X X X X X X X stop of upper border BORDER_BAR_H_START 36C write Border control 36D write X X X X X X X X width of horizontal bars BORDER_BAR_V_START 36E write X X X X X X X X X start of first vertical bar Product specification BORDER_BAR_H_WIDTH SAA4978H X X X X X X X X start of first horizontal bar This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... BORDER_BAR_V_WIDTH 36F write BORDER_REPEAT_H 370 write BORDER_REPEAT_V 371 write BORDER_Y 372 write X X X X X X X X Y value of sides and bars BORDER_U 373 write X X X X X X X X U value of sides and bars (twos complement) BORDER_V 374 write X X X X X X X X V value of sides and bars (twos complement) 375 write DESCRIPTION X X X X X X X X X width of vertical bars X X X X X X X X horizontal repeat value X X X X X X X X X vertical repeat value PLL PLL_CK_AND_CD V PLL_CK V PLL_CD V PLL_IDTO_PLUS_VARIOUS 376 write PLL_IDTO(18-16) X X X X X X X X X X X X X K factor control (0 to 31) X X X damping control (0 to 7) X X X V 30 PLL_OFF X PLL_OPEN V DO_SNAP X X X X X X increment offset for DTO bits 18 to 16 (twos complement; bit 18 is the sign bit) X X Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME PLL off; keep output frequency (off, on) PLL open loop mode (closed, open) do snapshot PLL_IDTO(15-8) 377 write V X X X X X X X X increment offset for DTO bits 15 to 8 PLL_IDTO(7-0) 378 write V X X X X X X X X increment offset for DTO bits 7 to 0; transfers all bits (18 to 0) PLL_SKEW_DELAY 379 write PLL_PE_MAX(15-8) 325 read V X X X X X X X X maximum phase offset during field HIGH byte PLL_PE_MAX(7-0) 326 read V X X X X X X X X maximum phase offset during field LOW byte; transfers all bits (15 to 0) PLL_PE_MIN(15-8) 327 read V X X X X X X X X minimum phase offset during field HIGH byte X X X skew transferred: 512 × (1 + PLL_SKEW_DELAY) clocks after HREF; PLL_SKEW_DELAY (0 to 7) Product specification SAA4978H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... PLL_PE_MIN(7-0) 328 read V X X X X X X X X minimum phase offset during field LOW byte; transfers all bits (15 to 0) PLL_PE_SUM(15-8) 329 read V X X X X X X X X accumulated phase offset during field HIGH byte PLL_PE_SUM(7-0) 32A read V X X X X X X X X accumulated phase offset during field LOW byte; transfers all bits (15 to 0) PLL_PE_SABS(15-8) 32B read V X X X X X X X X accumulated absolute phase offset during field HIGH byte PLL_PE_SABS(7-0) 32C read V X X X X X X X X accumulated absolute phase offset during field LOW byte; transfers all bits (15 to 0) PLL_INC_OFFSET(19-16) 32D read V 0 0 0 0 X X X X increment offset bits 19 to 16 (twos complement; bit 19 is the sign bit) PLL_INC_OFFSET(15-8) 32E read V X X X X X X X X increment offset bit HIGH byte PLL_INC_OFFSET(7-0) 32F read V X X X X X X X X increment offset bit LOW byte; transfers all bits (19 to 0) PLL_CKA_VALUE 330 read V 0 0 0 X X X X X actual K value PLL_ADAPT_STATUS 331 read V 0 0 0 0 0 0 0 X PLL adaptive status (locked, unlocked) RESERVED READ ADDRESS 332 read HA_VALUE 333 read X X X X X X X X available after VA or COPY_VALUE_STROBE VA_VALUE 334 read X X X X X X X X as HA_VALUE; bit 8 in register VARIOUS_BITS HD_VALUE 335 read X X X X X X X X available after VD or COPY_VALUE_STROBE VD_VALUE 336 read X X X X X X X X as HD_VALUE; bit 8 in register VARIOUS_BITS PIP_RISING_EDGE_POS 337 read X X X X X X X X PIP_FALLING_EDGE_POS 338 read X X X X X X X X INTR_0_SOURCE 339 read 0 0 0 0 0 0 X X interrupt read; register reset after read DESCRIPTION Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME 31 Read registers PSP Product specification SAA4978H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) VA_INTR_ACTIVE X VA interrupt active (not active, active) WE_INTR_ACTIVE VARIOUS_BITS DESCRIPTION X 33A read WE interrupt active (not active, active) 0 0 0 0 0 0 X X VA_VALUE_MSB X MSB of VA VD_VALUE_MSB X MSB of VD Various PSP control 32 VA_SYNC_WINDOW_START 37A write X X X X X X X X X start of vertical VA_SYNC enable window VA_SYNC_WINDOW_STOP 37B write X X X X X X X X X stop of vertical VA_SYNC enable window VA_INC_HOR_POS 37C write X X X X X X X X horizontal position of VA_COUNTER clock HREF_EXT_START 37D write X X X X X X X X start HREFEXT pulse HREF_EXT_STOP 37E write X X X X X X X X stop HREFEXT pulse INTR_AND_SYNC_ENABLE 37F write X X X X X X INTR_VA_ENABLE Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME X VA interrupt enable (disabled, enabled) INTR_WE_ENABLE X INTR_VD_ENABLE X HD_CNTR_RST_BY_HDREF X DIVIDE_VD_INC X SEL_HA_CLAMP X WE interrupt enable (disabled, enabled) VD interrupt enable (disabled, enabled) HD counter reset from HD_REF (no reset, reset by HD_REF) divide VD_INC by 2 (100 Hz, progressive scan mode) select clamp-counter reset (HA_REF, HA) write X X X X X X X X X delay in number of lines delay at pin 157 caused by VA HD_START 381 write X X X X X X X X start HD pulse HD_STOP 382 write X X X X X X X X stop HD pulse VD_HOR_POS 383 write X X X X X X X X horizontal phase of VD H_EXT_POS 384 write X X X X X X X X HD counter length Product specification 380 SAA4978H INTR_VA_DELAY This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INTR_VD_DELAY 385 write X X X X X X X X X value of COUNTER_VD that initiates interrupt 1 PLL_OFF_START 386 write X X X X X X X X X vertical start of PLL_OFF window PLL_OFF_STOP 387 write X X X X X X X X X vertical stop of PLL_OFF window DISPLAY_CONTROL 388 write DESCRIPTION X X X X X X X X RE_SHIFT X X RE pixel shift (0, 1, 2, 3) ENABLE_RESET_BLANK X PIXEL_REPETITION enable blank reset (disabled, enabled) X ENABLE_BORDER_V_BAR enable pixel repetition (disabled, enabled) X ENABLE_BORDER_V_SIDE enable vertical bars (disabled, enabled) X ENABLE_BORDER_H_BAR enable vertical sides (disabled, enabled) X 33 ENABLE_BORDER_H_SIDE enable horizontal bars (disabled, enabled) X enable horizontal sides (disabled, enabled) write ACQ_WINDOWS_RESET 38A write TRIGGER to reset acquisition windows COPY_VALUE_STROBE 38B write TRIGGER to copy register values TRIGGER_FLYBACK 38C write TRIGGER to set VD output TRIGGER_SCAN 38D write TRIGGER to reset VD output COUNTER_VD_RESET 38E write TRIGGER to reset VD counter INTR_1_RESET 38F write TRIGGER to reset interrupt 1 DISPLAY_WINDOWS_RESET 390 write TRIGGER to reset display windows SEL_1FH 391 write X select back-end clock at 16 MHz for 1fH processing (32 MHz, 16 MHz) BUS_B_VREF 392 write NRPXDIV4 393 write X X X X X X X X X vertical start field reference for bus B S X X X X X X X X 1⁄ 4 of horizontal length of video data in data path Product specification 389 SAA4978H RESERVED WRITE ADDRESS Philips Semiconductors READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) Picture Improved Combined Network (PICNIC) 1999 May 03 ADDRESS HEX NAME This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) 394 write DESCRIPTION Testing RESET_CONTROL X FIELD_RESET X TEST_Y_IN_D 33B read X X X X X X X X test receive register at bus D; Y input TEST_UV_IN_D 33C read X X X X X X X X test receive register at bus D; UV input 395 write X X X X X X X X test register for analog functions; normal application mode: 49H Analog blocks ANASWITCH CLAMP_ACTIVE X clamp active STDIFF_CONV X STDIFF_CONV_AGC X STDIFF_CONV_AGC_FILTER single to differential converter and AGC X 34 FRONTEND_TO_OUTPUT single to differential converter, AGC and filter X ATT_OUT front-end to output X ATT_RECONSTRUCT_OUT attenuator to output X FRONTEND_TO_BACKEND RESERVED WRITE ADDRESS attenuator and reconstruction filter to output X 396 write RESERVED WRITE ADDRESS 397 write TM_AD_DA 398 write front-end to back-end X X X X X X X X test mode AD, DA blocks TM_ADDA2 X ADC and DAC test TM_ADDA1 TM_AD2DA single to differential converter Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME X X ADC and DAC test direct bypass from ADC to DAC Product specification SAA4978H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... READ/ DOUBLE 8 7 6 5 4 3 2 1 0 WRITE BUFFERED(1) DESCRIPTION SNERT control (these registers are implemented as special function register, they have a HEX address outside the normal control register range) SNCON 98 read/ write X 0 0 0 0 0 X X SNERT control register (reset on bit 1 of register $E8: power-on reset) TRM read X SNERT transmit busy flag REC read/ write MB2 read/ write X X SNERT receive busy flag SNERT baud rate (1 MHz, 2 MHz) SNADD 99 write X X X X X X X X address of SNERT message to be transmitted SNWDA 9A write X X X X X X X X data of SNERT message to be transmitted SNRDA 9B read X X X X X X X X data from SNERT bus after a completed reception 35 Note Philips Semiconductors ADDRESS HEX Picture Improved Combined Network (PICNIC) 1999 May 03 NAME 1. Blank means not double buffered; E means double buffered and data available at end of active video; S means double buffered and data clocked in at start of active video; V means double buffered and data valid at start of VA. Product specification SAA4978H Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage −0.5 +6 V VDDD; VDDO digital supply voltage −0.5 +6 V ∆VDDA − DDD supply voltage difference between analog and digital supply voltages −0.5 +0.5 V ∆VDDA − DDO supply voltage difference between analog and output supply voltages −0.5 +0.5 V VI input voltage for all digital input and digital I/O pins −0.5 +5.5 V Vi analog input voltage −0.3 VDDA + 0.3 V Tstg storage temperature −55 +150 °C Tj operating junction temperature 0 125 °C 10 THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Rth(j-a) thermal resistance from junction to ambient Rth(j-c) thermal resistance from junction to case 1999 May 03 36 in free air VALUE UNIT 25 K/W 2 K/W Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H 11 CHARACTERISTICS VDDD = VDDA = 3.3 V; AGC at 0 dB; Tamb = 25 °C; nominal parameter settings: 2fH/100 Hz mode; features transparent; equalized frequency response test signal: EBU colour bar 100/0/75/0 “CCIR471-1”; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.15 3.3 3.45 V VDD(I/O) microcontroller I/O supply voltage 3.0 − 5.5 V VDDO digital supply voltage for outputs 3.0 3.3 3.6 V total power dissipation − − 1.6 W Dissipation Ptot YUV input processing (including AGC) YAGC Y AGC setting to obtain full ADC range Vi(Y)(b-w) = 1.0 V (p-p); note 1 117 132 148 − UAGC U AGC setting to obtain full ADC range Vi(U) = 1.33 V (p-p); note 1 120 136 151 − VAGC V AGC setting to obtain full ADC range Vi(V) = 1.05 V (p-p); note 1 117 132 148 − ∆EG(YUV)all overall input to output gain f = 0 to 2.5 MHz (analog error between Y, U and V filters off) −5.6 − +5.6 % ∆EG(UV)i gain error between U and V inputs f = 0 to 2.5 MHz (analog filters off) from input to digital domain − 1 3.2 % ∆EG(UV)all overall gain error between U and V f = 0 to 2.5 MHz (analog filters off) from input to output − 1.2 4.0 % ∆EG(f)(UV)i filtered gain error between U and V input f = 0 to 1.25 MHz (analog filters on) from input to digital domain − 2 6.4 % ∆EG(f)(UV)all overall filtered gain error between U and V f = 0 to 2.5 MHz (analog filters on) from input to output − 2.5 8 % Ci input capacitance − 7 15 pF ILI input leakage current − − 100 nA ∆GAGC(min-max) difference in gain between AGC minimum and maximum 9 9.5 10 dB GAGC(acc) AGC gain accuracy digital − 9 − bits Gstep(AGC) step resolution gain of AGC − − 0.4 % 1999 May 03 clamp not active; 0 < Vi < VDDA + 0.3 maximum gain variation per step 37 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL αct PARAMETER crosstalk between inputs and outputs SAA4978H CONDITIONS MIN. TYP. MAX. UNIT f = 0 to 1 MHz; Zsource = 200 Ω − − 50 dB f = 1 to 5 MHz; Zsource = 200 Ω − − 44 dB Input clamp processing (Y clamp level digital 32; U and V clamp level digital 0 in twos complement) Eclamp(stat)(Y) static clamp error in Y channel −5.0 − +2.0 LSB Eclamp(stat)(UV) static clamp error in UV channel digital correction circuit off −3.0 − +3.0 LSB Eclamp(dyn) dynamic clamp error average value (1 σ) − − 0.25 LSB Cclamp clamping capacitance 10 22 − nF Rsource source resistance − − 350 Ω Iclamp(max) maximum clamp current −160 − +160 µA Tilt maximum drift in one line period − − 0.25 LSB Vi(clamp)(Y) Y input clamping voltage − − mV over complete AGC range 600 Input transfer functions (sample rate 16 MHz; 9 bits); see Fig.7 fi(s)(max) maximum input sample frequency 18 − − MHz δclk duty factor of (internal) clock cycle 40 − 60 % INL DC integral non linearity ramp input signal; AGC on; filters off −2 − +2 LSB DNL DC differential non linearity ramp input signal; note 2 −0.99 − +0.99 LSB SNR overall signal-to-noise ratio (no harmonics) from input to output note 3 50 52 − dB Φdiff(UV) differential phase in U and V − 1 2.5 deg Gdiff(Y) differential gain in Y front-end Y within 0.2 to 0.75 V − − 1.5 % Φdiff(Y) differential phase in Y front-end Y within 0.2 to 0.75 V − − 1 deg SVRR supply voltage ripple rejection filters off; note 4 35 − − dB PLL function (base frequency 32 MHz) σline-line sigma value of line-to-line jitter locked to stable HA; note 5 − 0.4 1.0 ns σfield-field sigma value of field-to-field jitter locked to stable HA; note 5 − 0.4 1.0 ns funlock frequency in unlocked state 30.7 32 33.3 MHz 1999 May 03 38 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL PARAMETER SAA4978H CONDITIONS MIN. TYP. MAX. UNIT YUV output processing; note 6; see Fig.6 Vo(Y)(b-w) Y black-to-white output voltage ZL = 10 kΩ 0.96 1.00 1.04 V Vo(U)(p-p) U output voltage (peak-to-peak value) ZL = 10 kΩ 1.27 1.33 1.38 V Vo(V)(p-p) V output voltage (peak-to-peak value) ZL = 10 kΩ 1.01 1.05 1.09 V ∆EG(UV)o gain error between U and V output f = 0 to 2.5 MHz (analog filters off) from digital domain to output − − 2.5 % ∆EG(f)(UV)o filtered gain error between U and V output f = 0 to 2.5 MHz (analog filters on) from digital domain to output − − 5 % Zo output impedance f = 0 to 10 MHz 65 75 85 Ω VY(d)(0) Y super black level voltage at 0 VbY = black level voltage VbY − 0.63 VbY − 0.6 VY(d)(1023) Y super white (headroom) voltage at 1023 VbY = black level voltage VbY + 1.47 VbY + 1.53 VbY + 1.59 V VY(d)(288) Y black level voltage at 288 VbY = black level voltage − VY(d)(768) Y white level voltage at 768 VbY = black level voltage VbY + 0.96 VbY + 1.0 VbY + 1.04 V VU(d)(0) U voltage at 0 − − VU(d)(1023) U voltage at 1023 VbU = lower U voltage; note 7 VV(d)(0) V voltage at 0 − VV(d)(1023) V voltage at 1023 VbV = lower V voltage; note 7 VbV + 1.13 VbV + 1.18 VbV + 1.23 V αres(clk) residual clock attenuation related to YOUT f = 32 or 16 MHz − − 40 dB 33.4 − − MHz VbY VbU VbY − 0.57 V − V V VbU + 1.43 VbU + 1.49 VbU + 1.55 V VbV − V Output transfer functions (sample rate 32 MHz; 10 bits) fclk(max) maximum sample clock δclk duty factor of clock cycle 40 − 60 % INL DC integral non linearity −2 − +2 LSB DNL DC differential non linearity −0.75 − +0.75 LSB note 2 Digital output bus A and C, WEA, WEC, IEC and HREFEXT (CL = 15 pF; IOL = 2 mA; RL = 2 kΩ); timing referred to CLK16, HREFEXT is not a 3-state output VOH HIGH-level output voltage 2.4 − − V VOL LOW-level output voltage − − 0.4 V IOZ output current in 3-state mode − − 1.0 µA Vext(OZ) external applied voltage in 3-state mode − − VDDO + 0.3 V td(o) output delay time − − 30 1999 May 03 −0.1 < Vo < VDDO + 0.1 see Fig.4 39 ns Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL PARAMETER th(o) output hold time SR slew rate SAA4978H CONDITIONS see Fig.4 MIN. TYP. MAX. UNIT 4 − − ns 200 500 700 mV --------ns Digital input bus B and D; timing referred to CLK32 for bus D and to CLK16, CLK32 or CLKAS for bus B (see Fig.4); the reference for bus B depends on the selected mode respectively single clock, double clock or asynchronous clock VIL LOW-level input voltage VIH HIGH-level input voltage tsu(i) input set-up time th(i) input hold time 0 − 0.8 5 V tolerant 2.0 − 5.5 V see Fig.4 6 − − ns see Fig.4 1 − − ns 0 − 0.8 V 2.0 − 5.5 V V CLKAS VIL LOW-level input voltage VIH HIGH-level input voltage th(i)(async) asynchronous input hold time 4 − − ns tL(min) minimum LOW time − − 10 ns tH(min) minimum HIGH time − − 10 ns TCLKAS(min) minimum period time TCLK32 − − ns 5 V tolerant the asynchronous clock may not be faster than CLK32 CLK16 and CLK32 (CL = 30 pF; IOL = 2 mA; RL = 2 kΩ) VOL LOW-level output voltage 0 − 0.4 V VOH HIGH-level output voltage 2.4 − − V to(r) output rise time see Fig.4 2 3 4 ns to(f) output fall time see Fig.4 2 3 4 ns tdHO CLK16 HIGH transition delay time see Fig.5 − − 20 ns thHO CLK16 HIGH transition hold time see Fig.5 4 − − ns tdLO CLK16 LOW transition delay time see Fig.5 − − 20 ns thLO CLK16 LOW transition hold time see Fig.5 4 − − ns RED, HD and VD (CL = 15 pF; IOL = 2 mA; RL = 2 kΩ); timing referred to CLK32; see Fig.4 VOH HIGH-level output voltage 2.4 − − V VOL LOW-level output voltage − − 0.4 V td(o) output delay time see Fig.4 − − 20 ns th(o) output hold time see Fig.4 4 − − ns SR slew rate 200 500 700 mV --------ns 1999 May 03 40 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL PARAMETER SAA4978H CONDITIONS MIN. TYP. MAX. UNIT Oscillator stage (operation with crystal or external clock) fosc oscillator frequency CL34 CL35 recommended load capacitor Rser1(xtal) crystal series resistance Cpar(xtal) crystal parallel capacitance − 12 − MHz − 12 − pF − 18 − pF see Fig.12 − − 250 Ω see Fig.12 − − 7 pF 0.7VDDIO − − V − − 0.3VDDIO V − − 0.4 V see Fig.11 I2C-bus signal: SDA and SCL; note 8 VIH HIGH-level input voltage VIL LOW-level input voltage VOL LOW-level output voltage fSCL SCL clock frequency − − 400 kHz tHD;STA hold time START condition 0.6 − − µs tSCLL SCL LOW time 1.3 − − µs tSCLH SCL HIGH time 0.6 − − µs tSU;DAT data set-up time 100 − − ns tSU;DAT1 data set-up time (before repeated START condition) 0.6 − − µs tSU;DAT2 data set-up time (before STOP condition) 0.6 − − µs tSU;STA set-up time repeated START 0.6 − − µs tSU;STO set-up time STOP condition 0.6 − − µs IOL = 3.0 mA SNERT bus timing valid for both 1 and 2 Mbaud: SNDA and SNCL; see Fig.10 VOH HIGH-level output voltage IOH = −0.06 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − 5.5 V tsu(i)(SNCL) input set-up time to SNCL 80 − − ns th(i)(SNCL) input hold time to SNCL 0 − − ns th(o) output hold time 50 − − ns tsu(o) output set-up time 260 − − ns tdis(o) output disable time − − 200 ns tcy(SNCL) SNCL cycle time 500 − 1000 ns tSNRSTH SNRST pulse HIGH time 500 − − ns td(SNRST-DAT) delay SNRST pulse to data 200 − − ns 1999 May 03 41 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL PARAMETER SAA4978H CONDITIONS MIN. TYP. MAX. UNIT HA and VA (horizontal and vertical sync input) VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − 5.5 V AC characteristics parallel bus: P0, P2, ALE and PSEN (external ROM access); see Fig.8 tW(ALE) ALE pulse width − 62.5 − ns tAVLL address valid to ALE LOW 17 − − ns tLLAX address hold after ALE LOW 20 − − ns tLLIV ALE LOW to instruction input − − 96 ns tLLPL ALE LOW to PSEN LOW − 31.25 − ns tW(PSEN) PSEN pulse width − 93.75 − ns tPLIV PSEN LOW to valid instruction input − − 60 ns tPXIX input instruction hold after PSEN 0 − − ns tPXIZ input instruction float after PSEN − − 30 ns tAVIV address to valid instruction input − − 128 ns tPLAZ PSEN LOW to address float − − 10 ns DC characteristics microcontroller pins: P0, P1, INT0, INT1, T0, T1, RSTW, RSTR, SNDA, SNCL, ALE, PSEN and EA VOH HIGH-level output voltage IOH = −0.06 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − 5.5 V ILI input leakage current − − ±10 µA CI/O pin capacitance − − 10 pF Analog Y, U and V input filters (3rd-order linear phase filter with notch at fCLK); see Fig.6 f(−3dB) 3 dB down frequency 5.4 5.6 5.8 MHz α(0.5) attenuation at 1⁄2fCLK (8 MHz) 7 8 − dB αsb stop band attenuation (after notch) 32 − − dB fnotch notch frequency tuned to 1⁄2fCLK 15.3 16 16.7 MHz td(g) group delay at 4 MHz signal frequency 52 55 58 ns 1999 May 03 42 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SYMBOL PARAMETER SAA4978H CONDITIONS MIN. TYP. MAX. UNIT Analog Y, U and V output filters (3rd-order linear phase filter with notch at fCLK) f(−3dB) 3 dB down frequency 11.3 11.7 12.1 MHz 7 8 − dB 32 − − dB 30.6 32 33.4 MHz α(0.5) attenuation at (16 MHz) αsb stop band attenuation (after notch) fnotch notch frequency tuned to 1⁄2fCLK td(g) group delay at 8 MHz signal frequency 26 td(g)(tol) group delay tolerance between channels 1⁄ f 2 CLK − 28 31 ns − 5 ns Notes 1. With AGC at −3 dB, Y full ADC range is obtained at Vi = 1.41 V; with AGC at 6 dB, Y full ADC range is obtained at Vi = 0.5 V; with AGC at −3 dB, U full ADC range is obtained at Vi = 1.89 V; with AGC at 6 dB, U full ADC range is obtained at Vi = 0.67 V; with AGC at −3 dB, V full ADC range is obtained at Vi = 1.48 V; with AGC at 6 dB, V full ADC range is obtained at Vi = 0.52 V; at AGC attenuation more than 0 dB, where the input signal has an amplitude above the nominal value, the input processing and transfer function may have decreased specification. 2. DNL is defined as deviation of the code length from the average code length in LSB; qn DNL = max(-----------------) : 0.99LSB means no missing code. q av – 1 3. Measurements taken using video analyzer VM700A at YUV output, control bit SEL_1FH (address 391H) set to logic 1, internal analog filters off, AGC gain (addresses 302H, 303H and 304H) set to 074H, digital processing in between, digital filters off, sampling frequency of 16 MHz. 4. Supply Voltage Ripple Rejection (SVRR) is a relative variation of the full scale analog input for a supply variation of 0.25 V over a frequency range from 20 Hz to 50 kHz. This includes 1⁄2fV, fV, 2fV, fH and 2fH which are major load frequencies. 5. Measurements carried out using Modulation Domain Analyzer HP53310A after change of control bit PLL_OPEN (address 376H) from logic 1 to logic 0 (open to closed-circuit). Control bits PLL_CK (address 375H) set to logic 0. Control bits PLL_CD (address 375H) set to 7. 6. The outputs are able to drive an external low-pass filter without slewing. In fH and 2fH this filter is of the type as described in Fig.6. For calculating an output filter the typical output impedance is also given in Fig.6. 7. The output levels for U and V have 1 dB reserve headroom in case of a 75% saturated colour bar. The maximum levels are 1.33 V + 1 dB = 1.49 V for U and 1.05 V + 1 dB = 1.18 V for V. Due to 1 dB headroom the typical AGC setting to obtain 0 dB from input to output for U and V is 83. 8. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure “I2C-bus and how to use it” (order number 9398 393 40011). 1999 May 03 43 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H tf handbook, full pagewidth tr 90% 90% CLOCK 1.5 V 10% 10% INPUT DATA MHB175 tsu(i) OUTPUT DATA th(i) data valid data transition period th(o) td(o) Fig.4 Data input/output timing diagram. handbook, full pagewidth CLK32 CLK16 thLO MHB176 thHO tdLO tdHO Fig.5 Timing relationship between CLK32 and CLK16. 1999 May 03 44 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H typical output impedance internally handbook, full pagewidth external load 5 µH (2.5) 90 Ω Vbuffer 70 Ω 0.3 Ω 200 Ω Cp = 10 pF 0.5 µH 20 pF (10) Vo 51 pF (25.5) 210 pF (105) MHB177 Possible external load to be driven by output buffer without slewing. Cp is including parasitic capacitance of the application. Values in brackets are 2fH mode. Fig.6 Output load circuit. handbook, full pagewidth 4.43 MHz burst 0.2 V 64 µs 1.0 V MHB178 Fig.7 Test signal for differential gain and phase measurements. 1999 May 03 45 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... S4 S5 S6 CDCLK tW(ALE) tLLIV ALE tAVLL tW(PSEN) tLLPL tPLIV PSEN 46 tPXIZ tPLAZ tPXIX tLLAX PORT 0 Philips Semiconductors S3 Picture Improved Combined Network (PICNIC) book, full pagewidth 1999 May 03 S2 S1 A0 to A7 INSTRUCTION INPUT tAVIV PORT 2 A8 to A15 MHB179 Product specification SAA4978H Fig.8 Program memory access timing. Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) Table 1 SAA4978H YUV formats; note 1 I/O PIN 4:2:2 FORMAT 4 : 1 : 1 FORMAT 4 : 2 : 2 FORMAT DOUBLE CLOCK 4 : 2 : 2 DPCM FORMAT YX8 Y07 Y17 Y27 Y37 Y07 Y17 U07 Y07 V07 Y17 Y07 Y17 YX7 Y06 Y16 Y26 Y36 Y06 Y16 U06 Y06 V06 Y16 Y06 Y16 YX6 Y05 Y15 Y25 Y35 Y05 Y15 U05 Y05 V05 Y15 Y05 Y15 YX5 Y04 Y14 Y24 Y34 Y04 Y14 U04 Y04 V04 Y14 Y04 Y14 YX4 Y03 Y13 Y23 Y33 Y03 Y13 U03 Y03 V03 Y13 Y03 Y13 YX3 Y02 Y12 Y22 Y32 Y02 Y12 U02 Y02 V02 Y12 Y02 Y12 YX2 Y01 Y11 Y21 Y31 Y01 Y11 U01 Y01 V01 Y11 Y01 Y11 YX1 Y00 Y10 Y20 Y30 Y00 Y10 U00 Y00 V00 Y10 Y00 Y10 YX0 Y0L Y1L Y2L Y3L Y0L Y1L U0L Y0L V0L Y1L Y0L Y1L UVX8 U07 U05 U03 U01 U07 V07 − − − − UC03 VC03 UVX7 U06 U04 U02 U00 U06 V06 − − − − UC02 VC02 UVX6 V07 V05 V03 V01 U05 V05 − − − − UC01 VC01 UVX5 V06 V04 V02 V00 U04 V04 − − − − UC00 VC00 UVX4 − − − − U03 V03 − − − − − − UVX3 − − − − U02 V02 − − − − − − UVX2 − − − − U01 V01 − − − − − − UVX1 − − − − U00 V00 − − − − − − UVX0 U0L − V0L − U03 V03 − − − − − − Note 1. Index X refers to different I/O buses: a) X = A: output to PALplus. b) X = B: input from PALplus, MPEG. c) X = C: output to first field memory for 2fH applications. d) X = D: input from SAA4990H, SAA4991WP. The first index digit defines the sample number, the second defines the bit number. 1999 May 03 47 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H handbook, full pagewidth CLK WE prequalifier mode WE qualifier mode Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • UX0 YL YL YL YL YL YL YL YL UVX8 U7 U5 U3 U1 U7 U5 U3 U1 UVX7 U6 U4 U2 U0 U6 U4 U2 U0 UVX6 V7 V5 V3 V1 V7 V5 V3 V1 UVX5 V6 V4 V2 V0 V6 V4 V2 V0 UVX0 UL YX8 • • • • • • • • • • • • • • • VL UL • • • • • VL MHB180 Fig.9 YUV data relationship defined by rising edge of WE in 4 : 1 : 1 format. 1999 May 03 48 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... write sequence: SDNA driven by SAA4978H a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 w0 w1 w2 w3 w4 w5 w6 HIGH 3-state LOW w7 read sequence: SDNA driven by SAA4978H HIGH 3-state LOW r0 SDNA driven by slave r1 r2 r3 r4 r5 r6 HIGH 3-state LOW r7 Philips Semiconductors LOW Picture Improved Combined Network (PICNIC) andbook, full pagewidth 1999 May 03 HIGH SNCL 49 HIGH 50% SNCL 50% 50% LOW t su(o) write sequence: SDNA driven by SAA4978H a6 t h(o) a7 w0 HIGH 3-state LOW w1 t o(dis) read sequence: SDNA driven by SAA4978H a6 HIGH 3-state LOW a7 t h(SNCL) SDNA driven by slave r0 MHB181 Product specification Fig.10 Timing diagram for SNERT bus. HIGH 3-state LOW SAA4978H t su(SNCL) r1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SNDA SNCL RSTW CLK32 62 DIFFIN 43 to 51 53 to 61 SNCL RSTR PLUS 2fH FEATURES 18 bus B 18 bus A WEA SNDA 1fH TO 2fH CONVERSATION RSTW PALPLUS MODULE CLK16 WEB SNDA 66 67 to 84 1 SNCL RSTW 2 8 RSTR 9 CLK32 89 CLK16 WEC 18 bus C 113 114 to 122 124 to 132 88 18 bus D RED 110 91 to 99 101 to 109 12 21 YIN 14 23 UIN 15 25 50 VIN YOUT UOUT VOUT Philips Semiconductors CLK16 Picture Improved Combined Network (PICNIC) 12 APPLICATION INFORMATION handbook, full pagewidth 1999 May 03 CLK32 SAA4978H 26 18 HA HDFL 28 VA 29 19 FBL VDFL 10 4 5 SCL 6 7 SDA WDRST 34 RST 35 OSCI 36 OSCO 37 TEST 12 MHz CL34 38 TRST 1 kΩ TMS 39 TDI 40 TDO 41 TCK MHB182 CL35 Product specification SAA4978H Fig.11 Application diagram. Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H handbook, halfpage Cpar(xtal) Rser1(xtal) MHB183 Fig.12 Equivalent circuit of crystal. output g rin co rin g handbook, full pagewidth se ar e fin co co input MHB184 Fig.13 Peaking coring transfer curves. 1999 May 03 51 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H 13 PACKAGE OUTLINE QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height SOT322-2 c y X A 120 121 81 80 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 41 160 1 40 ZD wM bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 4.07 0.50 0.25 3.70 3.15 0.25 0.38 0.22 0.23 0.13 28.1 27.9 28.1 27.9 0.65 HD HE 31.45 31.45 30.95 30.95 L Lp v w y 1.6 1.03 0.73 0.3 0.15 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT322-2 1999 May 03 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-03-14 97-08-04 MO112DD1 52 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H If wave soldering is used the following conditions must be observed for optimal results: 14 SOLDERING 14.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 14.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 14.3 14.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 1999 May 03 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 53 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) 14.5 SAA4978H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 May 03 54 Philips Semiconductors Product specification Picture Improved Combined Network (PICNIC) SAA4978H 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 May 03 55 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1999 SCA63 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/00/02/pp56 Date of release: 1999 May 03 Document order number: 9397 750 05277