HFA3763 Data Sheet June 1999 File Number 400MHz Quadrature Modulator and AGC Features The HFA3763 is a highly integrated baseband converter for quadrature modulation applications. The HFA3763 400MHz quadrature modulator and AGC is one of the seven chips in the PRISM® full duplex chip set (see Typical Application Diagram). It features all the necessary blocks for baseband modulation of I and Q signals. An output AGC and Baseband shaping filters are integrated in the design. Four filter bandwidths are programmable via a two bit digital control interface. In addition, these filters are continuously tunable over a ±20% frequency range via one external resistor. The modulator channel receives digital or analog I and Q data for processing. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency of modulation. A selectable buffered divide by 2 LO output and a stable reference voltage are provided for convenience of the user. • Integrates all IF Transmit Functions Ordering Information • Wireless Local Area Networks ™ PART NUMBER HFA3763IN • Broad Frequency Range . . . . . . . . . . . 10MHz to 400MHz • I/Q Amplitude and Phase Balance . . . . . . . . . . . 0.2dB, 2o • 5th Order Programmable Low Pass Filter. . . . . . . . . . . . . . . . . . . 2.2MHz - 17.6MHz • 400MHz Output AGC Amplifier/Attenuator . . . . . . . .45dB • Selectable Digital or Analog TX Baseband Inputs • Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm • Fast Transmit-on Switching . . . . . . . . . . . . . . . . . . . . . 1µs • Power Management/Standby Mode • Single Supply 2.7V to 5.5V Operation Applications • Wireless Local Loop Systems • PCMCIA Wireless Duplex Transceivers TEMP. RANGE (oC) -40 to 85 4237.4 PACKAGE • ISM Systems PKG. NO. 80 Ld TQFP • TDMA Packet Protocol Radios Q80.14x14 • PCS/Wireless PBX ÷2 MOD_LO_OUT LPF_TUNE_0 LPF_SEL0 LPF_SEL1 MOD_LO_IN LPF_TUNE_1 Simplified Block Diagram 2V REF 2V REF 0o/90o LO_GND LPF_TXI_IN I ∑ IF_OUT LPF_TXQ_IN 4-1 TX D OR A LPF_TX_I LPF_TX_Q MOD_TX_I MOD_TX_Q IF_AGC_IN MOD_TX_IF_OUT AGC_CTRL Q CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. HFA3763 Pinout GND GND GND GND GND GND GND GND GND GND GND GND GND AGC_VCC GND IF_OUT GND AGC_PE GND AGC_VCC 80 LEAD TQFP TOP VIEW 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 GND GND GND GND GND GND GND GND LPF_VCC 2V REF LPF_BYP LPF_TXI_IN LPF_TXQ_IN NC NC LPF_SEL1 LPF_SEL0 LPF_TUNE1 LPF_TUNE0 TX D or A 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND AGC_CTRL GND AGC_VCC GND IF_AGC_IN GND GND GND GND LO_GND MOD_BYP MOD_BYP MOD_VCC MOD_LO_OUT MOD_VCC MOD_LO_IN GND MOD_TX_IF_OUT MOD_TX_PE MOD_TXIMOD_TXQ+ MOD_TXQ- GND LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ NC NC NC NC GND GND NC NC NC NC MOD_TXI+ 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Typical Application Diagram PRISM FULL DUPLEX CHIP SET HFA3661 (File #4240) HFA3424/21 (File #4131) D U P L E X E R LNA LNA RF/IF CONVERTER BPF HFA3761 (File #4236) FILTER LPF IF AGC A/D QMODEM LPF RF LO1 HFA3524 (File #4062) SYNTHESIZER IF LO1 BASEBAND HFA3524 (File #4062) HFA3925 (File #4132) PA SYNTHESIZER IF LO2 HFA3763 (File #4237) RF LO2 AGC IF/RF CONVERTER BPF HFA3663 (File #4241) HFA3664 (File #4242) LPF AGC QMODEM D/A LPF OPTIONAL WHEN IN ANALOG MODE PRISM FULL DUPLEX RADIO CHIP SET, FILE #4238 4-2 HFA3763 TX D or A LPF_TXI_IN LPF_TXQ_IN Block Diagram LPF_TX_PE LPF_SEL1 LPF_SEL0 I Q LPF_TUNE0 LPF_TUNE1 LPF_TX_Q LPF_TX_Q + LPF_TX_I LPF_TX_I + 1.25V / 90o MOD TX I + MOD TX I MOD TX Q + MOD TX Q - 0o 2V REF ∑ ÷2 MOD_TX_PE VCC MOD_TX_IF_OUT 250 IF_AGC_IN AGC_CTRL 10K LO_GND VCC L1 OUTPUT MATCH COMPONENTS TABLE C1 FREQ. L2 (2XLO) MOD_LO_IN C2 50Ω NETWORK 50Ω MOD_LO_OUT IF_OUT NOTE: VCC, GND and Bypass capacitors not shown. 4-3 L1 C1 L2 C2 105MHz 270nH 12pF 82nH 15pF 280MHz 5.0pF 33nH 6.0pF 82nH HFA3763 Pin Descriptions PIN SYMBOL DESCRIPTION 9 LPF_VCC 10 2V REF 11 LPF_BYP 12 LPF_TXI_In Low pass filter in phase (I) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. AC couple for analog input. 13 LPF_TXQ_In Low pass filter quadrature (Q) channel transmit input. Conventional or attenuated direct coupling is required for digital inputs. AC couple for analog input. 14 NC Connected internally for test purpose. Leave this pin floating. 15 NC Connected internally for test purpose. Leave this pin floating. 16 LPF_Sel1 17 LPF_Sel0 Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin. Stable 2V reference voltage output for external applications. Loading must be higher than 10kΩ. A bypass capacitor of at least 0.1µF is required. Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires 0.1µF decoupling capacitor. Digital control input pins. Selects four programmed cut off frequencies for the transmit channel. Tuning speed from one cutoff to another is less than 1µs. SEL1 LO LO SEL0 LO HI CUTOFF FREQUENCY 2.2MHz 4.4MHz SEL1 HI HI SEL0 LO HI CUTOFF FREQUENCY 8.8MHz 17.6MHz 18 LPF_Tune1 These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two pins (RTUNE) will fine tune the transmit filters. Refer to the tuning equation in the LPF AC specifications. 19 LPF_Tune0 20 TX D or A 22 LPF_TX_PE 23 LPF_TXQ- Negative output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40. 24 LPF_TXQ+ Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39. 25 LPF_TXI- Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the inverting input of the in phase Modulator (Mod_TXI-), pin 38. 26 LPF_TXI+ Positive output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the non inverting input of the in phase Modulator (Mod_TXI+), pin 37. 27 NC Connected internally for test purpose. Leave this pin floating. 28 NC Connected internally for test purpose. Leave this pin floating. 29 NC Connected internally for test purpose. Leave this pin floating. 30 NC Connected internally for test purpose. Leave this pin floating. 33 NC Connected internally for test purpose. Leave this pin floating. 34 NC Connected internally for test purpose. Leave this pin floating. 35 NC Connected internally for test purpose. Leave this pin floating. 36 NC Connected internally for test purpose. Leave this pin floating. 37 Mod_TXI+ In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXI+), pin 26. 38 Mod_TXI- In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXI-), pin 25. 39 Mod_TXQ+ Quadrature modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXQ+), pin 24. 40 Mod_TXQ- Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXQ-), pin 23. Selects the configuration of the Transmit baseband input for either Digital or Analog (500mVP-P max). Tie to a High for Analog and Ground for Digital inputs. Requires decoupling capacitor for analog and a simple direct coupled attenuator for digital inputs. Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High. 4-4 HFA3763 Pin Descriptions (Continued) PIN SYMBOL DESCRIPTION 41 Mod_TX_PE 42 Mod_TX_IF_Out 44 Mod_LO_In (2XLO) 45 Mod_VCC 46 Mod_LO_Out 47 Mod_VCC Modulator supply pin. Use high quality decoupling capacitors right at the pin. 48 MOD_BYP This pin must be connected to pin 49 and decoupled to gnd. (Note 1) 49 MOD_BYP This pin must be connected to pin 48. (Note 1) 50 LO_GND 55 IF_AGC_IN AC coupled input to the AGC amplifier. 57 AGC_VCC AGC supply pin supply pin. Use high quality decoupling capacitors right at the pin. 59 AGC_CTRL 61 AGC_VCC 63 AGC_PE 65 AGC_IF_OUT 67 AGC_VCC See Pinout GND Digital input control to enable the Modulator section. Enable logic level is High for transmit. Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 250Ω. Single ended local oscillator current input. Frequency of input signal must be twice the required modulator carrier LO frequency. Input current is optimum at 200µARMS. Input matching networks and filters can be designed for a wide range of power and impedances at this port. Typical input impedance is 130Ω.This pin requires AC coupling. NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy. Modulator supply pin. Use high quality decoupling capacitors right at the pin. Divide by 2 buffered output reference from “Mod_LO_in” input. Used for external applications where the modulating and demodulating carrier reference frequency is required. 50Ω single end driving capability. AC coupling is required. This output can be disabled by shorting to VCC or floating pin 50. When grounded, this pin enables the LO buffer (Mod_LO_Out). When open (NC) it disables the LO buffer. AGC control DC control voltage input requires external resistor to set scale factor. 10K for optimum temp. co. May require decoupling filtering capacitor. AGC supply pin supply pin. Use high quality decoupling capacitors right at the pin. Digital input control for the AGC amplifier. Enable logic level is High. AGC amplifier output. Output impedance of 250Ω. Need to be connected to VCC by an inductor with reactance well above 250Ω. AGC supply pin supply pin. Use high quality decoupling capacitors right at the pin. All remaining pins not listed above must be connected to a solid ground plane. NOTE: 1. If pin 50 is grounded, otherwise float. 4-5 HFA3763 Absolute Maximum Ratings TA = 25oC Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Package Power Dissipation at 70oC Plastic TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . . -65 ≤ TA ≤ 150 Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (TQFP - Lead Tips Only) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . -40oC ≤ TA ≤ 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Cascaded DC Electrical Specifications VCC = 4.5V to 5.5V, Unless Otherwise Specified (NOTE 2) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS Total Supply Current, TX Mode at 5.5V A Full - 80 106 mA Shutdown Current at 5.5V A Full - 0.8 1.0 mA All Digital Inputs VIH (TTL Threshold for All VCC) A Full 2.0 - VCC V All Digital Inputs VIL (TTL Threshold for All VCC) A Full -0.2 - 0.8 V High Level Input Current at 5.5V VCC for pin 16 with VIN = 2.4V A Full -200 -65 0 µA High Level Input Current at 5.5V VCC for pin 16 with VIN = 4.0V A Full -150 -30 0 µA Low Level Input Current at 5.5V VCC for pin 16 with VIN = 0.8V A Full -300 -95 0 µA High Level Input Current at 5.5V VCC for pins 17, 20, and 22 with VIN = 2.4V A Full 0 50 200 µA High Level Input Current at 5.5V VCC for pins 17, 20, and 22 with VIN = 4.0V A Full 0 80 300 µA Low Level Input Current at 5.5V VCC for pins 17, 20, and 22 with VIN = 0.8V A Full 0 15 150 µA High Level Input Current at 5.5V VCC for pins 41 and 63 with VIN = 2.4V A Full -20 1 20 µA High Level Input Current at 5.5V VCC for pin 41 with VIN = 4.0V A Full 0 110 300 µA High Level Input Current at 5.5V VCC for pin 63 with VIN = 4.0V A Full -20 1.5 20 µA Low Level Input Current at 5.5V VCC for pins 41 and 63 with VIN = 0.8V A Full -20 .1 20 µA Power Down/Up Switching Speed C 25 - 10 - µs Reference Voltage A Full 1.85 2.0 2.15 V Reference Voltage Variation Over Temperature B Full - 800 - µV/oC Reference Voltage Variation Over Supply Voltage B 25 - 1.6 - mV/V Reference Voltage Minimum Load Resistance C 25 10 - - kΩ PARAMETER NOTE: 2. A = Production Tested, B = Based on Characterization, C = By Design Cascaded AC Electrical Specifications, Modulator Performance VCC = 4.5V to 5.5V (NOTE 3) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS IF Modulator Output Power (Note 6) A 25 -4 1 6 dBm IF Modulator I/Q Amplitude Balance (Note 4) B Full -1.0 0 +1.0 dB IF Modulator I/Q Phase Balance (Note 4) B Full -4.0 0 +4.0 Degrees PARAMETER 4-6 HFA3763 Cascaded AC Electrical Specifications, Modulator Performance VCC = 4.5V to 5.5V (Continued) (NOTE 3) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS A Full 25 41 - dBc A 25 33 41 - dBc IF Modulator Side Band Suppression at 400MHz C 25 28 - - dBc IF Mod Carrier Suppression (LO Buffer Enabled) (Note 5) C 25 28 30 - dBc IF Mod Carrier Suppression (LO Buffer Disabled) (Note 5) A 25 28 38 - dBc IF Modulator I/Q 3dB Cutoff SEL0/1 = 2.2MHz B 25 1.98 2.2 2.42 MHz IF Modulator I/Q 3dB Cutoff SEL0/1 = 4.4MHz B 25 3.96 4.4 4.84 MHz IF Modulator I/Q 3dB Cutoff SEL0/1 = 8.8MHz B 25 7.92 8.8 9.68 MHz IF Modulator I/Q 3dB Cutoff SEL0/1 = 17.6MHz B 25 15.84 17.6 19.36 MHz PARAMETER IF Modulator Side Band Suppression at 105MHz (Note 5) NOTES: 3. A = Production Tested, B = Based on Characterization, C = By Design 4. Data is characterized by DC levels applied to MOD TXI and Q pins for 4 quadrants with LO output as reference or indirectly by the SSB characteristics. 5. Analog mode with an input frequency of 1MHz and an input amplitude of 400mVP-P and a 2.2MHz lowpass filter cutoff with VAGC = 1.25V. 6. Data is characterized with VAGC = 1V with an input of 400mVP-P at LPF_TXI_IN and LPF_TXQ_IN. DC/AC Electrical Specifications AGC/Attenuator, Individual Performance PARAMETER (NOTE 7) TEST LEVEL VCC = 4.5V to 5.5V Unless Otherwise Specified TEMP (oC) MIN TYP MAX UNITS DC ELECTRICAL SPECIFICATIONS AGC ATTENUATOR INDIVIDUAL PERFORMANCE AGC Scale Factor at 100MHz at 3dB A 25 36 45 54 dB/V AGC Linearity: Max-to-Min Scale Factor at 0dB to 45dB AGC with External 10kΩ A 25 0.9:1 2:1 3:1 - AGC Control Input for 45dB Max Attenuation with External 10kΩ A 25 1.7 2.0 2.5 V AGC Control Input for -3 dB from Minimum Attenuation (Gain Approx. = 6dB) with External 10kΩ A 25 1.0 1.2 1.4 V AGC Input Bias Current with External 10kΩ at -45 dB A Full - - 120 µA AC ELECTRICAL SPECIFICATIONS AGC ATTENUATOR INDIVIDUAL PERFORMANCE Frequency Range B 25 10 - 400 MHz Power Gain at min AGC at 100MHz VAGC = 1.0V C 25 - 9.0 - dB Power Gain Temperature Coefficient VAGC = 1.0V B 25 - +0.013 - dB/deg Output P1dB at Minimum AGC, 100MHz VAGC = 1.0V B 25 - 8.0 - dBm Output IP3 at Minimum AGC, 100MHz VAGC = 1.0V B 25 - 17.5 - dBm AGC/Attenuator Range A 25 42 45 - dB AGC Settling Time to 1dB, 0dB to -40dB C 25 - - 10 µs Output Impedance C 25 - 250 - Ω Input Impedance C 25 - 250 - Ω Gain Flatness, 20MHz Bandwidth C 25 - 0.02 - dB Phase Shift vs AGC at 100MHz C 25 - -0.045 - deg/dB Power Down/Up Switching Speed (Note 3) C 25 - - 10 µs NOTE: 7. A = Production Tested, B = Based on Characterization, C = By Design 4-7 HFA3763 AC Electrical Specifications, I/Q Up Converter and LO Individual Performance VCC = 4.5V to 5.5V Unless Otherwise Specified (NOTE 8) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS 2XLO Input Frequency Range (2 X Input Range) B 25 20 - 800 MHz 2XLO Input Current Range C 25 50 200 300 µARMS 2XLO Input Impedance C 25 - 130 - Ω Buffered LO Output Voltage, Single Ended A 25 80 100 - mVP-P Buffered LO Output Impedance C 25 - 50 - Ω Quadrature IF Modulator Output Frequency Range B 25 10 - 400 MHz IF Modulator I/Q Input Frequency Range C 25 - - 30 MHz IF Modulator Differential I/Q Max Input Voltage C 25 - 2.25 - VP-P IF Modulator Differential I/Q Input Impedance C 25 - 4 - kΩ IF Modulator Differential Input Capacitance C 25 - 0.5 - pF IF Modulator I/Q Amplitude Balance B Full -1.0 - 1.0 dB IF Modulator I/Q Phase Balance at 105MHz B Full -4 - 4 Degrees IF Modulator I/Q Phase Balance at 400MHz C 25 -4 - 4 Degrees IF Modulator Carrier Suppression (LO Buffer Enabled) C 25 28 30 - dBc IF Modulator Carrier Suppression (LO Buffer Disabled) A 25 28 38 - dBc IF Modulator SSB Sideband Suppression at 105MHz A Full 25 41 - dBc A 25 33 41 - dBc IF Modulator SSB Sideband Suppression at 400MHz C 25 28 - - dBc IF Output Level Compression Point C 25 - 1.0 - VP-P IF Modulator Intermodulation Suppression B 25 26 - - dBc PARAMETER NOTE: 8. A = Production Tested, B = Based on Characterization, C = By Design AC Electrical Specifications, TX Buffer Individual Performance VCC = 4.5V to 5.5V Unless Otherwise Specified (NOTE 9) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS TX LPF Buffer Analog Input Range A 25 - 500 - mVP-P TX LPF Buffer Analog/Digital Input Impedance C 25 10 12.5 - kΩ PARAMETER NOTE: 9. A = Production Tested, B = Based on Characterization, C = By Design AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance VCC = 4.5V to 5.5V Unless Otherwise Specified (NOTE 10) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS TX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 0 B 25 1.98 2.20 2.42 MHz TX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 0 B 25 3.96 4.40 4.84 MHz TX LPF 3dB Bandwidth, Sel0 = 0, Sel1 = 1 B 25 7.92 8.80 9.68 MHz TX LPF 3dB Bandwidth, Sel0 = 1, Sel1 = 1 B 25 15.84 17.60 19.36 MHz TX LPF Sel0, Sel1 Tuning Speed B 25 - - 1 µs PARAMETER 4-8 HFA3763 AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance VCC = 4.5V to 5.5V Unless Otherwise Specified (Continued) (NOTE 10) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS TX LPF 3dB Bandwidth Tuning B 25 -20 - +20 % LPF Tune Nominal Resistance B 25 - 787 - Ω TX/RX LPF Total Harmonic Distortion B 25 - 1 - % LPF Output Impedance, Single Ended C 25 - 50 - Ω PARAMETER NOTE: 10. A = Production Tested, B = Based on Characterization, C = By Design TABLE 1. LOW PASS FILTER PROGRAMING AND TUNING INFORMATION MODE LPF SEL1 LPF SEL0 f3dB (NOMINAL RTUNE) BW0 0 0 2.2MHz BW1 0 1 4.4MHz BW2 1 0 8.8MHz BW3 1 1 17.6MHz PERCENT OF NOMINAL FREQUENCY f 3dBNOMINAL∗ 787 f TUNED 3dB = ---------------------------------------------------R TUNE +20% -20% -30 -25 -20 -15 -10 -5 0 +5 +10 +15 [(787 - RTUNE)/RTUNE] * 100% FREQUENCY RTUNE 20% Low 984Ω Nominal 787Ω 20% High 656Ω FIGURE 1. TYPICAL f3dB vs RTUNE 4-9 +20 +25 +30 HFA3763 Thin Plastic Quad Flatpack Packages (LQFP) Q80.14x14 (JEDEC MS-026BEC ISSUE C) D 80 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE D1 -D- -B- -AE E1 e PIN 1 SEATING A PLANE -H- 0.08 0.003 -C- INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.062 - 1.60 - A1 0.002 0.005 0.05 0.15 - A2 0.054 0.057 1.35 1.45 - b 0.009 0.014 0.22 0.38 6 b1 0.009 0.012 0.22 0.33 - D 0.626 0.634 15.90 16.10 3 D1 0.547 0.555 13.90 14.10 4, 5 E 0.626 0.634 15.90 16.10 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.018 0.029 0.45 0.75 N 80 80 e 0.026 BSC 0.65 BSC 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 0.13 A-B S 0.005 M C D S b 11o-13o 0.020 0.008 MIN b1 0o MIN A2 A1 GAGE PLANE 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 0.09/0.16 0.004/0.006 7. “N” is the number of terminal positions. BASE METAL WITH PLATING L 0o-7o 4. Dimensions D1 and E1 to be determined at datum plane -H- . 11o-13o 0.25 0.010 0.09/0.20 0.004/0.008 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 4-10 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029