HFA3726 Data Sheet November 1999 400MHz Quadrature IF Modulator/Demodulator File Number 4310.3 Features • Integrates all IF Transmit and Receive Functions The HFA3726 is a highly integrated baseband converter for quadrature modulation applications. It features all the necessary functionality for baseband modulation and demodulation of I and Q signals. It has a two stage integrated limiting IF amplifier with 84dB of gain and a built in Receive Signal Strength Indicator (RSSI). “I” and “Q” Baseband antialiasing and shaping filters are integrated in this design. In addition, these filters are continuously tunable over a ±10% frequency range via one external resistor. The modulator channel receives digital I and Q data for processing. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency of modulation/demodulation. A selectable buffered divide by 2 LO output and a stable reference voltage is provided for convenience of the user. The device is housed in a thin 80 lead TQFP package well suited for PCMCIA board applications. ™ • Broad Frequency Range . . . . . . . . . . . 10MHz to 400MHz • 5th Order Low Pass Filter. . . . . . . . . . . . . . . . . . . .7.7MHz • 400MHz Limiting IF Gain Strip with RSSI. . . . . . . . . .84dB • Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm • Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . . 1µs • Power Management/Standby Mode • Single Supply 2.7V to 5.5V Operation Applications • Systems Targeting IEEE 802.11 Standard • TDD Quadrature-Modulated Communication Systems • Wireless Local Area Networks • PCMCIA Wireless Transceivers • ISM Systems Ordering Information • TDMA Packet Protocol Radios TEMP. PART NUMBER RANGE (oC) PACKAGE • PCS/Wireless PBX PKG. NO. • Wireless Local Loop HFA3726IN -40 to 85 80 Ld TQFP Q80.14x14 HFA3726IN96 -40 to 85 80 Ld TQFP Tape and Reel LIM1_IN IF LPF_TUNE_1 LPF_TUNE_0 LPF_RX_I LPF_RX_Q MOD_RX_I MOD_RX_Q LIM1_OUT LIM2_IN LIM2_OUT MOD_IF_IN Simplified Block Diagram IF LPF_RXI_OUT RSSI1 RSSI2 LPF_RXQ _OUT I MOD_LO_IN ÷2 MOD_LO_OUT LO_GND LPF_TXI_IN Q ∑ MOD_TX_IF_OUT M U X M U X 0o/90o LPF_TXQ_IN 1 LPF_TX_I LPF_TX_Q MOD_TX_I MOD_TX_Q 2V REF 2V REF CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. HFA3726 Pinout LIM1_RSSI RSSI_RL1 GND LIM1_OUT+ LIM1_OUTLIM1_VCC LIM1_PE GND GND GND GND GND GND GND GND GND LIM2_BYPLIM2_INLIM2_IN+ LIM2_BYP+ 80 LEAD TQFP TOP VIEW 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 LIM1_BYP+ LIM1_IN+ LIM1_INLIM1_BYPGND GND GND GND LPF_VCC 2V REF LPF_BYP LPF_TXI_IN LPF_TXQ_IN LPF_RXI_OUT LPF_RXQ_OUT GND GND LPF_Tune1 LPF_Tune0 GND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 MOD_TXIMOD_TXQ+ MOD_TXQ- LPF_RX_PE LPF_TX_PE LPF_TXQLPF_TXQ+ LPF_TXILPF_TXI+ LPF_RXQLPF_RXQ+ LPF_RXILPF_RXI+ GND GND MOD_RXI+ MOD_RXIMOD_RXQ+ MOD_RXQMOD_TXI+ 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LIM2_RSSI RSSI_RL2 GND LIM2_OUT+ LIM2_OUTLIM2_VCC LIM2_PE GND GND GND LO_GND MOD_IF_INMOD IF_IN+ MOD_VCC MOD_LO_OUT MOD_VCC MOD_LO_IN MOD_RX_PE MOD_TX_IF_OUT MOD_TX_PE HFA3726 LPF_TXQ_IN MUX_LPF LPF_TXI_IN LPF_RXI_OUT LPF_RXQ_OUT Block Diagram LPF_TUNE0 MUX LPF_TUNE1 LPF_RX PE LPF_TX_Q LPF_TX_Q + LPF_TX_I LPF_TX_I + Q I LPF_RX I LPF_RX I + LPF_RX Q + LPF_RX Q - MUX MOD_RX Q MOD_RX Q + MOD TX I + MOD TX I MOD TX Q + MOD TX Q - MOD_TX_PE 0o/ DOWN CONV 90o MOD_RX I MOD_RX I + MOD_RX PE LPF_TX_PE ∑ ÷2 MOD_IF_IN + MOD_IF_IN LIM2_OUT LIM2_OUT + IF LIM2_PE NOTE: VCC , GND and Bypass capacitors not shown. 3 2V REF LPF_BYP MOD_TX IF_OUT 50Ω MOD_LO_OUT MOD_LO_IN RSSI IF IN (2XLO) 1.25V VCC LO_GND RSSI_RL2 LIM2_RSSI SAW LIM1_INLIM1_RSSI RSSI_RL1 LIM1_IN+ IF LIM1_PE IF LIMITERS LIM1_OUT LIM1_OUT + UP CONVERTER LIM2_IN+ LIM2_IN- 2V REF HFA3726 Pin Description PIN SYMBOL DESCRIPTION 1 LIM1_BYP+ DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. 2 LIM1_In+ Non inverting analog input of Limiter amplifier 1. 3 LIM1_In- Inverting input of Limiter amplifier 1. 4 LIM1_BYP- 5, 6, 7, 8 GND 9 LPF_VCC 10 2V REF Stable 2V reference voltage output for external applications. Loading must be higher than 10kΩ. A bypass capacitor of at least 0.1µF is required. 11 LPF_BYP Internal reference bypass pin. This is the common voltage (VCM) used for the LPF digital thresholds. Requires 0.1µF decoupling capacitor. 12 LPF_TXI_In Low pass filter in phase (I) channel transmit digital input. (Note 1) 13 LPF_TXQ_In Low pass filter quadrature (Q) channel transmit digital input. (Note 1) 14 LPF_RXI_Out Low pass filter in phase (I) channel receive output. Requires AC coupling. (Note 2) 15 LPF_RXQ_Out Low pass filter quadrature (Q) channel receive output. Requires AC coupling. (Note 2) 16 GND Ground. Connect to a solid ground plane. 17 GND Ground. Connect to a solid ground plane. 18 LPF_Tune1 19 LPF_Tune0 20 GND 21 LPF_RX_PE Digital input control pin to enable the LPF receive mode of operation. Enable logic level is High. 22 LPF_TX_PE Digital input control pin to enable the LPF transmit mode of operation. Enable logic level is High. 23 LPF_TXQ- Negative output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the inverting input of the quadrature Modulator (Mod_TXQ-), pin 40. 24 LPF_TXQ+ Positive output of the transmit Low pass filter, quadrature channel. AC coupling is required. Normally connects to the non inverting input of the quadrature Modulator (Mod_TXQ+), pin 39. 25 LPF_TXI- Negative output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the inverting input of the in phase Modulator (Mod_TXI-), pin 38. 26 LPF_TXI+ Positive output of the transmit Low pass filter, in phase channel. AC coupling is required. Normally connects to the non inverting input of the in phase Modulator (Mod_TXI+), pin 37. 27 LPF_RXQ- Low pass filter inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the negative output of the quadrature demodulator (Mod_RXQ-), pin 36. 28 LPF_RXQ+ Low pass filter non inverting input of the receive quadrature channel. AC coupling is required. This input is normally coupled to the positive output of the quadrature demodulator (Mod_RXQ+), pin 35. 29 LPF_RXI- Low pass filter inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the negative output of the in phase demodulator (Mod_RXI-), pin 34. 30 LPF_RXI+ Low pass filter non inverting input of the receive in phase channel. AC coupling is required. This input is normally coupled to the positive output of the in phase demodulator (Mod_RXI-), pin 33. 31, 32 GND 33 Mod_RXI+ In phase demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXI+), pin 30. 34 Mod_RXI- In phase demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXI-), pin 29. DC feedback pin for Limiter amplifier 1. Requires good decoupling and minimum wire length to a solid signal ground. Ground. Connect to a solid ground plane. Supply pin for the Low pass filter. Use high quality decoupling capacitors right at the pin. These two pins are used to fine tune the Low pass filter cutoff frequency. A resistor connected between the two pins (RTUNE) will fine tune both transmit and receive filters. Refer to the tuning equation in the LPF AC specifications. Ground. Connect to a solid ground plane. Ground. Connect to a solid ground plane. 4 HFA3726 Pin Description (Continued) PIN SYMBOL DESCRIPTION 35 Mod_RXQ+ Quadrature demodulator positive output. AC coupling is required. Normally connects to the non inverting input of the Low pass filter (LPF_RXQ+), pin 28. 36 Mod_RXQ- Quadrature demodulator negative output. AC coupling is required. Normally connects to the inverting input of the Low pass filter (LPF_RXQ+), pin 27. 37 Mod_TXI+ In phase modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXI+), pin 26. 38 Mod_TXI- In phase modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXI-), pin 25. 39 Mod_TXQ+ Quadrature modulator non inverting input. AC coupling is required. This input is normally coupled to the Low pass filter positive output (LPF_TXQ+), pin 24. 40 Mod_TXQ- Quadrature modulator inverting input. AC coupling is required. This input is normally coupled to the Low pass filter negative output (LPF_TXQ-), pin 23. 41 Mod_TX_PE 42 Mod_TX_IF_Out 43 Mod_RX_PE Digital input control to enable the demodulator section. Enable logic level is High for receive. 44 Mod_LO_In (2XLO) Single ended local oscillator current input. Frequency of input signal must be twice the required modulator carrier and demodulator LO frequency. Input current is optimum at 200µARMS. Input matching networks and filters can be designed for a wide range of power and impedances at this port. Typical input impedance is 130Ω. This pin requires AC coupling. (Note 3) Digital input control to enable the Modulator section. Enable logic level is High for transmit. Modulator open collector output, single ended. Termination resistor to VCC with a typical value of 316Ω. NOTE: High second harmonic content input waveforms may degrade I/Q phase accuracy. 45 Mod_VCC Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin. 46 Mod_LO_Out 47 Mod_VCC 48 Mod_IF_In+ Demodulator non inverting input. Requires AC coupling. 49 Mod_IF In- Demodulator inverting input. Requires AC coupling. 50 LO_GND 51, 52, 53 GND 54 LIM2_PE 55 LIM2_VCC Limiter amplifier 2 supply pin. Use high quality decoupling capacitors right at the pin. 56 LIM2_Out- Positive output of limiter amplifier 2. Requires AC coupling. 57 LIM2_Out+ Negative output of limiter amplifier 2. Requires AC coupling. 58 GND 59 RSSI_RL2 Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and maintain temperature and process variation to a minimum. 60 LIM2_RSSI Current output of RSSI for the limiter amplifier 2. Connect in parallel with the RSSI output of the amplifier limiter 1 for cascaded response. 61 LIM2_BYP+ DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. 62 LIM2_In+ Non inverting analog input of Limiter amplifier 2. 63 LIM2_In- Inverting input of Limiter amplifier 2. 64 LIM2_BYP- Divide by 2 buffered output reference from “Mod_LO_in” input. Used for external applications where the modulating and demodulating carrier reference frequency is required. 50Ω single end driving capability.This output can be disabled by use of pin 50. AC coupling is required, otherwise tie to VCC. Modulator/Demodulator supply pin. Use high quality decoupling capacitors right at the pin. When grounded, this pin enables the LO buffer (Mod_LO_Out). When open (NC) it disables the LO buffer. Ground. Connect to a solid ground plane. Digital input control to enable the limiter amplifier 2. Enable logic level is High. Ground. Connect to a solid ground plane. DC feedback pin for Limiter amplifier 2. Requires good decoupling and minimum wire length to a solid signal ground. 5 HFA3726 Pin Description (Continued) PIN SYMBOL DESCRIPTION 65, 66, 67, 68, 69, 70, 71, 72, 73 GND 74 LIM1_PE 75 LIM1_VCC Limiter amplifier 1 supply pin. Use high quality decoupling capacitors right at the pin. 76 LIM1_Out- Negative output of limiter amplifier 1. Requires AC coupling. 77 LIM1_Out+ Positive output of limiter amplifier 1. Requires AC coupling. 78 GND 79 RSSI_RL1 Load resistor to ground. Nominal value is 6kΩ. This load is used to terminate the LIM RSSI current output and maintain temperature and process variation to a minimum. 80 LIM1_RSSI Current output of RSSI for the limiter amplifier 1. Connect in parallel with the RSSI output of the amplifier limiter 2 for cascaded response. Ground. Connect to a solid ground plane. Digital input control to enable the limiter amplifier 1. Enable logic level is High. Ground. Connect to a solid ground plane. NOTES: 1. The HFA3726 generates a lower side band signal when the “I” input leads the “Q” input by 90 degrees. 2. For a reference LO frequency higher than a CW IF signal input, the “I” channel leads the “Q” channel by 90 degrees. 3. The in-phase reference LO transitions occur at the rising edges of the 2XLO signal. Quadrature LO transitions occur at the falling edges. 180 degrees phase ambiguity is expected for carrier locked systems without differential encoding. TABLE 1. POWER MANAGEMENT TRANSMIT RECEIVE POWER DOWN LIM1_PE 0 1 0 LIM2_PE 0 1 0 LPF_RX_PE 0 1 0 MOD_RX_PE 0 1 0 MOD_TX_PE 1 0 0 LPF_TX_PE 1 0 0 6 HFA3726 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Thermal Resistance (Typical, Note 4) θJA (oC/W) Plastic TQFP Package . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Lead Temperature (Soldering 10s at Lead Tips Only) . . . . . . . . . . . . . . . . . . . .300oC Maximum Storage Temperature Range . . . . . . . -65oC ≤ TA ≤ 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Package Power Dissipation at 70oC Plastic TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.1W Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . -40oC ≤ TA ≤ 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on an low effective thermal conductivity test board in free air. See Technical Brief 379 for details. DC Electrical Specifications Full Power Supply Range, Unless Otherwise Specified SYMBOL (NOTE 5) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS Total Supply Current, RX Mode at 5.5V RXICC A Full - 70 105 mA Total Supply Current, TX Mode at 5.5V TXICC A Full - 60 80 mA Shutdown Current at 5.5V ICCOFF A Full - 0.8 2 mA All Digital Inputs VIH (TTL Threshold for All VCC) VIH A Full 2.0 - VCC V All Digital Inputs VIL (TTL Threshold for All VCC) VIL A Full -0.2 - 0.8 V High Level Input Current at 2.7V VCC, VIN = 2.4V ihi A 25 - - 80 µA High Level Input Current at 5.5V VCC, VIN = 4.0V ihh A 25 - - 400 µA Iil A 25 -20 - +20 µA PEt B 25 - 2 - µs Power Down/Up Switching Speed (See Figure 22) PEtpd B 25 - 10 - µs Reference Voltage VREF A Full 1.87 2.0 2.13 V Reference Voltage Variation Over Temperature VREFT B 25 - 800 - µV/oC Reference Voltage Variation Over Supply Voltage VREFV B 25 - 1.6 - mV/V Reference Voltage Minimum Load Resistance VREFRL C 25 10 - − kΩ PARAMETER Low Level Input Current, VIN = 0.8V RX to TX/TX to RX Switching Speed (See Figure 22) NOTE: 5. A = Production Tested, B = Based on Characterization, C = By Design. AC Electrical Specifications, Demodulator Performance Application Targeting IEEE 802.11, VCC = 3V, Figure 22 Unless Otherwise Specified SYMBOL (NOTE 6) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS IF Demodulator 3dB Limiting Sensitivity (Note 7) D3dB B 25 - -84 - dBm IF Demodulator I and Q Outputs Voltage Swing DIQsw A Full 300 450 650 mVP-P IF Demodulator I and Q Channels Output Drive Capability (ZOUT = 50Ω) Cmax = 10pF Doutz C 25 1.2 2 - kΩ IF Demodulator I/Q Amplitude Balance, IFin = -70dBm at 50Ω Dabal A Full -1.0 0 +1.0 dB IF Demodulator I/Q Phase Balance, IFin = -70dBm at 50Ω Dphbal A Full -4.0 0 +4.0 Degrees IF Demodulator Output Variation at -70dBm to 0dBm Input Dovar A Full -0.5 0 +0.5 dB IF Demodulator RSSI Noise Induced Offset Voltage (Note 8) Drssio B 25 - 580 - mVDC PARAMETER 7 HFA3726 AC Electrical Specifications, Demodulator Performance Application Targeting IEEE 802.11, VCC = 3V, Figure 22 Unless Otherwise Specified (Continued) SYMBOL (NOTE 6) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS Drssis B 25 - 15 - mV/dB IF Demodulator RSSI DC Level, Pin = -30dBm (Note 9) Drssi_30 A Full 0.904 1.46 1.71 Vdc IF Demodulator RSSI DC Level, Pin = -70dBm (Note 9) Drssi_70 A Full 0.456 0.86 0.99 Vdc IF Demodulator RSSI Linear Dynamic Range (Note 10) Drssidr B 25 - 60 - dB IF Demodulator RSSI Rise and Fall Time from -30dBm to -50dBm Input at 100pF Load Drssitr B 25 - 0.3 - µs PARAMETER IF Demodulator RSSI Voltage Output Slope (Note 9) NOTES: 6. A = Production Tested, B = Based on Characterization, C = By Design 7. 2XLO input = 572MHz, measure IF input level required to drop the I and Q output at 6MHz by 3dB from a reference output generated at IF input = -30dBm (hard limiting). This is a noise limited case with a BW of 47MHz. Please refer to the Overall Device Description, IF limiter. 8. The residual DC voltage generated by the RSSI circuit due to a noise limited stage at the end of the chain with no IF input. IF port terminated into 50Ω. Please referred to the Overall Device Description, IF limiter. 9. Both limiter RSSI current outputs are summed by 2 on chip 6kΩ resistors in parallel. 10. Range is defined where the indicated received input strength by the RSSI is ±3dBm accurate. AC Electrical Specifications, Modulator Performance Application Targeting IEEE 802.11, VCC = 3V, Figure 22 Unless Otherwise Specified SYMBOL (NOTE 11) TEST LEVEL TEMP (oC) MIN TYP MAX UNITS IF Modulator I/Q Amplitude Balance (Note 12) Mabal B 25 -1.0 0 +1.0 dB IF Modulator I/Q Phase Balance (Note 12) Mphbal B 25 -4.0 0 +4.0 Degrees IF modulator SSB Output Power (Note 13) Mssbpw A Full -12 -7 -4 dBm IF Modulator Side Band Suppression (Note 13) Mssbss A Full 26 33 - dBc IF Mod Carrier Suppression (LO Buffer Enabled) (Note 13) Mssbcs A Full 28 30 - dBc IF Mod Carrier Suppression (LO Buffer Disabled) (Note 13) Mssbcs1 B 25 28 36 - dBc IF Modulator Output Noise Floor Moutn0 B 25 - -132 - dBm/Hz IF Modulator I/Q 3dB Cutoff (Note 14) Msel3f A Full 6.83 7.7 8.57 MHz IF Modulator Spread Spectrum Output Power (Note 15) Mdsspw B 25 -12 -7 -4 dBm IF Modulator Side Lobe to Main Lobe Ratio, LPF = 7.7MHz (Note 15) Mdsssl B 25 - 35 - dB PARAMETER NOTES: 11. A = Production Tested, B = Based on Characterization, C = By Design 12. Data is characterized by DC levels applied to MOD TXI and Q pins for 4 quadrants with LO output as reference or indirectly by the SSB characteristics. 13. Power at the fundamental SSB frequency of two 6MHz, 90 degrees apart square waves applied at TXI and TXQ inputs. Levels are 3.4VP-P 1.7V offset. 14. Cutoff frequency is specified for both modulator and demodulator as the filter bank is shared and multiplexed for Transmit and Receive. Data is characterized by observing the attenuation of the fundamental of a square wave digital input swept at each channel separately. The IF output is down converted by an external wideband mixer with a coherent LO input for each of quadrature signals separately. 15. Typical ratio characterization with RTUNE set to 7.7MHz. TXI and TXQ analog Inputs at two independent and aligned 11M chip/s, 223-1 sequence code signals. 8 HFA3726 Typical Performance Curves, Demodulator (Figure 22 Test Diagram) 10mA/DIV. 50mV/DIV. 90 25o -40o OUTPUT SWING (mVP-P) SUPPLY CURRENT (mA) 85o 400 100 VCC = 3V 10 4.0 VCC 5.5 -100 FIGURE 1. DEMODULATOR SUPPLY CURRENT vs VCC AND TEMPERATURE 40mV/DIV. 700 OUTPUT SWING (mVP-P) -40o 500 4.0 VCC -40o 4.0 VCC 5.5 FIGURE 4. CASCADED LIMITER -3dB INPUT SENSITIVITY RESPONSE vs VCC AND TEMPERATURE 0.2o/DIV. +1o 0.1dB/DIV. AMPLITUDE BALANCE VARIATION PHASE BALANCE VARIATION 0 85o 25o -85 -90 2.5 5.5 FIGURE 3. DEMOD I/Q OUTPUT SWING vs VCC AND TEMPERATURE 0o -60 -40 -20 INPUT POWER (dBm INTO 50Ω) 1dBm/DIV. -80 85o 25o 300 2.5 -80 FIGURE 2. DEMODULATOR I/Q OUTPUT SWING vs INPUT POWER -3dB SENSITIVITY (dBm INTO 50Ω) 2.5 EXPECTED VARIATION WINDOW vs VCC +0.4dB 0.0dB EXPECTED VARIATION WINDOW vs VCC -0.4dB -1o 2.5 4.0 VCC 5.5 FIGURE 5. DEMOD I/Q PHASE BALANCE VARIATION vs VCC 9 2.5 4.0 VCC 5.5 FIGURE 6. DEMOD I/Q AMPLITUDE BALANCE VARIATION vs VCC HFA3726 Typical Performance Curves, Demodulator (Figure 22 Test Diagram) 0.4dB/DIV. (Continued) 0.1dB/DIV. +2o AMPLITUDE BALANCE VARIATION PHASE BALANCE VARIATION +0.4dB EXPECTED VARIATION 0o WINDOW vs TEMP -2o -60 -40 -20 0 20 40 TEMPERATURE 80 60 EXPECTED VARIATION 0.0dB -0.4dB -60 100 WINDOW vs TEMP -40 -20 0 20 40 60 100 80 TEMPERATURE FIGURE 7. DEMOD I/Q PHASE BALANCE VARIATION vs TEMPERATURE FIGURE 8. DEMOD I/Q AMPLITUDE BALANCE VARIATION vs TEMPERATURE 100mV/DIV. 100mV/DIV. 1.5V RSSI DC LEVEL 1.0V 0.5V -100 -80 -40 -20 -60 INPUT POWER (dBm INTO 50Ω) 85o 25o -40o 1.0V IF INPUT = -50dBM VCC = 3V 0.6V 2.5 0 FIGURE 9. DEMOD RSSI DC LEVEL vs INPUT POWER 4.0 VCC FIGURE 10. DEMOD RSSI DC LEVEL vs VCC AND TEMPERATURE 100mV/DIV. 900mV 85o 25o -40o DC OFFSET RSSI DC LEVEL 1.4V 500mV 100mV 2.5 4.0 VCC 5.5 FIGURE 11. DEMODULATOR RSSI DC OFFSET vs VCC AND TEMPERATURE 10 5.5 HFA3726 Typical Performance Curves, Modulator (Figure 23 Test Diagram) 10mA/DIV. 10dB/DIV. -7 SUPPLY CURRENT 90mA 85o 25o -40o 10mA 4.0 VCC 5.5 BW = 100kHz VBW = 30kHz FIGURE 12. MODULATOR SUPPLY CURRENT vs VCC AND TEMPERATURE 0.5dB/DIV. -5 OUTPUT POWER (dBm AT 50Ω) -40o 0dB -10 4.0 VCC -5dB 2.5 5.5 FIGURE 14. MODULATOR SSB OUTPUT POWER vs VCC AND TEMPERATURE 286MHz EXPECTED VARIATION WINDOW 5.5 4.0 VCC FIGURE 15. MODULATOR SSB SIDE BAND SUPPRESSION VARIATION vs VCC AND TEMPERATURE 0.5dB/DIV. -13 LO OUTPUT POWER (dBm AT 50Ω) SIDE BAND SUPPRESSION VARIATION FROM NOMINAL 1dB/DIV. +5dB 0dB 280MHz FREQUENCY 1dB/DIV. +5dB 85o 25o 2.5 274MHz FIGURE 13. TYPICAL SSB MODULATOR RESPONSE (NOTE 13 ON AC ELECTRICAL SPECS, MODULATOR PERFORMANCE TABLE, LO BUFFER ENABLED) SIDE BAND SUPPRESSION VARIATION FROM NOMINAL 2.5 EXPECTED VARIATION WINDOW -5dB 2.5 4.0 VCC 5.5 FIGURE 16. MODULATOR LO LEAKAGE VARIATION vs VCC AND TEMPERATURE 11 85o 25o -15.5 -18 2.5 -40o 4.0 VCC 5.5 FIGURE 17. MODULATOR LO OUTPUT POWER (FUNDAMENTAL) vs VCC AND TEMPERATURE HFA3726 Typical Performance Curves, Modulator (Figure 23 Test Diagram) (Continued) PERCENT OF NOMINAL FREQUENCY 1dB/DIV. 0dB -3dB +10% -10% -15 1MHz 2MHz 10MHz 0 +5 +10 +15 FIGURE 19. LPF CUTOFF FREQUENCY vs RTUNE, VCC = 3V, TA = 25oC 2%/DIV. +10% -24dBm 10dB/DIV. PERCENT OF CUTOFF -5 ((900-RTUNE)/RTUNE) * 100% FIGURE 18. TYPICAL MODULATOR I/Q 3dB CUTOFF FREQUENCY CURVE 0% -10% -60 -10 -40 -20 0 20 40 TEMPERATURE 60 80 100 FIGURE 20. LPF CUTOFF FREQUENCY vs TEMPERATURE AND VCC (NOTE 14 ON AC ELECTRICAL SPECS, MODULATOR PERFORMANCE TABLE) 12 SPAN 50MHz BW = 100kHz VBW = 30kHz VIDEO AVERAGE 280MHz FIGURE 21. TYPICAL MODULATOR SPREAD SPECTRUM OUTPUT 11M CHIPS/s, QPSK. RTUNE = 900Ω HFA3726 Test Diagram (280MHz IF) VCC VCC 75 IF_IN 100p 2 56 77 3 57 100p 560 62 0.1 63 100p 100p 100p 100p 100p 1 80 4 45 PE 54 55 9 47 100p 76 0.1 VCC 0.1 10nH (NOTE 16) 100p PE 74 0.1 0.1 VCC (NOTE 17) 8 TO 40p 0.1 47p 56 100p 48 1K 33 0.001 30 34 49 29 HI_Z_PROBE 64 35 0.001 28 47p 100p 79 59 36 (NOTE 18) 15 0.001 27 0.001 44 LO_IN 18 56 1K 19 100p 10 46 2V REF LO_OUT 0.1 (NOTE 19) 0.1 37 0.001 26 VCC 38 47nH TX_IF_OUT 0.001 0.1 39 0.001 24 40 50 11 23 TXQ 0.001 TABLE 2. POWER MANAGEMENT 21 LIM1_PE 0 1 0 LIM2_PE 0 1 0 LPF_RX_PE 0 1 0 0 1 0 MOD_TX_PE 1 0 0 LPF_TX_PE 1 0 0 43 41 NOTES: 16. Input termination used to provide a 50Ω impedance. Limiter Noise Figure ≅ 9dB for this configuration. 17. Bandpass filter for 280MHz, BW = 47MHz, Q = 6. 18. Network shown for a typical -10dBm input at 50Ω. 19. Matching network from 250Ω to 50Ω at 280MHz. FIGURE 22. TEST DIAGRAM (280MHz IF) 13 22 LPF_TX_PE LPF_RX_PE POWER DOWN MOD_TX_PE RECEIVE MOD_RX_PE TRANSMIT TXI 12 25 50 316 42 3 TO 10p MOD_RX_PE RXQ_OUT HI_Z_PROBE 47p 220 RSSI RXI_OUT 0.001 60 61 100p 14 0.001 13 50 HFA3726 Typical Application Diagram (Targeting IEEE 802.11 Standard) VCC 55 100p 80 4 9 47 57 100p 47p 62 63 0.1 48 1K 56 34 49 61 100p 29 64 47p 100p 79 59 15 36 20 27 0.01 (NOTE 22) 18 CONVERTER HFA3624IA 900 LO_IN 56 19 (NOTE 24) 46 VCC 38 316 42 IF/RF 47nH TX_IF_OUT 25 TXI 0.1 40 11 23 TXQ 0.01 41 MOD_TX_PE 43 MOD_RX_PE 50 NOTES: 12 39 0.01 24 NC DUAL SYNTHESIZER HFA3524IA 0.1 0.01 100p (NOTE 23) 560MHz VCO (AUXILIARY) 10 2V REF 37 0.01 26 0.1 TOYOCOM TQS 432 RXQ_OUT 0.01 35 0.01 28 47p 220 44 VCO 14 0.01 60 100p 100p RXI_OUT 0.01 33 0.01 30 BASEBAND PROCESSOR HSP3824VI 76 1 45 PE 54 13 22 21 LPF_RX_PE 3 RSSI VCC 0.1 560 0.1 100p 100p 77 100p 260 2 0.1 100p 100p 100p VCC (NOTE 21) PE 74 0.1 LPF_TX_PE 75 (NOTE 20) 56n RF/IF TOYOCOM TQS 432 VCC 8 TO 40p 10nH 0.1 20. Input termination used to match a SAW filter. 21. Typical bandpass filter for 280MHz, BW = 47MHz, Q = 6. Can also be used if desired after the second stage. 22. Network shown for a typical -10dBm input at 50Ω. 23. Output termination used to match a SAW filter. 24. RTUNE value for a 7.7 MHz cutoff frequency setting. FIGURE 23. TYPICAL APPLICATION DIAGRAM (TARGETING IEEE 802.11 STANDARD) Overall Device Description The HFA3726 is a highly integrated baseband converter for half duplex wireless data applications. It features all the necessary blocks for baseband modulation and demodulation of “I” and “Q” quadrature multiplexing signals. It targets applications using all phase shift types of modulation (PSK) due to its hard limiting receiving front end. Four fully independent blocks adds flexibility for numerous applications covering a wide range of IF frequencies. A differential design architecture, device pin out and layout have been chosen to improve system RF properties such as common mode signal immunity (noise, crosstalk), reduce relevant parasitics, settling times and optimize dynamic range for low power requirements. Single power supply requirements from 2.7VDC to 5.5VDC makes the HFA3726 a good choice for portable transceiver designs. 14 The HFA3726 has a two stage integrated limiting IF amplifier with frequency response to 400MHz. These amplifiers exhibit a -84dBm, -3dB cascaded limiting sensitivity with a built in Receive Signal Strength Indicator (RSSI) covering 60dB of dynamic range with excellent linearity. An up conversion and down conversion pair of quadrature doubly balanced mixers are available for “I” and “Q” baseband IF processing. These converters are driven by an internal quadrature LO generator which has a broadband response with excellent quadrature properties. To achieve broadband operation, the Local Oscillator frequency input is required to be twice the desired frequency for modulation/demodulation. Duty cycle and signal purity requirements for the 2X LO input using this type of quadrature architecture are less restrictive HFA3726 for the HFA3726. Ground reference input signals as low as 15dBm and frequencies up to 900MHz (2XLO) can be used and tailored by the user. A buffered, divide by 2, LO single ended 50Ω selectable output is provided for convenience of PLL designs. The receive channel mixers “I” and “Q” quadrature outputs have a frequency response up to 30MHz for baseband signals and the transmit mixers are summed and amplified to a single ended open collector output with frequency response up to 400MHz. Multiplexed or half duplex baseband 5th order Butterworth low pass filters are also included in the design. The “I” and “Q” filters address applications requiring low pass and antialiasing filtering for external baseband threshold comparison or simple analog to digital conversion in the receive channel. During transmission, the filter is used for pulse shaping and control of spectral mask. These cut off frequency is selected for optimization of spectrum output responses for 11Mchips/s for spread spectrum applications (This rate can also be interpreted as symbol rates for conventional data transmission). External processing correlators in the receive channel as in the Intersil HSP3824 baseband converter, will bring the demodulation to lower effective data rates. As an example, the use of 11M chips/sec, 11 chip Barker code using the 7.7MHz low pass filter in a QPSK type of modulation scheme will bring a post processed effective data rate to 1M symbol/sec or 2M bits/sec. In addition, these filters are continuously tunable over a ±10% frequency range via one external resistor. This feature gives the user the ability to reshape the spectrum of a transmitted signal at the antenna port which takes into account any spectral regrowth along the transmitter chain. The modulator “I” and “Q” filter inputs accept digital signal level data for modulation and their phase and gain characteristics, including I/Q matching and group delay are well suitable for reliable data transmission. In the Receive mode and over the full input limiting dynamic range, both low pass filters outputs swing a 500mVP-P baseband signal. Each block has its own independent power enable control for power management and half duplex transmit/receive operation. A stable 2VDC output and a buffered band gap reference voltage are also provided for an external analog to digital conversion reference. Detailed Description (Refer to Block Diagram) IF Limiter Two independent limiting amplifiers are available in the HFA3726. Each one has a broadband response to 400MHz with 45dB of gain. The low frequency response is limited by external components because the device has no internal coupling capacitors. The differential limiting output swing with a 500Ω load is typically 200mVP-P at the fundamental frequency and is temperature stable. Both amplifiers are very stable within their passband and the cascaded performance also exhibits very good stability for 15 any input source impedance. Wide bandwidth SAW filters for spread spectrum applications or any desired source impedance filter implementation can be used for IF filtering before the cascaded amplifiers. The stability is remarkable for such an integrated solution. In fact, in many applications it is possible to remove the bypass pin capacitors with no degradation in stability. The cascaded -1dB and -3dB input limiting sensitivity have been characterized as -79dBm and 84dBm respectively, for a 50Ω single ended input at 280MHz and with a 47MHz bandwidth interstage bandpass LC filter (refer to Figure 22, Test Diagram). The input sensitivity is determined to a large extent by the bandwidth of the interstage filter and input source impedance. The noise figure for each stage has been characterized at 6dB for a 250Ω single end input impedance and 9dB for a 50Ω input impedance. These low noise figures combined with their high gain, eliminate the need for additional IF gain components. The use of interstage bandpass filtering is suggested to decrease the noise bandwidth of the signal driving the second stage. Excessive broadband noise energy amplified by the first stage will force the last limiting stage to lose some of its effective gain or “limit on the noise”. The use of interstage filters with narrower bandwidths will further improve the sensitivity of the cascaded limiter chain. The amplifier differential output impedance is 140Ω (70Ω single ended) which gives the user, the ability to design simple wide or narrow LC bandwidth interstage filters, or tailor a desired cascaded gain by using differential attenuators. The filter can be designed with a desired “Q” by using the followIng relationship: Q = Rp/X; where Rp is the parallel combination of 140Ω source resistance and the load (approximately 500Ω when using 560Ω termination as in Figure 22, Test Diagram), and X is the reactance of either L or C at the desired center frequency. Another independent feature of the limiting amplifier is its Receive Signal Strength Indicator (RSSI). A Log-Amp design was developed which resulted in a current output proportional to the input power. The RSSI output voltage is set by summing the two stages output currents, which are full wave rectified signals, to a common resistor to ground. This full wave rectified voltage can then be converted to DC by the use of a filter capacitor in parallel with the resistor (The larger the capacitor value, the less the AC ripple with the expense of longer RSSI settling times). This arrangement gives the user the flexibility to set the dynamic voltage swing to any desired level by an appropriate resistance choice. Each stage has an available on chip 6kΩ low temperature coefficient resistor to ground for current output termination that can be used for convenience. The RSSI gives a ±3dBm accurate indication of the receive input power. This accuracy is across a 60dB input dynamic range. The cascaded HFA3726 RSSI slope is of 5.0µa/dB. HFA3726 Quadrature Down Converter The quadrature down converter mixers are based in a Gilbert cell design. The input signal is routed to both mixers in parallel. With full balanced differential architecture, these mixers are driven by an accurate internal Local Oscillator (LO) chain as described later. Phase and gain accuracy of the output baseband signals are excellent and are a function of the combination of LO accuracy, balanced device design and layout characteristics. Mainly used for down conversion, its input frequency response exceeds 400MHz with a differential voltage gain of 2.5. With a differential input impedance of 1kΩ, the input compression point exceeds 2VP-P, which makes it suitable for use with the hard limiting output from the limiter amplifier chain or any low power external AGC application. The output frequency response is limited to 30MHz for “I” and “Q” baseband signals driving a 4kΩ differential load. The HFA3726 down conversion mixers can generate two 10MHz, 90o apart signals, with the use of proper low pass filtering, and exhibits ±4o and ±0.5dB of phase and amplitude match for a input CW IF signal of 400MHz and a 2XLO input of 780MHz. LO Quadrature Generator The In Phase and Quadrature reference signals are generated by a divide by two chain internal to the device which drives both the up and down conversion mixers. With a fully balanced approach, the phase relationship between the two quadrature signals is within 90o ±4o for a wide 20 to 400MHz frequency range. The reference signal input frequency needs to be twice the desired internal reference frequency. The ground referenced 2XLO input is current driven, which makes the input power requirement a function of external components that can be calculated assuming the input impedance of 130Ω. A typical input current value of 200µARMS is the only requirement for reliable LO generation. Figure 24 shows a typical 2XLO input network. Divide by two flip flop architectures for LO generation often require tight control of signal purity or duty cycles. The HFA3726 has an internal duty cycle compensation scheme which eases the requirements of tight controlled duty cycles. In addition, a 50Ω LO buffer is available to the user for PLL’s design reference. It substitutes a divide by two prescaler needed to bring the 2X LO frequency reference down. It is capable to drive 100mVP-P into 50Ω and its frequency response is from 20MHz to 400MHz corresponding to a 2XLO input frequency response of 40MHz to 800MHz. The LO buffer can be disabled by removing the ground connection to the pin LO GND. The quadrature generator is always enabled for either transmit or receive modes. 16 47p 50Ω I RMS = 200µA 220 44 56 EQUIVALENT 130Ω FIGURE 24. MOD LO IN (2XLO) EQUIVALENT CIRCUIT Quadrature Up Converter The Quadrature up converter mixers are also based on a doubly balanced Gilbert Cell design. “I” and “Q” Up converter signals are summed and buffered together through a single end open collector stage. As with the demodulators, both modulator mixers are driven from the same quadrature LO generator. It features a ±4o and 0.5dB of phase and amplitude balance up to 400MHz which are reflected into its SSB characteristics. For “I” and “Q” differential inputs of 500mVP-P, 90o apart, the carrier feedthrough or LO leakage is typical -30dBc into 250Ω with a sideband suppression of minimum 26dBc at 400MHz. Carrier feedthrough can be further improved by disabling the LO output port (please refer to pin#50 description) or using a DC bias network as in Figure 25. Featuring an output compression level of 1VP-P, the modulator output can generate a CW signal of typical 10dBm into 250Ω (158mVRMS) when differential DC inputs of 500mVP-P (equivalent to applying ±125mV ground referenced levels from the DC bias quiescent point of the device input) are applied to both “I” and “Q” inputs. Four quadrant phase shifts of the carrier output, like in Vector Modulator applications, can be set by proper choice of “I” and “Q” DC differential inputs, such that the square root of the sum of the squares of I and Q is constant. Although specified to drive a 250Ω load, the HFA3726 modulator open collector output enables user designed output matching networks to suit any application interface. The nominal AC current capability of this port is of 1.3mARMS, which is shared between the termination resistor and the load for I and Q differential DC inputs of 500mVP-P as explained above. (Use 70.7% of this AC capability for I and Q quadrature signals in case of SSB generation). Low Pass Filters These filters are implemented using a 5th order Butterworth architecture. They are multiplexed, i.e., the same filter bank is used for both transmit and receive modes. The filter block, in the transmit mode is set to accept digital (TTL threshold) levels inputs for “I” and “Q” signals with a frequency cutoff of 7.7MHz. An external resistor is used to fine tune the cut off frequencies for each setting within ±10% of the nominal value. This feature is often needed to fulfill requirements of spectral mask compliance at the antenna output. 37 38 MOD_TXQ - When in the receive mode, the filters exhibit a 0dB of gain with differential inputs and single ended outputs. MOD_TXI - MOD_TXI + The “I” and “Q” filter matching is within 2o for phase and 0.5dB for amplitude at the passband. Group delay characteristics follow closely a theoretical 5th order Butterworth design. MOD_TXQ + HFA3726 39 40 In the transmit mode, the digital ground referenced “I” and “Q” input signals are level shifted, shaped and buffered with constant driving differential outputs of 550mVP-P. 1K Coupling Capacitors 1K 1K 1K 50K Capacitor coupling is used to tie all HFA3726 blocks together. Special bias is used to maintain the DC levels on both ends of coupling pins (capacitors) when the device is changes from Transmitter to a Receiver and vice versa. The capacitance values must be chosen as a compromise to maintain proper frequency response and settling times (when the device is brought up from sleep mode or power down). 50K 43K 43K FIGURE 25. CARRIER NULL BIASING AC Electrical Specifications, IF Limiter, Single Stage Individual Performance Full Supply Range, TA = 25oC SYMBOL (NOTE 25) TEST LEVEL MIN TYP MAX UNITS IFf A - - 400 MHz IF Voltage Gain IFvG A 39 45 - dB IF Amp. Noise Figure at 250Ω Source Input IFNF B - - 7 dB IFinmax B - - 500 mVP-P IF Differential Limiting Output (1st Harmonic at 500Ω Load) IFVpp A 160 200 260 mVP-P IF Voltage Output Variation at -40dBm to -10dBm Input Range, 500Ω Load IFVppI A -0.5 - +0.5 dB RSSI Slope, Current Output IFRSSIsi B 5.7 - µA/dB RSSI Slope, Voltage Output at 6K Load IFRSSIv A 25 34 45 mV/dB RSSI Output Voltage Compliance IFRSSIvc B - - VCC-0.7 V RSSI DC Offset and Noise Induced Voltage at 6K Load IFRSSIof A 200 400 600 mV RSSI Absolute Accuracy, VIN = -40dBm IFRSSIa A -10 - +10 % RSSI Rise and Fall Time at 50pF Load (-20dBm to -40dBm Input) IFRSSIt B - - 1 µs PARAMETER IF Frequency Range (Min Limited by Bypass Capacitors) Maximum IF Input, Single Ended NOTE: 25. A = Production Tested, B = Based on Characterization, C = By Design TABLE 3. IF LIMITER S11, S22 PARAMETER FREQUENCY S11 (SINGLE ENDED) S22 (DIFFERENTIAL) 50MHz 0.96 -4.0o 100MHz 0.95 -8.0o 0.45 3.0o 200MHz 0.91 -17.0o 0.47 7.0o 300MHz 0.84 -26.0o 0.50 9.0o 400MHz 0.80 -33.0o 0.53 10.0o 17 0.45 0.0o HFA3726 AC Electrical Specifications, I/Q Down Converter Individual Performance Full Supply Range, TA = 25oC SYMBOL (NOTE 26) TEST LEVEL MIN TYP MAX UNITS QDf B 10 - 400 MHz QDIQf C - - 30 MHz Demodulator Voltage Gain at Frequency Range QDg A 6 8 9 dB Demodulator Differential Input Resistance Drin C - 1 - kΩ Demodulator Differential Input Capacitance Dcin C - 0.5 - pF Demodulator Differential Output Level at 4K Load, Input = 200mVP-P QDdo A 400 500 560 mVP-P Demodulator Amplitude Balance QDab A -0.5 - 0.5 dB Demodulator Phase Balance at 200MHz QDpb A -1.85 - 1.85 Degrees Demodulator Phase Balance at 400MHz QDPb1 B -4 - 4 Degrees QDoc B - 1.25 - VP-P PARAMETER Quadrature Demodulator Input Frequency Range Demodulator Baseband I/Q Frequency Range Demodulator Output Compression Voltage at 4K Load NOTE: 26. A = Production Tested, B = Based on Characterization, C = By Design AC Electrical Specifications, I/Q Up Converter and LO Individual Performance Full Supply Range, TA = 25oC SYMBOL (NOTE 27) TEST LEVEL MIN TYP MAX UNITS 2XLO Input Frequency Range (2 X Input Range) LOinf B 20 - 800 MHz 2XLO Input Current Range LOinz C 50 200 300 µARMS LOz C - 130 - Ω BLOout A 80 100 - mVP-P BLOoutZ C - 50 - Ω Quadrature IF Modulator Output Frequency Range QMLOf B 10 - 400 MHz IF Modulator I/Q Input Frequency Range QMIQf C - - 30 MHz IF Modulator Differential I/Q Max Input Voltage QMdi B - 2.25 - VP-P QMIQdz C - 4 - kΩ Mcin C - 0.5 - pF IF Modulator I/Q Amplitude Balance QMIQac A -0.5 - 0.5 dB IF Modulator I/Q Phase Balance at 200MHz QMIQpac A -2 - 2 Degrees IF Modulator I/Q Phase Balance at 400MHz QMIQp1 B -4 - 4 Degrees IF Modulator Output at SSB Into 50Ω, I and Q, 500mVP-P QMIFo A -22 - -10 dBm IF Modulator Carrier Suppression (LO Buffer Enabled) QMCs A 28 30 - dBc IF Modulator Carrier Suppression (LO Buffer Disabled) QMCs1 A 28 36 - dBc IF Modulator SSB Sideband Suppression at 200MHz QMSSBs A 28 - - dBc IF Modulator SSB Sideband Suppression at 400MHz QMSSBs B 26 - - dBc IF Output Level Compression Point QMIFP1 C - 1.0 - VP-P QMIMsup B 26 - - dBc PARAMETER 2XLO Input Impedance Buffered LO Output Voltage, Single Ended Buffered LO Output Impedance IF Modulator Differential I/Q Input Impedance IF Modulator Differential Input Capacitance IF Modulator Intermodulation Suppression NOTE: 27. A = Production Tested, B = Based on Characterization, C = By Design 18 HFA3726 TABLE 4. QUADRATURE MODULATOR S22 PARAMETER FREQUENCY S22 50MHz 0.99 -2.8o 100MHz 0.98 -6.5o 200MHz 0.96 -12.3o 300MHz 0.87 -25.1o 400MHz 0.82 -30.8o AC Electrical Specifications, TX Buffer Individual Performance Full Supply Range, TA = 25oC SYMBOL (NOTE 28) TEST LEVEL MIN TYP MAX UNITS TX LPF Buffer Serial Data Rate TXBrat A - 11 - MBPS TX LPF Buffer Digital Input Impedance LPFDz C 10 12.5 - kΩ PARAMETER NOTE: 28. A = Production Tested, B = Based on Characterization, C = By Design AC Electrical Specifications, RX/TX 5TH Order LPF Individual Performance Full Supply Range, TA = 25oC SYMBOL (NOTE 29) TEST LEVEL MIN TYP MAX UNITS LPF3dB2 A 6.93 7.7 8.47 MHz TX/RX LPF 3dB Bandwidth Tuning LPFtu A - ±10 - % LPF Tune Nominal Resistance LPFTr B - 900 - Ω RX LPF Voltage Gain LPFg A -1.5 0 +1.5 dB RX LPF Single Ended Output Voltage Swing at 2kΩ Load LPFRXar B - 500 - mVP-P RX LPF Differential Input Impedance LPFRXzi A 4 5 - kΩ TX LPF Differential Digital Output Voltage Swing at 4kΩ Load LPFTXo A 450 550 670 mVP-P TX/RX I/Q Channel Amplitude Match LPFIQm A -0.5 - 0.5 dB TX/RX I/Q Channel Phase Match LPFIQpm A -3 - 3 Degrees TX/RX LPF Total Harmonic Distortion LPFTHD B - 1 - % PARAMETER TX/RX LPF 3dB Bandwidth NOTE: 29. A = Production Tested, B = Based on Characterization, C = By Design TABLE 5. TYPICAL LPF TUNE RESISTANCE FREQUENCY RTUNE 10% Low 1059Ω Nominal 900Ω 10% High 783Ω (Note 30) NOTE: 30. Do not use an RTUNE value of less than 775Ω. 19 HFA3726 Typical Performance Curves, Individual Blocks 1dB/DIV. 0.25dB/DIV. 7dB 5.5V 85o 45dB 85o 25o -40o 2.7V 25o 6dB -40o 40dB 85o 25o -40o 10M 100M 500MHz FIGURE 26. SINGLE STAGE LIMITER GAIN vs FREQUENCY AND TEMPERATURE, VCC = 2.7V, 5.5V 20 5dB 2.5V 4V VCC 5.5V FIGURE 27. SINGLE STAGE LIMITER NOISE FIGURE vs VCC AND TEMPERATURE, RS = 250Ω, FREQUENCY = 400MHz HFA3726 Thin Plastic Quad Flatpack Packages (LQFP) Q80.14x14 (JEDEC MS-026BEC ISSUE C) D 80 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE D1 -D- -B- -AE E1 e PIN 1 SEATING A PLANE -H- 0.08 0.003 -C- INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.062 - 1.60 - A1 0.002 0.005 0.05 0.15 - A2 0.054 0.057 1.35 1.45 - b 0.009 0.014 0.22 0.38 6 b1 0.009 0.012 0.22 0.33 - D 0.626 0.634 15.90 16.10 3 D1 0.547 0.555 13.90 14.10 4, 5 E 0.626 0.634 15.90 16.10 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.018 0.029 0.45 0.75 N 80 80 e 0.026 BSC 0.65 BSC 7 Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 0.13 A-B S 0.005 M C D S b 11o-13o 0.020 0.008 MIN b1 0o MIN A2 A1 GAGE PLANE 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 0.09/0.16 0.004/0.006 7. “N” is the number of terminal positions. BASE METAL WITH PLATING L 0o-7o 4. Dimensions D1 and E1 to be determined at datum plane -H- . 11o-13o 0.25 0.010 0.09/0.20 0.004/0.008 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 21 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029