HANBit HMD8M32F4E 32Mbyte(8Mx32) EDO Mode 4K Ref. 100Pin SMM, 5V Design Part No. HMD8M32F4E GENERAL DESCRIPTION The HMD8M32F4E is a 8M x 32bit dynamic RAM high density memory module. The module consists of four CMOS 4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 100-pin, double-sided, FR-4-printed circuit board. A 0.1uF or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 100-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible. PIN ASSIGNMENT FEATURES P1 w Access times : 50, 60ns P2 PIN Symbol PIN Symbol PIN Symbol PIN Symbol w Single +5V ± 0.5V power supply 1 Vcc 26 Vcc 51 Vcc 76 Vcc w JEDEC Standard pinout 2 NC 27 /CAS0 52 NC 77 /CAS2 w EDO mode operation 3 /RAS0 28 /CAS1 53 /RAS2 78 /CAS3 w TTL compatible inputs and outputs 4 /RAS1 29 NC 54 /RAS3 79 DQ22 w FR4-PCB design 5 DQ15 30 NC 55 DQ31 80 DQ21 6 DQ14 31 NC 56 DQ30 81 DQ20 7 DQ13 32 NC 57 DQ29 82 DQ19 w High-density 32MByte design OPTIONS MARKING w Timing 8 Vss 33 Vss 58 Vss 83 Vss DQ12 34 NC 59 NC 84 DQ18 50ns access -5 9 60ns access -6 10 DQ11 35 NC 60 /WE 85 DQ17 11 DQ10 36 DQ9 61 NC 86 DQ16 12 DQ8 37 DQ7 62 NC 87 NC 13 Vss 38 Vss 63 Vss 88 Vss 14 DQ6 39 DQ5 64 NC 89 NC 15 DQ4 40 NC 65 NC 90 NC NC w Packages 100-pin SMM F PERFORMANCE RANGE Speed tRAC tCAC tRC tHPC 16 DQ3 41 A11 66 DQ28 91 5 50ns 13ns 90ns 26ns 17 DQ2 42 A10 67 DQ27 92 NC 18 Vss 43 Vss 68 Vss 93 Vss 19 DQ1 44 A9 69 DQ26 94 NC 20 DQ0 45 A8 70 DQ25 95 Vss 21 A0 46 A7 71 DQ24 96 NC 22 A1 47 A6 72 DQ23 97 NC 23 A2 48 A5 73 Vss 98 Vss 24 A3 49 A4 74 NC 99 NC 25 Vcc 50 Vcc 75 Vcc 100 Vcc 6 60ns 15ns 110ns 30ns 100PIN SMM TOP VIEW HANBit Electronics Co.,Ltd. HANBit HMD8M32F4E FUNCTIONAL BLOCK DIAGRAM U1 /RAS0 /RAS /CAS0 /LCAS /CAS1 /UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /W /RAS /RAS3 /LCAS /RAS /RAS1 /LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /OE A0-A11 U4 /RAS /RAS2 /LCAS /CAS2 /UCAS DQ16-31 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CAS0 /CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /W /UCAS /W U3 /UCAS A0-A11 U2 /CAS3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0-15 /OE /CAS2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /OE /W A0-A11 /CAS3 A0-A11 /WE A0-A11 Vcc Vss 0.1uF or Capacitor for each DRAM 0.22uF To all DRAMs HANBit Electronics Co.,Ltd. HANBit HMD8M32F4E ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 7.0V Voltage on Vcc Supply Relative to Vss Vcc -1V to 7.0V Power Dissipation PD 4W TSTG -55oC to 150oC IOS 50mA Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 816 mA -6 - 736 mA Don't care - 32 mA -5 - 816 mA -6 - 736 mA -5 - 896 mA -6 - 816 mA Don't care - 16 mA -5 - 816 mA -6 - 736 mA Il(L) -80 80 µA IO(L) -10 2.4 - 10 0.4 µA V V ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 VOH VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) HANBit Electronics Co.,Ltd. HANBit HMD8M32F4E ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE o ( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A11) CIN1 - 100 pF Input Capacitance (/WE) C IN2 - 130 pF Input Capacitance (/RAS0-/RAS3) CIN3 - 40 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 30 pF Input/Output Capacitance (DQ0-31) CDQ1 - 20 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 -6 STANDARD OPERATION SYMBOL MIN Random read or write cycle time tRC 90 Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 3 Output buffer turn-off delay tOFF 3 13 3 13 ns Transition time (rise and fall) tT 2 50 2 50 ns /RAS precharge time tRP 30 40 ns /RAS pulse width tRAS 50 10K ns /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 38 45 ns /CAS pulse width tCAS 8 10K 10 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns MAX MIN MAX 110 ns 3 10K 60 UNIT ns HANBit Electronics Co.,Ltd. HANBit HMD8M32F4E Column address hold time tCAH 8 10 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 ns Write command hold time tWCH 10 10 ns Write command hold referenced to /RAS tWCR 50 55 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 13 10 ns Write command to /CAS lead time tCWL 8 10 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 8 10 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 5 5 ns /CAS hold time (C-B-R refresh) tCHR 10 10 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA /CAS precharge time (Fast page) tCP 8 /RAS pulse width (Fast page ) tRASP 50 /W to /RAS precharge time (C-B-R refresh) tWRP 10 64 64 30 35 10 200K 60 10 ns ns ns 200K ns ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns NOTES 1. An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1TTL loads and 100pF 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5. Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by t AA. HANBit Electronics Co.,Ltd. HANBit HMD8M32F4E PACKAGING INFORMATION 1.2 ± 0.08 mm ORDERING INFORMATION Part Number Density Org. Package HMD8M32F4E- 5 32MByte x 32 100 Pin-SMM HMD8M32F4E- 6 32MByte x 32 100 Pin-SMM Component Vcc MODE SPEED 4EA 5.0V EDO 50ns 4EA 5.0V EDO 60ns Number HANBit Electronics Co.,Ltd.