Agilent HMMC-3004 DC – 16 GHz GaAs HBT MMIC Divide-by-4 Prescaler Data Sheet Features • Wide frequency range: 0.2 – 16 GHz • High input power sensitivity: On-chip pre- and post-amps -20 to +10 dBm (1–10 GHz) -15 to +10 dBm (10 – 12 GHz) -10 to +5 dBm (12 – 15 GHz) • Dual mode Pout: (chip form) +6.0 dBm (0.99 Vp-p) @ 80 mA Chip Size: Chip Size Tolerance: Chip Thickness: Pad Dimensions: 1330 x 440 µm (52.4 x 17.3 mils) ± 10 µm (± 0.4 mils) 127 ± 15 µm (5.0 ± 0.6 mils) 70 x 70 µm (2.8 x 2.8 mils) 0 dBm (0.5 Vp-p) @ 60 mA • Low phase noise: -153 dBc/Hz @ 100 kHz Offset • (+) or (-) single supply bias operation • Wide bias supply range: 4.5 to 6.5 volt operating range • Differental I/O with on-chip 50Ω matching Description The HMMC-3004 GaAs HBT MMIC Prescaler offers DC to 16 GHz frequency translation for use in communications and EW systems incorporating highfrequency PLL oscillator circuits and signal-path down conversion applications. The prescaler provides a large input power sensitivity window and low phase noise. In addition to the features listed above the device offers an input disable contact pad to eliminate any self-oscillation condition. Absolute Maximum Ratings[1] (@ TA = 25°C, unless otherwise indicated) Symbol Parameters/Conditions Units Min. Max. VCC Bias Supply Voltage V VEE Bias Supply Voltage V [VCC-VEE] Bias Supply Delta V VDisable Pre-amp Disable Voltage V VEE VCC VLogic Logic Threshold Voltage V VCC –1.5 VCC –1.2 Pin (CW) CW RF Input Power dBm +10 VRFin DC Input Voltage (@ RFin or RFin Ports) V VCC ± 0.5 TBS[2] Backside Operating Temperature °C -40 +85 Tstg Storage Temperature °C -65 +165 Tmax Max. Assembly Temp. (60 seconds max.) °C +7 -7 +7 310 Notes: 1. Operation in excess of any parameter limit (except TBS) may result in permanent damage to this device. 2. MTTF >1 x106 hours @ TBS ≤ 85°C. Operation in excess of maximum operating temperature (TBS) will degrade MTTF. HMMC-3004 DC Specifications/Physical Properties (@ TA = 25°C, VCC - VEE = 5.0 volts, unless otherwise indicated) Symbol Parameters and Test Conditions Units Min. Typ. Max. VCC - VEE Operating bias supply difference[1] V 4.5 5.0 6.5 Bias supply current (High output power configuration[2]: VPwrSel = VEE) Bias supply current (Low output power configuration: VPwrSel = open) mA mA 68 51 80 60 92 69 VRFin(q) VRFout(q) Quiescent DC voltage appearing at all RF ports V VLogic Nominal ECL Logic Level (VLogic contact self-bias voltage, generated on-chip) V |ICC| or |IEE| VCC VCC - 1.45 VCC - 1.35 VCC - 1.25 Notes: 1. Prescaler will operate over full specified supply voltage range. VCC or VEE not to exceed limits specified in Absolute Maximum Ratings section. 2. High output power configuration: Pout = +6.0 dBm (Vout = 0.99 Vp-p), Low output power configuration: Pout = 0 dBm (Vout = 0.5 Vp-p) RF Specifications, (TA = 25°C, Z0 = 50Ω, VCC - VEE = 5.0 volts) Symbol Parameters and Test Conditions ƒin(max) Maximum input frequency of operation ƒin(min) Minimum input frequency of operation (Pin = -10 dBm) ƒSelf-Osc. Pin [1] Units Min. Typ. GHz 16 18 GHz 0.2 Output Self-Oscillation Frequency[2] GHz 3.4 @ DC, (Square-wave input) @ ƒin = 500 MHz, (Sine-wave input) ƒin = 1 to 10 GHz ƒin = 10 to 12 GHz ƒin = 12 to 15 GHz dBm dBm dBm dBm dBm RL Small-Signal Input/Output Return Loss (@ƒin < 12 GHz) dB 15 S12 Small-Signal Reverse Isolation (@ƒin <12 GHz) dB 30 ϕN SSB Phase Noise (@ Pin = 0 dBm, 100 kHz offset from a ƒout = 1.2 GHz Carrier) dBc/Hz -153 Jitter Input signal time variation @ zero-crossing (ƒin = 10 GHz, Pin = -10 dBm) ps 1 Τr or Τf Output edge speed (10% to 90% rise/fall time) ps 70 -15 -15 -15 -10 -4 >-25 >-20 >-25 >-15 >-10 Max. 0.5 +10 +10 +10 +10 +4 Notes: 1. For sine-wave input signal. Prescaler will operate down to D.C. for square-wave input signal. Minimum divide frequency limited by input slew-rate. 2. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Pre-amp Disable (VDisable) feature, or the Differental Input de-biasing technique. 2 HMMC-3004 RF Specifications, continued High Output Power Operating Mode [1] (TA = 25°C, ZO = 50Ω, VCC - VEE = 5.0V) Symbol Parameters and Test Conditions Units Min. Typ. Pout @ ƒout < 1 GHz @ ƒout = 2.5 GHz @ ƒout = 3.5 GHz dBm dBm dBm 4.0 4.0 3.0 6.0 6.0 5.0 |Vout(p-p)| @ ƒout < 1 GHz @ ƒout = 2.5 GHz @ ƒout = 3.5 GHz volts volts volts 0.79 0.79 0.70 0.99 0.99 0.88 dBm -48 PSpitback ƒout power level appearing at RFin or RFin (@ ƒin = 12 GHz, Unused RFout or RFout unterminated) ƒout power level appearing at RFin or RFin (@ ƒin = 12 GHz, Both RFout & RFout terminated) dBm -68 Pfeedthru Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz, Pin = 0 dBm, Referred to Pin (ƒin)) dBc -30 H2 Second harmonic distortion output level (@ ƒout = 3.0 GHz, Referred to Pout (ƒout)) dBc -25 Max. Low Output Power Operating Mode [2] Pout @ ƒout < 1 GHz @ ƒout = 2.5 GHz @ ƒout = 3.5 GHz dBm dBm dBm -2.0 -2.0 -3.0 0 0 -1.0 |Vout(p-p)| @ ƒout < 1 GHz @ ƒout = 2.5 GHz @ ƒout = 3.5 GHz volts volts volts 0.39 0.39 0.35 0.5 0.5 0.44 dBm -57 PSpitback ƒout power level appearing at RFin or RFin (@ ƒin = 12 GHz, Unused RFout or RFout unterminated) ƒout power level appearing at RFin or RFin (@ ƒin = 12 GHz, Both RFout & RFout terminated) dBm -77 Pfeedthru Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz, Pin = 0 dBm, Referred to Pin (ƒin)) dBc -30 H2 Second harmonic distortion output level (@ ƒout = 3.0 GHz, Referred to Pout (ƒout)) dBc -30 Notes: 1. VPwrSel = VEE . 2. VPwrSel = Open Circuit. Post Amplifier Stage Input Preamplifier Stage VCC VCC 50Ω RFin 50Ω 50Ω RFout 50Ω RFout ÷4 RFin 18/36 mA Divide Cell VEE VEE Figure 1. HMMC-3004 Simplified Schematic. 3 VDisable VPwrSel Applications The HMMC-3004 is designed for use in high frequency communications, microwave instrumentation, and EW radar systems where low phase-noise PLL control circuitry or broad-band frequency translation is required. Operation The device is designed to operate when driven with either a singleended or differential sinusoidal input signal over a 200 MHz to 16 GHz bandwidth. Below 200 MHz the prescaler input is “slew-rate” limited, requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to DC when driven with a square-wave. The device may be biased from either a single positive or single negative supply bias. The backside of the device is not DC connected to any DC bias point on the device. For positive supply operation VCC is nominally biased at any voltage in the +4.5 to +6.5 volt range with VEE (or VEE & VPwrSel) grounded. For negative bias operation VCC is typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to VEE (or VEE & VPwrSel). Several features are designed into this prescaler: 1) Dual-Output Power Feature Bonding both VEE and VPwrSel pads to either ground (positive bias mode) or the negative supply (negative bias mode), will deliver ~0 dBm [0.5Vp-p] at the RF output port while drawing ~40 mA supply current. Eliminating the VPwrSel connection results in reduced output power and voltage swing, -6.0 dBm [0.25Vp-p] but at a reduced current draw of ~30 mA resulting in less overall power dissipation. 4 (NOTE: VEE must ALWAYS be bonded and VPwrSel must NEVER be biased to any potential other than VEE or open-circuited.) 2) VLogic ECL Contact Pad Under normal conditions no connection or external bias is required to this pad and it is selfbiased to the on-chip ECL logic threshold voltage (VCC –1.35V). The user can provide an external bias to this pad (1.5 to 1.2 volts less than VCC) to force the prescaler to operate at a system generated logic threshold voltage. 3) Input Disable Feature If an RF signal with sufficient signal to noise ratio is present at the RF input, the prescaler will operate and provide a divided output equal to the input frequency divided by the divide modulus. Under certain “ideal” conditions where the input is well matched at the right input frequency, the device may “selfoscillate”, especially under small signal input powers or with only noise present at the input. This “self-oscillation” will produce an undesired output signal also known as a false trigger. By applying an external bias to the input disable contact pad (more positive than VCC –1.35V), the input preamplifier stage is locked into either logic “high” or logic “low” preventing frequency division and any self-oscillation frequency which may be present. 4) Input DC Offset Another method used to prevent false triggers or self-oscillation conditions is to apply a 20 to 100 mV DC offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider. Adding a 10KΩ resistor between the unused RF input to a contact point at the VEE potential will result in an offset of ≈25mV between the RF inputs. Note however, that the input sensitivity will be reduced slightly due to the presence of this offset. Assembly Techniques Figure 3 shows the chip assembly diagram for single-ended I/O operation through 12 GHz for either positive or negative bias supply operation. In either case the supply contact to the chip must be capacitively bypassed to provide good input sensitivity and low input power feedthrough. Independent of the bias applied to the device, the backside of the chip should always be connected to both a good RF ground plane and a good thermal heat sinking region on the mounting surface. All RF ports are DC connected on-chip to the VCC contact through on-chip 50Ω resistors. Under any bias conditions where VCC is not DC grounded, the RF ports should be AC coupled via series capacitors mounted on the thin-film substrate at each RF port. Only under bias conditions where VCC is DC grounded (as is typical for negative bias supply operation) may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. In the latter case the device backside may be “floated” and bias applied as the difference between VCC and VEE. All bonds between the device and this bypass capacitor should be as short as possible to limit the inductance. For operation at frequencies below 1 GHz, a large value capacitor must be added to provide proper RF bypassing. Due to on-chip 50Ω matching resistors at all four RF ports, no external termination is required on any unused RF port. However, improved “Spitback” performance (~20 dB) and input sensitivity can be achieved by terminating the unused RFout port to VCC through 50Ω (positive supply) or to ground via a 50Ω termination (negative supply operation). GaAs MMICs are ESD sensitive. ESD preventive measures must be employed in all aspects of storage, handling, and assembly. factors in successful GaAs MMIC performance and reliability. MMIC ESD precautions, handling considerations, die attach and bonding methods are critical Agilent application note #54, “GaAs MMIC ESD, Die Attach and Bonding Guidelines” provides basic information on these subjects. Optional DC Operating Values/Logic Levels (TA = 25°C) Function Symbol Logic Threshold[1] Input Disable Conditions Min. (volts/mA) Typical (volts/mA) Max. (volts/mA) VLogic VCC – 1.5 VCC – 1.35 VCC – 1.2 VDisable(High) [Disable] VLogic + 0.25 VLogic VCC VDisable(Low) [Enable] VEE IDisable VLogic – 0.25 VD > VEE + 3 (VDisable – VEE – 3)/500 (VDisable – VEE – 3)/500 (VDisable – VEE – 3)/500 VD < VEE + 3 0 0 0 Note: 1. Acceptable voltage range when applied from external source. VCC VCC RFin RFout VCC VCC RFin RFout No Connection VCCBypass VLogic VDisable 230 VEE VPwrSel 900 260 440 Notes: • All dimensions in microns. • All Pad Dim: 70 x 70 µm (except where noted) • Tolerances: ±10 µm • Chip Thickness: 127 ± 15 µm 370 220 70 0 70 350 500 0 Figure 2. Pad Locations and Chip Dimensions. 5 650 800 950 1090 1260 1330 POSITIVE SUPPLY To +4.5V to +6.5V VCC supply (Bypassed via 1 µF Capacitor) AC Coupling Capacitor(s) >300 pF VCC Bypass Capacitor 3 mil nominal Gap (@ Device Input) AC Coupling Capacitor (Note: Must be large enough to pass lowest frequency output signal) RFout RFin Optional 50 Ω Termination RFout RFin Optional Differential Input VEE bond required (GND) To VCC or GND if AC coupling cap is employed Optional Differential Output OPTIONAL VPwrSel Pad Connection: w/Pad bonded to ground: HIGH Pout Assembly (+5.5 dBm [0.94 Vp-p] @ ICC = 80 mA) w/Pad NOT bonded to ground: LOW Pout Assembly (0 dBm [0.5 Vp-p] @ ICC = 60 mA) NEGATIVE SUPPLY 3 mil nominal Gap (@ Device Input) RFout RFin Optional 50 Ω Termination RFout RFin Optional Differential Output Optional Differential Input >300 pF VEE Bypass Capacitor VEE bond required w/Pad NOT bonded to VEE: LOW Pout Assembly (0 dBm [0.5 Vp-p] @ ICC = 60 mA) To -4.5V to -6.5V VEE supply (Bypassed via 1 µF Capacitor) Figure 3. Assembly Diagrams. 6 OPTIONAL VPwrSel Pad Connection: w/Pad bonded to VEE: HIGH Pout Assembly (+6.0 dBm [0.99 Vp-p] @ ICC = 80 mA) HMMC-3004 Supplemental Data VCC – VEE = +5 V, TA = 25°C 100 TA = 25°C 0 High Power Mode 90 0 ISupply (mA) INPUT POWER, Pin (dBm) 10 -10 -20 -30 -0.2 80 -0.4 70 -0.6 -0.8 60 50 -1.0 Low Power Mode 40 -1.2 30 -1.4 20 -1.6 10 -1.8 -2.0 0 -40 0 2 4 6 8 10 12 0 14 16 18 20 1 2 3 4 5 6 7 8 9 VCC – VEE (V) INPUT FREQUENCY, ƒin (GHz) Figure 5. Typical Supply Current & VLogic vs. Supply Voltage. Figure 4. Typical Input Sensitivity Window. VCC–VEE = +5 V, TA = 25°C 8 Low Pout Mode, Tr = ~70 pS, Output Freq: 882 MHz, TA = 25°C INPUT POWER, Pin (dBm) Pout (@ Pin = 0 dBm) (dBm) High Power Mode 6 4 2 Low Power Mode 0 -2 0 PERIOD, (200 pS/div.) 0.5 1.5 1 2 2.5 3 3.5 4 4.5 OUTPUT FREQUENCY (GHz) Figure 7. Typical Output Power vs. Output Frequency, ƒout (GHz). Figure 6. Typical Output Voltage Waveform. Pin = 0 dBm, Fcarrier = 6.0 GHz -50 -23 -60 -43 -70 PSpitback (dBm) SSB PHASE NOISE (dBc/Hz) -3 -63 -83 -103 VCC – VEE = +5 V, Pin = 0 dBm, TA = 25°C Unterminated RFout Port -80 -90 -123 -100 -143 -110 Both RFout Ports Terminated -163 10 100 1K 10K 100K OFFSET FROM CARRIER (Hz) Figure 8. Typical Phase Noise Performance. 7 1M 10M -120 0 2 4 6 8 10 12 14 16 18 20 22 INPUT FREQUENCY, ƒin (GHz) Figure 9. Typical “Spitback” Power. P(ƒout) appearing at RF input port. VLogic – VCC (V) 20 This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifications. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact your local Agilent Technologies’ sales representative. www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. Obsoletes 5988-3195EN May 22, 2002 5988-6157EN