PD- 97108 iP1203PbF Single Output Full Function Synchronous Buck Power Block Integrated Power Semiconductors, PWM Control & Passives Features • • • • • • • • • • 5.5V to 13.2V Input Voltage 0.8V to 8V Output Voltage 15A Maximum Load Capability 200-400kHz Nominal Switching Frequency Over Current Hiccup External Synchronization Capable Overvoltage Protection Over Temperature Protection Internal Features Minimize Layout Sensitivity Very Small Outline 9mm x 9mm x 2.3mm iP1203PbF Power Block Description The iP1203PbF is a fully optimized solution for medium current synchronous buck applications requiring up to 15A. It includes full function PWM control, with optimized power semiconductor chipsets and associated passives, achieving high power density. Very few external components are required to create a complete synchronous buck power supply. iPOWIR™ technology offers designers an innovative space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. iP1203PbF Simplified Application Schematic VIN V IN OC Pin Number (See Page 18) Pin Name Pin Description 1, 23 VIN Input voltage connection pins 2,3,4,5,7,17,20,21 PGND Power Ground pins 6 VCC_bypass PWM controller power supply pin. Internally generated. Requires a 2.2µf external bypass capacitor 8 SS Soft start pin. External capacitor provides soft start. Pulling soft start pin low will disable the output. Cannot be cycled to unlatch OVP trip 9 CC Output of the error amplifier 10 FB Inverting input of the error amplifier 11 FBs Output overvoltage sense pin. 12 RT Switching frequency setting pin. For RT selection, refer to Fig.9 of the datasheet 13 PGOOD Power Good pin. Open collector, requires external pulll-up. If function not needed, pin can be left floating 14 VREF Non inverting input of the error amplifier (reference Voltage pin). Connect a 100pF cap from this pin to PGND. 15 SYNC External Clock synchronization pin. Set free running frequency to 80% of the SYNC frequency. When not in use, leave pin floating 16 OCSET Output overcurrent trip threshold pin 18,19 VSW Output inductor connection pins 22 VSWs Test pad, for internal use, short to VSW 24 VINs Test pad, for internal use, short to VIN VOUT V SW V CC_bypass FB FB S PGOOD SS iP1203 iP1203PbF CC SYNC PGND RT PACKAGE DESCRIPTION INTERFACE CONNECTION iP1203PbF iP1203TRPbF LGA LGA V REF PARTS PARTS PER PER BAG REEL 10 --- --1000 T&R ORIENTATION Fig 26 8/11/06 iP1203PbF All specifications @ 25°C (unless otherwise specified) Absolute Maximum Ratings Parameter VIN Symbol VIN Feedback FB FBS Output Overvoltage Sense PGOOD Soft Start SYNC Output RMS Current Block Temperature Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Typ Max 15 6 6 15 6 6 15 Units Conditions IoutVSW ––– ––– ––– ––– ––– ––– ––– ––– TBLK -10 ––– 125 °C Min 5.5 Typ ––– Max 13.2 Units V ––– ––– 15 A TPCB = TCASE = 90°C. See Fig.3 ––– ––– 11 A TPCB = 90°C, TCASE = no airflow, no heatsink. 0.8 0.8 ––– ––– 8.0 3.3 V Min Typ Max Units SS V A See Fig.3 Recommended Operating Conditions Parameter Input Voltage Range Symbol VIN Output RMS Current IoutVSW Output Voltage Range VOUT Conditions For VIN = 12V For VIN = 5.5V Electrical Specifications @ VIN = 12V Parameter Power Loss Over Current Shutdown HICCUP Duty Cycle Soft Start Time Reference Voltage VOUT Accuracy Error Amplifier Source/Sink Current Error Amplifier Transconductance Output Overvoltage Shutdown Threshold Symbol PLOSS ––– 3.75 4.9 W IOC ––– 25 ––– A DHICCUP ––– 5 ––– % tSS ––– 5 ––– ms VREF ––– 0.8 ––– V VOUT_ACC1 -3 ––– 3 VOUT_ACC2 -2 ––– 2 IERR ––– 60 ––– µA gm ––– 2000 ––– µmho OVP PGOOD Trip Threshold VTh_PGOOD PGOOD Output Low Voltage VLO_PGOOD 2 % Conditions fSW = 300kHz, VIN = 12V, TBLK= 25°C VOUT = 1.5V, IOUT = 15A, See Fig.10 VIN = 12V, VOUT = 1.5V fSW = 300KHz, ROCSET = 40.2kΩ VIN = 12V, VOUT = 1.5V, CSS=0.1µF TBLK = -10°C to 125°C VIN= 12V, VOUT = 1.5V TBLK = 0°C to 70°C VIN= 12V, VOUT = 1.5V 1.1 x VOUT 1.15 x VOUT 1.2 x VOUT V 0.85 x VOUT ––– V FB ramping down ––– 0.3 V ISINK=2mA ––– ––– www.irf.com iP1203PbF Electrical Specifications (continued) Parameter Frequency Symbol fSW Min 170 255 340 ––– ––– ––– Typ Max 230 345 460 Units kHz kHz kHz SYNC Frequency Range fSYNC 480 ––– 800 kHz SYNC Pulse Duration tSYNC ––– 200 ––– ns 2 ––– ––– V ––– ––– 0.8 V SYNC, High Level Threshold Voltage Conditions RT = 48.7kΩ RT = 30.9kΩ RT = 21.5kΩ Free running frequency set 20% below sync frequency SYNC, Low Level Threshold Voltage VIN Quiescent Current IIN-LEAKAGE 35 mA Thermal Shutdown ––– ––– 25 Tempshdn 140 85 ––– ––– ––– °C DMAX % fSW = 200kHz, TBLK = 25°C VIN-UVLO ––– 4.5 ––– V VIN ramping up to 12V VIN-UVLO HYST ––– 0.25 ––– V VIN ramp up and ramp down Output Disable Voltage Soft Start Low Threshold Voltage VSS-DIS ––– ––– 0.25 V SS Pin Pulled Low Input Voltage Slew Rate VIN-SLEW ––– ––– 50 mV/µs Max Duty Cycle VIN Undervoltage Lockout Threshold Voltage VIN Undervoltage Lockout Hysteresis www.irf.com VIN = 12V 3 4 FBS VREF RT SYNC CC FB 0.8V SS 0.8V 25k 25k 64uA OVP (+15%) PGood (-10%) SW1 SW2 Error Amp 3uA 25uA Ramp Oscilator PWM Comp UVLO Bias Generator S R Q Control OC Latch / Hiccup PWM Driver SW2 SW1 20k PGOOD PGND OCSET VSW VCC bypass VIN iP1203PbF Fig. 1: iP1203PbF Internal Block Diagram www.irf.com iP1203PbF 6 VIN = 12V VOUT = 1.5V Power Loss (W) 5 fsw L = 300kHz = 1.0µH TBLK = 125°C 4 Maximum 3 Typical 2 1 0 0 5 10 15 Output Current (A) Fig. 2: Power Loss vs. Current Case Temperature (°C) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 16 14 Output Current (A) 12 Safe Operating Area VIN = 12V V OUT = 1.5V 10 fsw L 8 = 300kHz = 1.0µH Tx 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (°C) www.irf.com Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE 5 iP1203PbF Typical Performance Curves 1.0 fsw = 300kHz L = 1.0µH TBLK = 125°C 1.02 0.5 1.00 0.0 0.98 -0.5 1.36 10 1.32 9 1.28 8 1.24 7 6 1.20 5 1.16 4 1.12 1.08 1.04 1.00 0.96 0.96 -1.0 5 6 7 8 9 10 11 12 13 0.92 14 0.8 1.6 2.4 0.5 0.0 1.000 0.960 Power Loss (Normalized) Power Loss (Normalized) IOUT = 15A L = 1.0µH TBLK = 125°C -0.5 350 25 Vin = 5.5V 15 10 5 6 6 8 10 12 14 16 18 Overload Current (A) 7.2 8.0 6.0 5.0 1.16 4.0 fsw = 300kHz TBLK = 125°C 1.12 3.0 1.08 2.0 1.04 1.0 1.00 0.0 -1.0 0.8 1.2 1.6 2.0 2.4 20 22 24 Fig. 8: Nominal Overcurrent Threshold Setting External Resistor Selection Fig. 7: Normalized Power Loss vs. Inductance 400 Switching Frequency (kHz) ROC-SET (kOhms) for 12Vin Vin = 12V 20 6.4 0.96 ROC-SET (kOhms) for 5.5Vin L = 1.0µH TBLK = 125°C 30 5.6 VOUT = 1.5V IOUT = 15A 0.4 205 185 165 145 125 105 85 65 45 25 5 VOUT = 1.5V fsw = 300kHz 35 4.8 Output Inductance (µH) 55 40 4.0 1.20 400 Fig. 6: Normalized Power Loss vs. Frequency 45 -1 VIN = 12V Swiching Frequency (kHz) 50 0 380 360 340 320 300 280 260 240 220 200 20 25 30 35 40 RT (kOhms) 45 50 Fig. 9: Switching Frequency vs RT www.irf.com SOA Temp Adjustment (°C) 1.0 300 3.2 1.24 SOA Temp Adjustment (°C) VIN = 12V VOUT = 1.5V 250 1 Fig. 5: Normalized Power Loss vs. VOUT 1.5 1.120 200 fsw = 300kHz L = 1.0µH TBLK = 125°C 2 Output Voltage (V) Fig. 4: Normalized Power Loss vs. VIN 1.040 3 -2 Input Voltage (V) 1.080 VIN = 12V IOUT = 15A SOA Temp Adjustment (°C) 1.04 Power Loss (Normalized) 1.5 VOUT = 1.5V IOUT = 15A SOA Temp Adjustment (°C) Power Loss (Normalized) 1.06 iP1203PbF Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case. 0 Procedure 10 20 30 40 50 60 70 80 90 100 110 120 Case Temperature (ºC) 16 14 1 12 Output Current (A) 1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. (see AN-1047 for further explanation of TX ) 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current. 4) If no top sided heatsinking is available, assume TCASE temperature of 125°C for worst case performance. 3 10 2 8 6 TX VIN = 12V VOUT = 1.5V fSW = 300kHz L=1.0uH 4 2 iP1203 SOA 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) Adjusting the Power Loss and SOA Curves for Different Operating Conditions To make adjustments to the power loss curves in Fig. 2, multiply the normalized value obtained from the curves in Figs. 4, 5, 6 or 7 by the value indicated on the power loss curve in Fig. 2. Then if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 2. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 3, determine your maximum PCB Temp & Case Temp at the maximum operating current of each iP1203PbF. Then, add the correction temperature from the normalized curves in Figs. 4, 5, 6 or 7 to the TX axis intercept (see procedure no. 2 above) in Fig. 3. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 3. See example no. 2. Operating Conditions for the following examples: Output Current = 12A Output Voltage = 1.2V Input Voltage = 13.2V Sw Freq= 400kHz Inductor = 0.6µH Example 1) Adjusting for Maximum Power Loss: (Fig. 2) Maximum power loss = 4.1W (Fig. 4) Normalized power loss for input voltage ≈ 1.025 (Fig. 5) Normalized power loss for output voltage ≈ 0.97 (Fig. 6) Normalized power loss for frequency ≈ 1.08 (Fig. 7) Normalized power loss for inductor value ≈ 1.08 Adjusted Power Loss = 4.1 x 1.025 x 0.97 x 1.08 x 1.08 ≈ 4.75W www.irf.com 7 iP1203PbF Example 2) Adjusting for SOA Temperature: Assuming TCASE = 110°C & TPCB = 90°C for both outputs Output1 (Fig. 4) Normalized SOA Temperature for input voltage ≈ +0.7°C (Fig. 5) Normalized SOA Temperature for output voltage ≈ -0.75°C (Fig. 6) Normalized SOA Temperature for frequency ≈ +1.0°C (Fig. 7) Normalized SOA Temperature for inductor value ≈ +2.0°C TX axis intercept temp adjustment = +0.5°C - 0.75°C + 1.0°C +2.0°C ≈ +2.75°C The following example shows how the SOA current is adjusted for a TX change of +2.75°C and output is in SOA 0 10 20 30 40 50 60 70 80 90 100 110 120 Case Temperature (ºC) 16 14 Unadjusted SOA curve Output Current (A) 12 Adjusted SOA curve 10 8 6 TX VIN = 12V VOUT = 1.5V fSW = 300kHz L=1.0uH 4 2 iP1203 SOA iP1203PbF SOA 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (ºC) Iin Average A V Vin Average PIN= VIN Average x I IN Average Cin POUT= VOUT Average xI OUTAverage Vin DC PLoss = PIN - POUT VIN Iout Average VSW Lo Co iP1203PbF iP1203 Iout FB PGND Vout A Averaging Circuit V Vout Average Fig. 10: Power Loss Test Circuit 8 www.irf.com iP1203PbF VINs PGND PGND PGND PGND VIN VCCbypass VIN PGND VSWs SS PGND VSW PGND CC FB FBS VSW OCSET SYNC PGND VREF RT PGOOD Fig. 11: Recommended PCB Footprint (Top View) www.irf.com 9 iP1203PbF iP1203PbF Users Design Guidelines The iP1203PbF is a single output 15A power block consisting of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by parasitics are of concern. The power block operates with fixed frequency voltage mode control. The iP1203PbF components are integrated in a land grid array (LGA) package. Iss SS 10 10 iP1203 iP1203PbF Css VIN / Enabling the Output The input operating voltage range of the iP1203PbF is 5.5V to 13.2V. The iP1203PbF output is turned on upon application of input voltage. The VIN slew rate should not exceed 50mV/µs. The converter can also be turned on and off by releasing or pulling the SS pin low through a logic level MOSFET, the drain of which connects to the soft start pin (see Fig.12). This feature can be useful if sequencing or different start-up timing of different system outputs are required. In situations where the output has undergone a latched shutdown due to overvoltage, cycling Vin will reset the output. Cycling soft start pin will not unlatch the output. Soft Start The Soft Start function provides a controlled rise of the output voltage, thus limiting the inrush current. The soft start function has an internal 25µA +/-20% current source that charges the external soft start capacitor Css up to 3V. During power-up, the output voltage starts ramping up only after the charging voltage across the Css capacitor has reached a 0.8Vtyp threshold, as shown in Fig. 13. 10 Fig.12: Soft Start/Enable Circuit 3V 0.8Vtyp VCss VOUT Fig. 13: Power Up Threshold Frequency and Synchronization The operating switching frequency (fSW) range of iP1203PbF is 200 kHz to 400 kHz. The desired frequency is set by placing an external resistor to the RT pin of the iP1203PbF. See Fig. 9 for the proper resistor value. The iP1203PbF is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge clock. The free running oscillator frequency is twice the switching frequency. During synchronization, RT is selected such that the free running frequency is 20% below the synchronization frequency. The maximum synchronization frequency that iP1203PbF can accept is 800kHz. Note that the actual switching frequency is half the synchronization frequency. www.irf.com iP1203PbF Overcurrent Protection HICCUP PGOOD The overcurrent protection function of the iP1203PbF offers a hiccup feature. During overloads, when the overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart (output HICCUP mode). The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor. Typically, the discharge time of the soft start capacitor is 10 times the charge time. The duty cycle of the hiccup process is typically 5%. The output will stay in hiccup indefinitely until the overload is removed. The typical overcurrent trip threshold of the device is internally set at 30A. The overcurrent shutdown / HICCUP threshold is about ±30% accurate. This is an output voltage status signal that is open collector and is pulled low when the output voltage falls below 85% of the output voltage. High state indicates that outputs are in regulation. The PGOOD pin can be left floating if not used. The iP1203PbF overcurrent shutdown and HICCUP threshold can be set externally by adding ROCSET resistor from OCSET pin. Refer to Fig.8 for ROCSET selection. Thermal Shutdown The iP1203PbF provides thermal shutdown. The threshold typically is set to 140°C. When the trip threshold is exceeded, thermal shutdown turns the output off. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range. Overvoltage Protection (OVP) Overvoltage is sensed through output voltage sense pin FBs. The OVP threshold is set to 115% of the output voltage. Upon overvoltage condition, the OVP forces a latched shutdown. In this mode, the upper FET turns off and the lower FET turns on, thus crowbaring the output. Reset is performed by recycling the input voltage. Overvoltage can be sensed by either connecting FBs to its corresponding output through a separate output voltage divider resistor network, or it can be connected directly to its corresponding feedback pin FB. For Type III control loop compensation, FBs should be connected through voltage dividers only. Refer to the iP1203PbF Design Procedure section on how to set the OVP trip threshold. www.irf.com 11 iP1203PbF iP1203PbF Design Procedure Setting the Overvoltage Trip Only a few external components are required to complete a dual output synchronous buck power supply using iP1203PbF. The following procedure will guide the designer through the design and selection process of these external components. The output of the iP1203 will shut down if it experiences a voltage in the range of 115% of VOUT. The overvoltage sense pin FBs is connected to the output through voltage dividers, R26 and R27 (Fig. 14), and the trip setpoint is programmed according to equation (1). A separate overvoltage sense pin FBs is provided to protect the power supply output if for some reason the main feedback loop is lost (for instance, loss of feedback resistors). An optional 100pF capacitor (C14) is used for delay and filtering. A typical application for the iP1203 is: VIN = 12V, VOUT = 1.5V, IOUT = 15A, fsw = 300kHz, Vp-p = = 50mV Setting the Output Voltage The output voltage of the iP1203PbF is set by the 0.8V reference VREF and external voltage dividers. Vout Selecting the Soft-Start Capacitor The soft start capacitor Css is selected according to equation (2): R2 FB tss = 40 x Css R5 iP1203 (2) where, tss is the output voltage ramp time in milliseconds, and Css is the soft start capacitor in µF. R26 FB S C14 (Optional) If this redundancy is not required and if a Type II control loop compensation scheme is utilized, FBs pin can be connected to FB. A 0.1µF capacitor will provide an output voltage rampup time of about 4ms. R27 Fig. 14: Typical Scheme for Output Voltage Setting Input Capacitor Selection For Type II compensation, The switching currents impose RMS current requirements on the input capacitors. Equation (3) allows the selection of the input capacitors. VOUT is set according to equation (1): I RMS = I out D(1 − D ) VOUT = VREF x (1 + R2 /R5 ) (see Fig. 14) (1) Setting R2 to 1K, VOUT to 1.5V and VREF to 0.8V, will result in R5= 1.14 Kohms. Final values can be selected according to the desired accuracy of the output. (3) where, Iout is the output current, and D is the duty cycle and is expressed as: D = VOUT / VIN. For the above example D= 0.13 and, using equation (3) the capacitor rms current yields 5.0A. To set the output voltage for Type III compensation, refer to equation (24) in Type III compensation section. 12 www.irf.com iP1203PbF For better efficiency and low input ripple, select low ESR ceramic capacitors. The amount of the capacitors is determined based on the rms rating. In the above example, a total of 3 x 22µF, 2A capacitors will be required to support the input rms current. Output Capacitor CO Selection Selection of the output capacitors depends on two factors: a. Low effective ESR for ripple and load transient requirements To support the load transients and to stay within a specified voltage dip ∆V due to the transients, ESR selection should satisfy equation (4): RESR ≤ ∆V / ILoadmax (4) If output voltage ripple is required to be maintained at specified levels then the expression in equation (5) should be used to select the output capacitors. (5) Where, Vp-p is the peak to peak output ripple voltage . Iripple is the inductor peak-to peak ripple current. In addition, the voltage ripple caused by the output capacitor needs to be significantly smaller than the ripple caused by the ESR of the capacitor. Use equation (6) to satisfy this requirement. Co > 10 2π × f s × RESR (6) If the inductor current ripple Iripple is 30% of IOUT1, the 50mV peak to peak output voltage ripple requirement will be met if the total ESR of the output capacitors is less than 11mΩ. This will require 2 x 470µF POSCAP capacitors. Additional ceramic capacitors can be added in parallel to further reduce the ESR. Care should be given to properly compensate the control loop for low output capacitor ESR values. www.irf.com b. Stability The value of the output capacitor ESR zero frequency fesr plays a major role in determining stability. fesr is calculated by the expression in equation (7). fESR = 1 / (2 π x RESR x CO) Where, ILoadmax is the maximum load current. RESR ≤ Vp-p / Iripple When selecting output capacitors, it is important to consider the overshoot performance of the power supply. If the amount of capacitance is not adequate, then, when unloading the output, the magnitude of the overshoot due to stored inductor energy, and depending on the speed of the response of the control loop, can exceed the overvoltage trip threshold of the iP1203PbF and can cause undesirable shutdown of the output. The magnitude of the overshoot should be kept below 1.125VOUT . To prevent the overshoot from tripping the output a delay can be added by installing capacitor C14 as shown in Fig.14. (7) Details on how to consider this parameter to design for stability are outlined in the control loop compensation section of this datasheet. Inductor LO Selection Inductor selection is based on trade-offs between size and efficiency. Low inductor values result in smaller sizes, but can cause large ripple currents and lower efficiency. Low inductor values also benefit the transient performance. The inductor Lois selected according to equation (8): LO = Vout x (1 - D) / (fsw x Iripple) (8) For the above example, and for Iripple of 30% of IOUT, LO is calculated to be 1.0µH. The core must be selected according to the peak of maximum output current. 13 iP1203PbF Control Loop Compensation Vout The iP1203PbF feedback control is based on single loop voltage mode control principle. R2 FB The goal in the design of the compensator is to achieve the highest unity gain (0 db) crossover frequency with sufficient phase margin for the closed loop transfer function. The LC filter of the power supply introduces a double pole with 40db/dec slope and 180° phase lag. The 180° phase contribution from the LC filter is the source of instabilty. The resonant frequency of the LC filter is expressed by equation (9): f LC = 1 / (2π L0 × C 0 ) iP1203PbF iP1203 R5 VREF E/A1 C6 CC C9 (Optional) R19 (9) The error amplifier of the iP1203PbF PWM controller is transconductance amplifier, and its output is available for external compensation. Magnitude(dB) H(s) dB Two types of compensators are studied in this section. The first one is called Type II and it is used to compensate systems the ESR frequency fesr (equation 7) of which is in the midfrequency range and Type III that can be used for any type of output capacitors and have a wide range of fesr. For output voltage settings less than 1.0V that use low ESR ceramic capacitors, it is recommended that the unity gain crossover frequency be set around 20kHz to maintain stable operation. FZ Fig. 15: Typical Type II Compensation and its Gain Plot H ( s) = g m × Type II From Fig.15 the transfer function H(s) of the error amplifier is given by (10): R5 1 + sR19 C 9 H (s) = g m × × (10) R5 + R 2 sR19 C 9 Frequency R5 × R19 R5 + R 2 (11) where, gm is the transconductance of the error amplifier. fz = 1 2π × R19 × C 9 (12) The term s represents the frequency dependence of the transfer function. Follow the steps below to determine the feedback loop compensation component values: The Type II controller introduces a gain and a zero expressed by equations (11) and (12): 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. 14 www.irf.com iP1203PbF 2. Calculate R5 using equation (13): R19 = Vramp × f ×f R + R2 1 1 × 0 2 esr × 5 × (13) Vin f LC R5 gm Where, VIN = Maximum input voltage f0 = Error amplifier zero crossover frequency fesr= Output capacitor Co zero frequency fLC = Output frequency resonant filter gm= Error amplifier transconductance. Use 2mS for gm. Vramp = Oscillator ramp voltage. Use 1.25V for Vramp 3. Place a zero at 75% of fLC to cancel one of the LC filter poles. f z = 0 . 75 × 1 2π Lo × C o H ( s) = (1 + sR20 C 9 ) × (1 + sR2 C 8 ) 1 × sR2 C 9 (1 + sR20 C 7 ) × (1 + sR21C8 ) fLC = 5.0kHz fz = 3.8kHz f0 = 45kHz (15% of 300kHz) fesr = 14kHz, per equation (7) using Resr = 12mΩ. R19 = 2.49K C9 = 18nF Sometimes, a pole fp2 is added at half the switching frequency to filter the switching noise. This is done by adding a capacitor Copt in Fig.15 from the output of the error amplifier (CC pin of iP1203PbF) to ground. This pole is given by equation (15): (15) (17) C7 Vout Calculation of the compensation components based on the example above, yields: 1 2π × R19 × C opt The transfer function of the Type III compensator is given by equation (17) (14) 4. Calculate C9 using equations (12) and (14) f p2 = Type III The Type III compensation scheme allows the use of any type of capacitors with ESR frequency of any range. This scheme suggests a double pole double zero compensation and requires more components around the error amplifier to achieve the desired gain and phase margins. Fig. 13 represents the Type III compensation network for iP1203PbF. C9 R20 C8 R21 CC R2 iP1203PbF iP1203 FB R5 V E/A1 REF C6 Magnitude(dB) H(s) dB FZ1 FZ2 FP2 FP3 Frequency Fig. 16: Typical Type III Compensation and its Gain Plot Copt is found from equation (16) by rearranging the terms in equation (15) and by setting fp2 = fsw / 2: Copt = 1 2π × f p 2 × R19 www.irf.com (16) 15 iP1203PbF The frequencies of the three poles and the two zeros of the Type III compensation scheme are represented by the following equations: fp1= 0 f p2 (18) (19) 1 = 2π × R21 × C8 f p3 = 1 2π × R20 × C 7 (20) f z1 = 1 2π × R20 × C 9 (21) f z2 = 1 2π × R2 × C8 (22) 7. Place the second pole fp2 at or near fesr of the output capacitor Co and determine the value of R21 from R2 equation (19). Make sure R21 < 10 8. Use equation (24) to calculate R5. R 5 = R2 x V ref V -V o ref (24) More than one iteration may be required to calculate the values of the compensation components if crossover frequencies higher than the range specified in step 1 are required (for higher bandwidths and faster transient response performance). To ensure stability a phase margin greater than 45° should be achieved. Refer to AN-1043 for more detailed compensation techniques using Transconductance Amplifiers. The crossover frequency f0 for Type III compensation is represented by equation (23): f0 = 1 Vramp × VIN × R20 × C8 × 1 2π × L0 × C 0 (23) Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. 2. Select R20~ 10kΩ 3. Place the first zero fz1 at 75% of the resonant frequency fLC of the output filter. Determine C9 from equation (21). 4. Place a third pole fP3 at or near the switching frequency fSW. Select C7 such that C7 < C9 10 5. Calculate C8 from equation (23). 6. Place the second zero at 125% of the resonant frequency fLC of the output filter. Calculate R2 using equation (22). 16 www.irf.com iP1203PbF Typical Waveforms Ch1: Switching node, 400kHz Ch2: 800kHz external synchronization Fig. 17: iP1203PbF Outputs Synchronized to 800kHz Ch1: Output voltage, 500mV/div Ch3: Output current, 10A/div Fig. 18: iP1203PbF Output Hiccup, Due to Overload Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div Fig. 19: iP1203PbF Transient Response Load Step 1A to 12A Fig. 20: iP1203PbF Transient Response Load Step 12A to 0A www.irf.com 17 iP1203PbF Ch1: FBs input, 200mV/div Ch2: Output voltage, 1V/div Fig. 21: iP1203PbF Overvoltage Trip. Output Voltage Turns Off When Voltage at FBs Pin Exceeds 15% of FB (0.8V) 18 Fig. 22: iP1203PbF Pin Assignment www.irf.com iP1203PbF Layout Guidelines For stable and noise free operation of the whole power system, it is recommended that the designers use the following guidelines: 1. Follow the layout scheme presented in Fig. 23. Make sure that the output inductor L is placed as close to iP1203PbF as possible to prevent noise propagation that can be caused by switching of power at the switching node Vsw, to sensitive circuits. 2. Provide a mid-layer solid ground plane with connections to the top layer through vias. The PGND pads of iP1203PbF also need to be connected to the same ground plane through vias. 3. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. capacitors should be as close to the device as possible. 5. The feedback track from the output VOUT to FB should be routed as far away from noise generating traces as possible. 6. The compensation components and the Vref bypass capacitor should be placed as close as possible to their corresponding iP1203PbF pins, away from noise generating traces. 7. Refer to IR application note AN-1029 (Optimizing a PCB Layout for an iPOWIR Technology Design) to determine what size vias and copper weight and thickness to use when designing the PCB. 8. Place the overcurrent threshold setting resistors ROCSET close to the iP1203PbF block at the corresponding connection node. 4. Although there is a certain degree of VIN bypassing inside the iP1203PbF, the external input decoupling www.irf.com Fig. 23: iP1203PbF Suggested Layout 19 †† 10uF 16V Removed Removed Installed C7, C8 R19 Removed Installed Installed 30.9K(300kHz) R24 100pF C6 0.1uF C5 2.2uF C4 C18 10uF 16V Type II Configuration Type III Configuration R20,R21 Designator Compensation Configuration PGND J2 10uF 16V C19 10uF 16V C17 14 RT 12 SYNC 15 REF V 8 RT SYNC VREF SS iP1203 iP1203PbF VCC_bypass SS PGOOD V INS VINS PGOOD13 24 23 VIN V INS VIN VCC_bypass 6 10K R1 1 PGND 2 C16 PGND 3 VIN 4 12V 5 V IN 7 J1 17 PGND PGND PGND PGND PGND PGND 20 20 21 U1 10 9 VSWS FB CC 11 22 VSWS FBS 19 VSW 16 18 OCSET C9 0.018uF NI R20 2.49K R19 1.13k 1.13K R27 1K R26 NI R21 1K R2 R5 C11 470uF 6.3V Type III Compensation †† 100pF C14 FBS CC NI C7 FB C10 470uF 6.3V 1.0uH VSW L1 37.4K RROCSET OCSET C8 NI 0.1uF C13 1.5V iP1203PbF Fig. 24: Typical Application Schematic www.irf.com iP1203PbF 2X S IDE VIEW T OP VIEW 0.15 [.006] C 9 [0.355] 6 B NOT ES : 2.31 [.0909] 2.13 [.0839] A 1. 2. 3. 4. 5 DIMENS IONING & TOLERANCING PER AS ME Y14.5M-1994. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. CONT ROLLING DIMENS ION: MILLIMET ER LAND DES IGNATION PER JES D MO 222, S PP-010. PRIMARY DAT UM C IS S EAT ING PLANE. 6 BILAT ERAL T OLERANCE ZONE IS APPLIED TO EACH S IDE OF T HE PACKAGE BODY. 7 DET AILS OF T ERMINAL # 1 IDENTIFIER ARE OPT IONAL, BUT MUS T BE LOCAT ED WITHIN T HE ZONE INDICAT ED . THE T ERMINAL # 1 IDENT IFIER MAY BE EIT HER A MOLD OR MARKED FEAT URE . ORIENT AT ION CORNER ID 7 9 [0.355] e X 0.508 Y 0.800 (2) X Y 0.508 0.800 X 2.769 Y 1.778 X Y 2.261 2.261 X 1.016 Y 0.508 X 1.016 2.139 1.016 0.15 [.006] C 6 (3) 4.966 3.835 3.353 2.959 1.791 1.422 0.914 0.000 6.474 9.000 8.369 7.633 2X (4) (5) 0.000 0.758 0.892 1.380 1.833 1.870 3.021 4.243 4.461 4.522 15X K 15X R 12X e 7.489 8.352 9.000 0.889 (1) (6) Y X (7) X 2.261 2.032 Y 2.261 X 1.524 Y R 2.032 0.269 K 0.254 Y (8) (9) (10) LAYOUT NOTES : 1. MIRROR T HE EXACT LY MODULE PAD OPENING TO PCB LAYOUT . BOT T OM VIEW Fig. 25: Outline Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR technology products: AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss vs Current and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1043: Stabilize the Buck Converter with Transconductance Amplifier This paper explains how to stabilize a buck converter for Type II and Type III control loop compensation using transconductance amplifiers. AN-1047: Graphical solution to two branch heatsinking Safe Operating Area This paper is a suppliment to AN-1030 and explains how to use the double side Power Loss vs Current and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers iPOWIR Technology BGA and LGA Packages This paper discusses optimization of the layout design for mounting iPOWIR BGA and LGA packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations. Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as soldering, pick and place, reflow, cleaning and reworking recommendations. www.irf.com 21 iP1203PbF 0438 XXXX iP1203 iP1203PbF 0438 XXXX iP1203 iP1203PbF 0438 XXXX iP1203 iP1203PbF 16.0 (.630) 12.0 (.472) FEED DIRECTION NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541. iP1203, BGA iP1203PbF Fig. 26: Tape & Reel Information NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541. iP1203PbF, BGA 0538 XXXX iP1203PbF Fig. 27: Part Marking 22 www.irf.com iP1203PbF SQUEEGEE VIEW RECOMMENDED STENCIL OPENING ALL DIMENSIONS IN INCHES The recommended reflow peak temperature is 260°C. The total furnance time is approximately 5 minutes with approximately 10 seconds at the peak temperature. Fig.28: Recommended Solder Profile and Stencil Design This product has been designed and qualified for the industrial market. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice.8/06 www.irf.com 23