HANBit HMS1M32M8A/Z8A HAN SRAM MODULE 4Mbyte(1M x 32-Bit) , 64-Pin SIMM Design BIT Part No. HMS1M32M8A, HMS1M32Z8A GENERAL DESCRIPTION The HMS1M32M8A is a high-speed static random access memory (SRAM) module containing 1,048,576 words organized in a x32-bit configuration. The module consists of eight 1M x 4 SRAMs mounted on a 64-pin, doublesided, FR4-printed circuit board. Four chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes independently. Output enable (/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible. FEATURES PIN ASSIGNMENT Access times : 10, 12, 15, 17 and 20ns High-density 4MByte design High-reliability, high-speed design Single + 5V ±0.5V power supply Easy memory expansion with /CE and /OE functions All inputs and outputs are TTL-compatible Industry-standard pinout Part identification A18 DQ0 DQ1 DQ2 DQ3 Vcc A7 A8 A9 DQ4 DQ5 DQ6 DQ7 /WE A14 /CE1 /CE3 A16 Vss DQ16 DQ17 DQ18 DQ19 A10 A11 A12 A13 DQ20 DQ21 DQ22 DQ23 Vss - HMS1M32M8A : 64Pin SIMM Design - HMS1M32Z8A : 64Pin ZIP Design → Pin-Compatible with the HMS1M32M8A OPTIONS MARKING Timing 10ns access -10 12ns access -12 15ns access -15 17ns access -17 20ns access -20 Packages 64-pin SIMM M 64-pin ZIP Z 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Vss A19 DQ8 DQ9 DQ10 DQ11 A0 A1 A2 DQ12 DQ13 DQ14 DQ15 Vss A15 /CE2 /CE4 A17 /OE DQ24 DQ25 DQ26 DQ27 A3 A4 A5 Vcc A6 DQ28 DQ29 DQ30 DQ31 ZIP TOP VIEW 1 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A FUNCTIONAL BLOCK DIAGRAM 32 DQ0 - DQ31 20 A0 - A19 A0-19 A0-19 DQ 0-3 DQ 4-7 /WE /WE U1 /OE U5 /OE /CE /CE /CE1 A0-19 A0-19 DQ 8-11 DQ12-15 /WE /WE U2 /OE U6 /OE /CE /CE A0-19 /WE DQ16-19 /OE A0-19 /WE DQ20-23 /OE /CE2 U3 U7 /CE /CE /CE3 A0-19 A0-19 DQ24-27 /WE /WE /OE /OE DQ28-31 /WE U4 /OE /CE U8 /CE /CE4 TRUTH TABLE MODE /OE /CE /WE OUTPUT POWER STANDBY X H X HIGH-Z STANDBY NOT SELECTED H L H HIGH-Z ACTIVE READ L L H DOUT ACTIVE WRITE X L L DIN ACTIVE 2 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN,OUT -0.5V to +7.0V Voltage on Vcc Supply Relative to Vss VCC -0.5V to +7.0V Power Dissipation PD 8W TSTG -65oC to +150oC Voltage on Any Pin Relative to Vss Storage Temperature Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER * ( TA=0 to 70 o C ) SYMBOL MIN TYP. MAX Supply Voltage VCC 4.5V 5.0V 5.5V Ground VSS 0 0 0 Input High Voltage VIH 2.2 - Vcc+0.5V** Input Low Voltage VIL -0.5* - 0.8V VIL(Min.) = -2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA ** VIH(Min.) = Vcc+2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA DC AND OPERATING CHARACTERISTICS (1)(0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V ) PARAMETER Input Leakage Current Output Leakage Current SYMBO L TEST CONDITIONS VIN =Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC MIN MAX UNITS ILI -2 2 µA IL0 -2 2 µA 2.4 Output High Voltage IOH = -4.0Ma VOH Output Low Voltage IOL = 8.0Ma VOL V 0.4 V * Vcc=5.0V, Temp=25 oC DC AND OPERATING CHARACTERISTICS (2) MAX DESCRIPTION Power Supply Current: Operating Power Supply Current :Standby TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA SYMBOL -10 -12 -15 UNIT lCC 195 190 185 mA Min. Cycle, /CE=VIH lSB 50 50 50 mA f=0MHZ, /CE≥VCC-0.2V, VIN≥ VCC-0.2V or VIN≤0.2V lSB1 10 10 10 mA 3 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A CAPACITANCE DESCRIPTION TEST CONDITIONS SYMBOL MAX UNIT Input /Output Capacitance VI/O=0V CI/O 8 pF Input Capacitance VIN=0V CIN 7 pF * NOTE : Capacitance is sampled and not 100% tested AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V, unless otherwise specified) TEST CONDITIONS PARAMETER VALUE Input Pulse Level 0 to 3V Input Rise and Fall Time 3ns Input and Output Timing Reference Levels 1.5V Output Load See below Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ Output Load (A) VL=1.5V +5.0V 50Ω DOUT 480Ω DOUT Z0=50Ω 30pF 255Ω 5pF* READ CYCLE -10 PARAMETER -12 -15 SYMBOL UNIT MIN MAX MIN MAX MIN MAX Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Select to Output tCO - 10 - 12 - 15 ns Output Enable to Output tOE - 5 - 6 - 7 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 ns Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Select to Power Up Time tPU 0 - 0 - 0 - ns Chip Select to Power Down Time tPD - 10 12 - 15 ns 4 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A WRITE CYCLE -10 PARAMETER -12 -15 SYMBOL UNIT MIN MAX MIN MAX MIN MAX Write Cycle Time tWC 10 - 12 - 15 - ns Chip Select to End of Write tCW 7 - 8 - 10 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 7 - 8 - 10 - ns Write Pulse Width (/OE High) tWP 7 - 8 - 10 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 6 0 7 ns Data to Write Time Overlap tDW 5 - 6 - 7 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End of Write to Output Low-Z tOW 3 - 3 - 3 - ns TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE( Address Controlled)( /CE =/OE = VIL , /WE = VIH) tRC Address tAA tOH Data out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE ( /WE = VIH ) tRC Address tHZ(3,4,5) tAA tCO /CE tLZ(4,5) tOHZ tOE /OE tOH tOLZ Data Out Vcc Supply Current High-Z Data Valid lCC lSB tPD tPU 50% 50% 5 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A Notes (Read Cycle) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low. TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock ) tWC Address tAW tWR(5) /OE tCW(3) /CE tAS(4) tWP(2) /WE tDW tDH High-Z Data In Data Valid tOHZ tOW Data Out High-Z TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed) tWC Address tAW tWR(5) tCW(3) /CE tAS(4) tOH /WE tWP(2) tDW Data In tDH High-Z Data Valid tWHZ(6,7) tOW (10) (9) High-Z(8) Data Out 6 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A Notes(Write Cycle) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of wirte. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION /CE /WE /OE MODE I/O PIN SUPPLY CURRENT H X* X Not Select High-Z I SB, I SB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC Note: X means Don't Care 7 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A PACKAGING DIMMENSIONS SIMM Design 98.04 mm 10.16 mm 6.35 mm 16 mm 1 64 2.03 mm 1.02 mm 6.35 mm 6.35 mm 1.27 mm 3.34 mm 85.09 mm 2.54 mm 0.25 mm MAX MIN Gold : 1.04±0.10 mm 1.27 1.29±0.08 mm Solder : 0.914±0.10 mm (Solder & Gold Plating Lead) ZIP Design 89 mm CUT 1.5 mm 14 mm 64 1 6 mm 40 mm 2.54 mm 2 mm 90 mm 1.29±0.08 mm 2.5 mm 8 HANBit Electronics Co.,Ltd. HANBit HMS1M32M8A/Z8A ORDERING INFORMATION 1 2 3 HMS 4 5 6 7 8 1M 32 M 8A -15 15ns Access Time HANBit Component, 64PIN Memory Modules SIMM x32bit SRAM 1M 1. - Product Line Identifier HANBit ------------------------------------------------------ H 2. - Memory Modules 3. - SRAM 4. - Depth : 1M 5. - Width : x 32bit 6. - Package Code SIMM ------------------------------------------------------- M ZIP ------------------------------------------------------- Z 7. - Number of Memory Components------8, 64PIN -------------A 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns 9 HANBit Electronics Co.,Ltd.