HOLTEK HT66F017

Enhanced Flash Type 8-Bit MCU with EEPROM
HT66F016/HT66F017
HT68F016/HT68F017
Revision: 1.00
Date: May 14, 2012
Contents
Table of Contents
General Description ............................................................................7
Features ...............................................................................................7
CPU Features ........................................................................................................7
Peripheral Features ................................................................................................7
Technical Document ...........................................................................7
Selection Table ....................................................................................8
Block Diagram .....................................................................................8
Pin Assignment ...................................................................................9
Pin Description ..................................................................................10
HT66F016/HT66F017 ..........................................................................................10
HT68F016/HT68F017...........................................................................................11
Absolute Maximum Ratings .............................................................11
D.C. Characteristics ..........................................................................12
A.C. Characteristics ..........................................................................14
A/D Converter Characteristics .........................................................15
Comparator Electrical Characteristics ............................................15
Power-on Reset Characteristics ......................................................16
Bandgap Reference (Vbg) Characteristic Curve ............................16
System Architecture .........................................................................17
Clocking and Pipelining ........................................................................................17
Program Counter..................................................................................................18
Stack ....................................................................................................................18
Arithmetic and Logic Unit - ALU ...........................................................................18
Flash Program Memory ....................................................................19
Structure...............................................................................................................19
Special Vectors.....................................................................................................19
Look-up Table.......................................................................................................19
Table Program Example .......................................................................................19
In Circuit Programming.........................................................................................20
RAM Data Memory.............................................................................21
Structure...............................................................................................................21
Rev. 1.00
2
May 14, 2012
Contents
Special Function Register Description ...........................................23
Indirect Addressing Registers - IAR0, IAR1..........................................................23
Memory Pointers - MP0, MP1 ..............................................................................23
Bank Pointer - BP ................................................................................................24
Accumulator - ACC ..............................................................................................24
Program Counter Low Register - PCL..................................................................24
Look-up Table Registers - TBLP, TBHP, TBLH.....................................................24
Status Register - STATUS ...................................................................................25
EEPROM Data Memory .....................................................................26
EEPROM Data Memory Structure ........................................................................26
EEPROM Registers..............................................................................................26
Reading Data from the EEPROM .........................................................................28
Writing Data to the EEPROM ...............................................................................28
Write Protection ....................................................................................................28
EEPROM Interrupt ...............................................................................................28
Programming Considerations ...............................................................................28
Oscillator............................................................................................30
Oscillator Overview...............................................................................................30
System Clock Configurations................................................................................30
External Crystal/Ceramic Oscillator - HXT ...........................................................31
Internal RC Oscillator - HIRC ...............................................................................31
Internal 32kHz Oscillator - LIRC...........................................................................31
Supplementary Oscillators....................................................................................31
Operating Modes and System Clocks .............................................32
System Clocks......................................................................................................32
System Operation Modes .....................................................................................33
Control Register ...................................................................................................34
Fast Wake-up .......................................................................................................35
Operating Mode Switching and Wake-up..............................................................35
NORMAL Mode to SLOW Mode Switching...........................................................36
SLOW Mode to NORMAL Mode Switching...........................................................37
Entering the SLEEP0 Mode..................................................................................37
Entering the SLEEP1 Mode..................................................................................38
Entering the IDLE0 Mode .....................................................................................38
Entering the IDLE1 Mode .....................................................................................38
Standby Current Considerations...........................................................................38
Wake-up...............................................................................................................39
Programming Considerations ...............................................................................39
Watchdog Timer ................................................................................40
Watchdog Timer Clock Source .............................................................................40
Watchdog Timer Control Register.........................................................................40
Watchdog Timer Operation...................................................................................40
Watchdog Timer Enable/Disable Control ..............................................................40
Rev. 1.00
3
May 14, 2012
Contents
Reset and Initialisation .....................................................................42
Reset Functions ...................................................................................................42
Reset Initial Conditions .........................................................................................43
Input/Output Ports.............................................................................46
Pull-High Resistors ...............................................................................................46
Port A Wake-up ....................................................................................................47
I/O Port Control Register ......................................................................................47
Pin-remapping Functions......................................................................................48
Pin-remapping Registers ......................................................................................48
I/O Pin Structures .................................................................................................48
Programming Considerations ...............................................................................48
Timer Modules - TM..........................................................................50
Introduction ..........................................................................................................50
TM Operation .......................................................................................................50
TM Clock Source..................................................................................................50
TM Interrupts ........................................................................................................51
TM External Pins ..................................................................................................51
Programming Considerations ...............................................................................52
Compact Type TM - CTM..................................................................53
Compact TM Operation ........................................................................................53
Compact Type TM Register Description ...............................................................54
CTM Register List.................................................................................................54
Compact Type TM Operating Modes ....................................................................58
Compare Match Output Mode ..............................................................................58
Timer/Counter Mode.............................................................................................60
PWM Output Mode...............................................................................................60
Standard Type TM - STM..................................................................62
Standard TM Operation ........................................................................................62
Standard Type TM Register Description ...............................................................62
STM Register List.................................................................................................63
Standard Type TM Operating Modes....................................................................67
Compare Output Mode .........................................................................................67
Timer/Counter Mode.............................................................................................69
PWM Output Mode...............................................................................................69
Single Pulse Mode ...............................................................................................71
Capture Input Mode..............................................................................................72
Analog to Digital Converter..............................................................73
A/D Overview .......................................................................................................73
A/D Converter Register Description ......................................................................73
A/D Converter Data Registers ADRL, ADRH .......................................................73
A/D Converter Control Registers - ADCR0, ADCR1, ACERL...............................73
A/D Operation.......................................................................................................77
A/D Input Pins ......................................................................................................78
Rev. 1.00
4
May 14, 2012
Contents
Summary of A/D Conversion Steps ......................................................................78
Programming Considerations ...............................................................................79
A/D Transfer Function...........................................................................................79
A/D Programming Example ..................................................................................79
Comparators ......................................................................................82
Comparator Operation..........................................................................................82
Comparator Interrupt ............................................................................................82
Programming Considerations ...............................................................................82
Interrupts............................................................................................84
Interrupt Registers ................................................................................................84
Interrupt Operation ...............................................................................................88
External Interrupt ..................................................................................................90
Comparator Interrupt ............................................................................................90
Multi-function Interrupt ..........................................................................................90
A/D Converter Interrupt ........................................................................................90
Time Base Interrupts ............................................................................................90
EEPROM Interrupt ...............................................................................................92
LVD Interrupt ........................................................................................................92
TM Interrupts ........................................................................................................92
Interrupt Wake-up Function ..................................................................................92
Programming Considerations ...............................................................................93
Low Voltage Detector - LVD .............................................................94
LVD Register ........................................................................................................94
LVD Operation......................................................................................................95
Configuration Options ......................................................................96
Application Circuits ..........................................................................96
Instruction Set ...................................................................................97
Introduction ..........................................................................................................97
Instruction Timing .................................................................................................97
Moving and Transferring Data ..............................................................................97
Arithmetic Operations ...........................................................................................97
Logical and Rotate Operations .............................................................................97
Branches and Control Transfer.............................................................................97
Bit Operations.......................................................................................................98
Table Read Operations.........................................................................................98
Other Operations..................................................................................................98
Instruction Set Summary ......................................................................................98
Instruction Definition ......................................................................100
Rev. 1.00
5
May 14, 2012
Contents
Package Information .......................................................................110
16-pin DIP (300mil) Outline Dimensions .............................................................110
16-pin NSOP (150mil) Outline Dimensions .........................................................112
16-pin SSOP (150mil) Outline Dimensions .........................................................113
Product Tape and Reel Specifications.................................................................114
Rev. 1.00
6
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Enhanced Flash Type 8-Bit MCU with EEPROM
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features
Peripheral Features
· Operating Voltage:
· Flash Program Memory: up to 2K´16
·
·
·
·
·
·
·
·
·
·
fSYS= 8MHz: 2.2V~5.5V
fSYS= 12MHz: 2.7V~5.5V
fSYS= 20MHz: 4.5V~5.5V
Up to 0.2ms instruction cycle with 20MHz system
clock at VDD=5V
Power down and wake-up functions to reduce power
consumption
Three oscillators
- External crystal -- HXT
- Internal RC --HIRC
- Internal 32kHz RC -- LIRC
Multi-mode operation: NORMAL, SLOW, IDLE and
SLEEP
Fully integrated internal 8MHz oscillator requires no
external components
All instructions executed in one or two instruction
cycles
Table read instructions
63 powerful instructions
8 subroutine nesting levels
Bit manipulation instruction
· RAM Data Memory: up to 128´8
· EEPROM Memory: 64´8
· Watchdog Timer function
· 14 bidirectional I/O lines
· Two external interrupt lines shared with I/O pins
· Multiple Timer Module for time measure, input
·
·
·
·
capture, compare match output, PWM output or
single pulse output functions
Comparator function
Dual Time-Base functions for generation of fixed time
interrupt signals
Low voltage reset function
Low voltage detect function
· 4-channel 12-bit resolution A/D converter
· Package types: 16-pin DIP/NSOP/SSOP
General Description
The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers. Offering use rs t h e c onv e n i enc e of Fl a s h M e m o r y
multi-programming features, these devices also include
a wide range of functions and features. Other memory
includes an area of RAM Data Memory as well as an
area of EEPROM memory for storage of non-volatile
data such as serial numbers, calibration data etc.
A full choice of HXT, HIRC and LIRC oscillator functions
are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically
between a range of operating modes using different
clock sources gives users the ability to optimise
microcontroller operation and minimize power consumption.
Analog features include a multi-channel 12-bit A/D converter and a comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse
generation and PWM generation functions. Protective
features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that
reliable operation is maintained in hostile electrical environments.
The inclusion of flexible I/O programming features,
Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering, environmental
monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in
addition to many others.
Rev. 1.00
7
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Selection Table
Most features are common to all devices. The main feature distinguishing them is the A/D Converter only. The following
table summarises the main features of each device.
Device
Program
Memory
Data
Memory
Data
EEPROM
I/O
A/D
16-bit
Timer
Module
Time
Base
Comparator
Stack
Package
HT68F016
1Kx16
64x8
64x8
14
¾
STMx1
2
1
4
16DIP/NSOP/SSOP
HT68F017
2Kx16
128x8
64x8
14
¾
CTMx1
STMx1
2
1
8
16DIP/NSOP/SSOP
HT66F016
1Kx16
64x8
64x8
14
12-bitx4
STMx1
2
1
4
16DIP/NSOP/SSOP
HT66F017
2Kx16
128x8
64x8
14
12-bitx4
CTMx1
STMx1
2
1
8
16DIP/NSOP/SSOP
Block Diagram
L o w
V o lta g e
D e te c t
L o w
V o lta g e
R e s e t
F la s h /E E P R O M
P r o g r a m m in g
C ir c u itr y
F la s h
P ro g ra m
M e m o ry
W a tc h d o g
T im e r
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
S ta c k
E E P R O M
D a ta
M e m o ry
E x te rn a l
R C /X ta l
O s c illa to r s
R A M
D a ta
M e m o ry
T im e B a s e
In te rru p t
C o n tr o lle r
In te rn a l R C
O s c illa to r s
1 2 - B it A /D
C o n v e rte r
C o m p a ra to r
I/O
Rev. 1.00
T im e r
M o d u le s
8
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Pin Assignment
P B 2
1
1 6
P B 3
P B 1 /[T P 1 ]
2
1 5
P B 4
P B 0
3
1 4
P B 5
P A 3 /IN T 0 /T C K 1 /A N 3
4
1 3
P A 4 /[IN T 1 ]/T P 1
P A 2 /[IN T 0 ]/[T C K 1 ]/C X /A N 2
5
1 2
P A 5 /IN T 1 /O S C 2
P A 1 /C -/A N 1 /V R E F
6
1 1
P A 6 /[T P 1 ]/O S C 1
P A 0 /C + /A N 0
7
1 0
P A 7 /[T P 1 ]
V S S /A V S S
8
9
V D D /A V D D
H T 6 6 F 0 1 6
1 6 D IP -A /N S O P -A /S S O P -A
P B 2
1
1 6
P B 3
P B 1 /[T C K 0 ]/[T P 1 ]
2
1 5
P B 4
P B 0 /[T P 0 ]
3
1 4
P B 5
P A 3 /IN T 0 /T C K 1 /T P 0 /A N 3
4
1 3
P A 4 /[IN T 1 ]/T C K 0 /T P 1
P A 2 /[IN T 0 ]/[T C K 1 ]/[T P 0 ]/C X /A N 2
5
1 2
P A 5 /IN T 1 /[T P 0 ]/O S C 2
P A 1 /C -/A N 1 /V R E F
6
1 1
P A 6 /[T C K 0 ]/[T P 1 ]/O S C 1
P A 0 /C + /A N 0
7
1 0
P A 7 /[T C K 0 ]/[T P 1 ]
V S S /A V S S
8
9
V D D /A V D D
H T 6 6 F 0 1 7
1 6 D IP -A /N S O P -A /S S O P -A
P B 2
1
1 6
P B 3
P B 1 /[T P 1 ]
2
1 5
P B 4
P B 0
3
1 4
P B 5
P A 3 /IN T 0 /T C K 1
4
1 3
P A 4 /[IN T 1 ]/T P 1
P A 2 /[IN T 0 ]/[T C K 1 ]/C X
5
1 2
P A 5 /IN T 1 /O S C 2
P A 1 /C 6
1 1
P A 6 /[T P 1 ]/O S C 1
P A 0 /C +
7
1 0
P A 7 /[T P 1 ]
V S S /A V S S
8
9
V D D /A V D D
H T 6 8 F 0 1 6
1 6 D IP -A /N S O P -A /S S O P -A
P B 2
1
1 6
P B 3
P B 1 /[T C K 0 ]/[T P 1 ]
2
1 5
P B 4
P B 0 /[T P 0 ]
3
1 4
P B 5
P A 3 /IN T 0 /T C K 1 /T P 0
4
1 3
P A 4 /[IN T 1 ]/T C K 0 /T P 1
P A 2 /[IN T 0 ]/[T C K 1 ]/[T P 0 ]/C X
5
1 2
P A 5 /IN T 1 /[T P 0 ]/O S C 2
P A 1 /C 6
1 1
P A 6 /[T C K 0 ]/[T P 1 ]/O S C 1
P A 0 /C +
7
1 0
P A 7 /[T C K 0 ]/[T P 1 ]
V S S /A V S S
8
9
V D D /A V D D
H T 6 8 F 0 1 7
1 6 D IP -A /N S O P -A /S S O P -A
Note:
1. Bracketed pin names indicate non-default pinout remapping locations.
2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the
²/² sign can be used for higher priority.
3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 1.00
9
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1
etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such
as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet.
The following tables only include the pins which are directly related to the MCU. The pin descriptions of the additional
peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional description.
HT66F016, HT68F016
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
ST
CMOS
¾
¾
PA0~PA7
Port A
PAWU
PAPU
PB0~PB5
Port B
PBPU
ST
CMOS
AN0~AN3
A/D converter input
ACERL
AN
¾
PA0~PA3
VREF
A/D converter reference input
ADCR1
AN
¾
PA1
C-
Comparator input
AN
¾
PA1
C+
Comparator input
AN
¾
PA0
CX
Comparator output
¾
CMOS
PA2
TCK1
TM1 input
PRM
ST
¾
TP1
TM1 I/O
PRM
TMPC
ST
CMOS
INT0
External Interrupt 0
INTC0
INTEG
ST
¾
PA3 or PA2
INT1
External Interrupt 1
INTC2
INTEG
ST
¾
PA5 or PA4
OSC1
HXT pin
CO
HXT
¾
PA6
OSC2
HXT pin
CO
¾
HXT
PA5
VDD
Power supply
¾
PWR
¾
¾
VSS
Ground
¾
PWR
¾
¾
Note:
CPC
PA2 or PA3
PA4, PA6, PA7 or PB1
I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output
AN: Analog input pin
HXT: High frequency crystal oscillator
HT68F016 doesn¢t have AN0~AN3, VREF pin.
Rev. 1.00
10
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
HT66F017, HT68F017
Pin Name
Function
OP
I/T
O/T
Pin-Shared Mapping
PA0~PA7
Port A
PAWU
PAPU
ST
CMOS
¾
PB0~PB5
Port B
PBPU
ST
CMOS
¾
AN0~AN3
A/D converter input
ACERL
AN
¾
PA0~PA3
VREF
A/D converter reference input
ADCR1
AN
¾
PA1
C-
Comparator input
AN
¾
PA1
C+
Comparator input
AN
¾
PA0
CX
Comparator output
¾
CMOS
PA2
TCK0
TM0 input
PRM
ST
¾
PA4, PA6, PA7or PB1
TCK1
TM1 input
PRM
ST
¾
PA2 or PA3
TP0
TM0 I/O
PRM
TMPC
ST
CMOS
PA2, PA3, PA5 or PB0
TP1
TM1 I/O
PRM
TMPC
ST
CMOS
PA4, PA6, PA7 or PB1
INT0
External Interrupt
INTC0
INTEG
ST
¾
PA3 or PA2
INT1
External Interrupt
INTC2
INTEG
ST
¾
PA5 or PA4
OSC1
HXT pin
CO
HXT
¾
PA6
OSC2
HXT pin
CO
¾
HXT
PA5
VDD
Power supply *
¾
PWR
¾
¾
AVDD
A/D converter power supply *
¾
PWR
¾
¾
VSS
Ground **
¾
PWR
¾
¾
AVSS
A/D converter ground **
¾
PWR
¾
¾
Note:
CPC
I/T: Input type; O/T: Output type
OP: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option; ST: Schmitt Trigger input
CMOS: CMOS output
HXT: High frequency crystal oscillator
*: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together
internally with VDD.
**: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally
with VSS.
HT68F017 doesn¢t have AN0~AN3, VREF pin.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................100mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
11
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
VDD
Operating Voltage
(HXT, HIRC)
¾
3V
5V
3V
IDD1
Operating Current (HXT),
(fSYS=fH, fS=fSUB=fLIRC)
5V
3V
5V
5V
IDD2
IDD3
IIDLE0
Operating Current (HIRC),
(fSYS=fH, fS=fSUB=fLIRC)
3V
Operating Current (LIRC),
(fSYS=fL=fLIRC, fS=fSUB=fLIRC)
3V
IDLE0 Mode Standby Current
(LIRC on)
3V
IDLE1 Mode Standby Current
(HXT)
IIDLE1
ISLEEP1
VIL
VIH
5V
5V
3V
5V
3V
fSYS=8MHz
2.2
¾
5.5
V
fSYS=12MHz
2.7
¾
5.5
V
fSYS=20MHz
4.5
¾
5.5
V
¾
1.0
1.5
mA
¾
2.5
4.0
mA
¾
1.5
2.5
mA
¾
3.5
5.5
mA
¾
2.0
3.0
mA
¾
4.5
7.0
mA
¾
5.5
8.5
mA
¾
1.4
2.1
mA
¾
2.4
3.6
mA
¾
10
20
mA
¾
30
50
mA
¾
1.5
3.0
mA
¾
3.0
6.0
mA
¾
0.6
1.0
mA
¾
1.3
2.0
mA
¾
0.9
1.4
mA
¾
1.2
1.8
mA
¾
¾
1
mA
¾
¾
2
mA
¾
1.5
3.0
mA
¾
2.5
5.0
mA
0
¾
0.2VDD
V
No load, fH=8MHz,
ADC off, WDT enable
No load, fH=12MHz,
ADC off, WDT enable
No load, fH=16MHz,
ADC off, WDT enable
No load, fH=20MHz,
ADC off, WDT enable
No load, fH=8MHz,
ADC off, WDT enable
No load, ADC off,
WDT enable
No load, ADC off, WDT
enable
No load, ADC off, WDT
enable, fSYS=12MHz on
No load, ADC off, WDT
disable
SLEEP1 Mode Standby Current 3V
(LIRC on)
5V
No load, ADC off, WDT
enable
Input Low Voltage for I/O Ports, ¾
TC and INT
5V
¾
Input High Voltage for I/O Ports, ¾
TC and INT
5V
¾
LVR Voltage Level
Rev. 1.00
Unit
SLEEP0 Mode Standby Current 3V
(LIRC off)
5V
VLVR2
VLVR4
Max.
5V
VLVR1
VLVR3
Typ.
No load, ADC off, WDT
enable, fSYS=8MHz on
IDLE1 Mode Standby Current
(HIRC)
ISLEEP0
5V
Min.
Conditions
¾
0
0.8VDD
1.5
¾
VDD
+5%
V
3.5
V
5.0
LVR Enable, 2.10V option
-5%
2.10
LVR Enable, 2.55V option
-5%
2.55
+5%
V
LVR Enable, 3.15V option
-5%
3.15
+5%
V
LVR Enable, 3.80V option
-5%
3.80
+5%
V
12
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
Conditions
VLVD1
LVDEN=1, VLVD=2.0V
-5%
2.00
+5%
V
VLVD2
LVDEN=1, VLVD=2.2V
-5%
2.20
+5%
V
VLVD3
LVDEN=1, VLVD=2.4V
-5%
2.40
+5%
V
LVDEN=1, VLVD=2.7V
-5%
2.70
+5%
V
LVDEN=1, VLVD=3.0V
-5%
3.00
+5%
V
VLVD6
LVDEN=1, VLVD=3.3V
-5%
3.30
+5%
V
VLVD7
LVDEN=1, VLVD=3.6V
-5%
3.60
+5%
V
VLVD8
LVDEN=1, VLVD=4.0V
-5%
4.00
+5%
V
LVR disable, LVDEN=1
¾
75
120
mA
LVR enable, LVDEN=1
¾
90
150
mA
3V
IOL=9mA
¾
¾
0.3
V
5V
IOL=20mA
¾
¾
0.5
V
3V
IOH=-3.2mA
2.7
¾
¾
V
5V
IOH=-7.4mA
4.5
¾
¾
V
20
60
100
kW
10
30
50
kW
VLVD4
LVD Voltage Level
VLVD5
ILVD1
¾
ILVD2
Additional Power Consumption
¾
if LVR and LVD is Used
VOL
Output Low Voltage I/O Port
VOH
Output High Voltage I/O Port
3V
Pull-high Resistance for I/O
Ports
5V
V125
1.25V Reference with Buffer
Voltage
¾
¾
-3%
1.25
+3%
V
I125
Additional Power Consumption
if 1.25V Reference with Buffer is ¾
used
¾
¾
200
300
mA
RPH
Rev. 1.00
¾
13
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
2.2V~5.5V
DC
¾
8
MHz
2.7V~5.5V
DC
¾
12
MHz
4.5V~5.5V
DC
¾
20
MHz
2.2V~5.5V
0.4
¾
8
MHz
2.7V~5.5V
0.4
¾
12
MHz
4.5V~5.5V
0.4
¾
20
MHz
3.0V~
Ta= -40°C~85°C
5.5V
-6%
8
+6%
MHz
4.5V~
Ta= -40°C~85°C
5.5V
-2%
8
+2%
MHz
-10%
32
+10%
kHz
VDD
¾
fCPU
Operating Clock
fSYS
System Clock (HXT)
fHIRC
¾
¾
Conditions
System Clock (HIRC)
fLIRC
System Clock (LIRC)
5V
tINT
Interrupt Pulse Width
¾
¾
10
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
120
240
480
ms
tLVD
Low Voltage Width to Interrupt
¾
¾
20
45
90
ms
tLVDS
LVDO stable time
¾
For all VLVD, LVR disable
200
¾
¾
ms
tBGS
VBG Turn on Stable Time
¾
¾
200
¾
¾
ms
tTIMER
TCKn Input Pulse Width
¾
¾
0.3
¾
¾
ms
tSRESET
Software Reset Width to Reset
¾
¾
45
90
120
ms
System Reset Delay Time
(Power on Reset)
¾
¾
25
50
100
ms
System Reset Delay Time (Any
Reset except Power on Reset)
¾
¾
8.3
16.7
33.3
ms
fSYS=HXT OSC
128
¾
¾
fSYS=HIRC OSC
16
¾
¾
fSYS=LIRC OSC
2
¾
¾
tRSTD
Ta=25°C
System Start-up Timer Period
(Wake-up from HALT, fSYS off at
HALT State)
¾
System Start-up Timer Period
(Wake-up from HALT, fSYS on at
HALT State)
¾
¾
2
¾
¾
tSYS
tEERD
EEPROM Read Time
¾
¾
¾
2
4
tSYS
tEEWR
EEPROM Write Time
¾
¾
¾
2
4
ms
tSST
Note:
tSYS
1. tSYS=1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS and located as close to the device as possible.
Rev. 1.00
14
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
A/D Converter Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
2.7
¾
5.5
V
Conditions
AVDD
A/D Converter Operating Voltage
¾
VADI
A/D Converter Input Voltage
¾
¾
0
¾
VREF
V
VREF
A/D Converter Reference Voltage
¾
¾
2
¾
AVDD
V
DNL
Differential Non-linearity
5V
tADCK= 1.0ms
¾
±1
±2
LSB
INL
Integral Non-linearity
5V
tADCK= 1.0ms
¾
±2
±4
LSB
IADC
Additional Power Consumption if
A/D Converter is Used
3V
No load, tADCK= 0.5ms
¾
0.90
1.35
mA
5V
No load, tADCK= 0.5ms
¾
1.20
1.80
mA
0.5
¾
10
ms
VREF=AVDD
tADCK
A/D Converter Clock Period
2.2~
5.5V
tADC
A/D Conversion Time (Include
Sample and Hold Time)
2.2~
12-bit A/D Converter
5.5V
¾
16
¾
tADCK
tADS
A/D Converter Sampling Time
2.2~
5.5V
¾
¾
4
¾
tADCK
tON2ST
A/D Converter On-to-Start Time
2.2~
5.5V
¾
2
¾
¾
ms
¾
Comparator Electrical Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VCMP
Comparator Operating Voltage
ICMP
Comparator Operating Current
Min.
Typ.
Max.
Unit
¾
2.2
¾
5.5
V
3V
¾
¾
37
56
mA
5V
¾
¾
130
200
mA
VDD
Conditions
¾
VCMPOS
Comparator Input Offset Voltage
¾
¾
-10
¾
10
mV
VHYS
Hysteresis Width
¾
¾
20
40
60
mV
VCM
Comparator Common Mode
Voltage Range
¾
¾
VSS
¾
VDD-1.4V
V
AOL
Comparator Open Loop Gain
¾
¾
60
80
¾
dB
tPD
Comparator Response Time
¾
¾
370
560
ns
Note:
With 100mV overdrive
(Note)
Measured with comparator one input pin at VCM = (VDD-1.4)/2 while the other pin input transition from VSS to
(VCM +100mV) or from VDD to (VCM -100mV).
Rev. 1.00
15
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Power-on Reset Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RPOR AC
VDD Raising Rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Bandgap Reference (Vbg) Characteristic Curve
1 .2 7 0
1 .2 6 5
-4 5 °C
1 .2 6 0
B a n d G a p V o lta g e
1 .2 5 5
2 5 °C
1 .2 5 0
9 0 °C
1 .2 4 5
1 .2 4 0
1 .2 3 5
1 .2 3 0
1 .2 2 5
1 .2 2 0
1 .2 1 5
2 .7 V
3 .1 5 V
5 .6 V
O p e r a tin g V o lta g e
Rev. 1.00
16
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
System Architecture
generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1
clock during which time a new instruction is fetched. The
remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions here the contents of the Program Counter are changed, such as subroutine calls or jumps, in
which case the instruction will take one more instruction
cycle to execute.
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take
advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all instruction set operations, which carries
out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal
data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes
the device suitable for low-cost, high-volume production
for controller applications.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Clocking and Pipelining
The main system clock, derived from either a HXT,
HIRC or LIRC oscillator is subdivided into four internally
fS Y S
C lo c k )
(S y s te m
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.00
17
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Program Counter
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Only the
lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is overflow, the first Program Counter save in
the stack will be lost.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
S ta c k L e v e l 3
Program Counter
Device
Program Counter
High Byte
PCL Register
HT66F016
HT68F016
PC9~PC8
PCL7~PCL0
HT66F017
HT68F017
PC10~PC8
PCL7~PCL0
B o tto m
o f S ta c k
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register.
By transferring data directly into this register, a short program jump can be executed directly, however, as only
this low byte is available for manipulation, the jumps are
limited to the present page of memory, that is 256 locations. When such program jumps are executed it should
also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching,
so an extra cycle is needed to pre-fetch.
P ro g ra m
M e m o ry
S ta c k L e v e l N
Device
Program Counter
Stack Levels
HT66F016, HT68F016
4
HT66F017, HT68F017
8
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
Stack
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has multiple levels depending upon the device
and is neither part of the data nor part of the program
space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or
interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a
subroutine or an interrupt routine, signaled by a return
instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
Rev. 1.00
C o u n te r
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
18
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Flash Program Memory
byte from the Program Memory will be transferred to the
user defined Data Memory register [m] as specified in
the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
The Program Memory is the location where the user
code or program is stored. For this device series the
Program Memory is Flash type, which means it can be
programmed and re-programmed a large number of
times, allowing the user the convenience of code modification on the same device. By using the appropriate
programming tools, these Flash devices offer users the
flexibility to conveniently debug and develop their applications while also offering a means of field programming
and updating.
The accompanying diagram illustrates the addressing
data flow of the look-up table.
Structure
T B L P R e g is te r
The Program Memory has a capacity of 2K´16 bits. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by a separate
table pointer register.
Device
Capacity
HT66F016, HT68F016
1K´16
HT66F017, HT68F017
2K´16
0 0 0 0 H
0 0 0 4 H
R e g is te r T B L H
H ig h B y te
D a ta
1 6 b its
U s e r S e le c te d
R e g is te r
L o w
B y te
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG
statement is ²700H² which refers to the start address of
the last page within the 2K words Program Memory of
the device. The table pointer is setup here to have an initial value of ²06H². This will ensure that the first data
read from the data table will be at the Program Memory
address ²706H² or 6 locations after the start of the last
page. Note that the value for the table pointer is referenced to the first address of the present page if the
²TABRD [m]² instruction is being used. The high byte of
the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the
²TABRD [m]² instruction is executed.
R e s e t
In te rru p t
V e c to r
1 6 b its
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is
reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will
jump to this location and begin execution.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the address of the look up data
to be retrieved in the table pointer register, TBLP and
TBHP. These registers define the total address of the
look-up table.
After setting up the table pointer, the table data can be
retrieved from the Program Memory using the
²TABRD[m]² or ²TABRDL[m]² instructions, respectively.
When the instruction is executed, the lower order table
Rev. 1.00
M e m o ry
Table Program Example
0 3 F F H
0 7 F F H
P ro g ra m
A d d re s s
L a s t p a g e o r
T B H P R e g is te r
19
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· Table Read Program Example
tempreg1 db
?
; temporary register #1
tempreg2 db
?
; temporary register #2
:
:
mov a,06h
; initialise low table pointer - note that this address
mov tblp,a
; is referenced
mov a,07h
; initialise high table pointer
tbhp,a
:
:
tabrd tempreg1
; transfers value in table referenced by table pointer data at program
; memory address ²706H² transferred to tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrd tempreg2
;
;
;
;
:
:
org 700h
transfers value in table referenced by table pointer data at program
memory address ²705H² transferred to tempreg2 and TBLH in this
example the data ²1AH² is transferred to tempreg1 and data ²0FH² to
register tempreg2
; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
In Circuit Programming
The Program Memory can be programmed serially
in-circuit using this 5-wire interface. Data is downloaded
and uploaded serially on a single pin with an additional
line for the clock. Two additional lines are required for
the power supply and one line for the reset. The technical details regarding the in-circuit programming of the
devices are beyond the scope of this document and will
be supplied in supplementary literature.
The provision of Flash type Program Memory provides
the user with a means of convenient and easy upgrades
and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a
means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with
the possibility of manufacturing their circuit boards complete with a programmed or un-programmed
microcontroller, and then programming or upgrading the
program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal
and re-insertion of the device.
Holtek
Writer Pins
MCU
Programming Pins
Pin
Description
ICPMS
PA7
Programming
Mode Select
ICPDA
PA0
Programming
Serial Data
ICPCK
PA2
Programming
Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
During the programming process the ICPMS pin will be
held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0
and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no
other outputs are connected to these two pins
Programmer and MCU Pins
Rev. 1.00
20
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
M C U
P r o g r a m m in g P in s
W r ite r P in s
8 0 H
B a n k 1
G e n e ra l
P u rp o s e
D a ta M e m o ry
U n u s e d
V D D
V D D
P A 7
IC P M S
P A 0
IC P D A
IC P C K
P A 2
V S S
V S S
*
*
n F H
N o te : G e n e ra l P u rp o s e D a ta M e m o ry s p a c e :
8 0 H ~ B F H fo r H T 6 6 F 0 1 6 /H T 6 8 F 0 1 6
8 0 H ~ F F H fo r H T 6 6 F 0 1 7 /H T 6 8 F 0 1 7
General Purpose Data Memory
*
The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read
and write accessible under program control.
T o o th e r C ir c u it
Note:
B a n k 0
* may be resistor or capacitor. The resistance
of * must be greater than 1kW or the capacitance
of * must be less than 1nF.
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored.
The overall Data Memory is subdivided into two banks
for all the devices. The Special Purpose Data Memory
registers are accessible in all banks, with the exception
of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data
Memory banks is achieved by setting the Bank Pointer
to the correct value. The start address of the Data Memory for all devices is the address 00H.
Structure
Divided into two sections, the first of these is an area of
RAM, known as the Special Function Data Memory. Here
are located registers which are necessary for correct operation of the device. Many of these registers can be read
from and written to directly under program control, however, some remain protected from user manipulation.
Device
Capacity
Bank 0
Bank 1
HT66F016
HT68F016
64´8
80H~BFH Unimplemented
HT66F017
HT68F017
128´8
80H~FFH Unimplemented
General Purpose Data Memory Structure
Rev. 1.00
21
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
B a n k 0
B a n k 0
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
B a n k 1
R 0
P 0
R 1
P 1
B P
A C C
P C L
T B L P
T B L H
T B H P
S T A T U S
S M O D
L V D C
IN T E G
IN T C 0
IN T C 1
IN T C 2
M F I0
M F I1
M F I2
P A
P A C
P A P U
P A W U
P R M
T M P C
W D T C
T B C
U n u s e d
U n u s e d
E E A
E E D
IA
M
IA
M
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 C H
3 D H
3 E H
3 F H
4 0 H
4 1 H
7 F H
B a n k 1
A D R L
A D R H
A D C R 0
A D C R 1
A C E R L
C P C
C T R L
L V R C
U n u s e d
U n u s e d
U n u s e d
U n u s e d
U n u s e d
U n u s e d
U n u s e d
T M 1 C 0
T M 1 C 1
T M 1 D L
T M 1 D H
T M 1 A L
T M 1 A H
T M 1 R P
U n u s e d
P B
P B C
P B P U
U n u s e d
E E C
U n u s e d
: U n u s e d , re a d a s "0 0 "
HT66F016/HT68F016 Special Purpose Data Memory
Note: note: address 20H~24H are unimplemented for HT68F016
B a n k 0
B a n k 0
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
B a n k 1
IA R 0
M P 0
IA R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
T B H P
S T A T U S
S M O D
L V D C
IN T E G
IN T C 0
IN T C 1
IN T C 2
M F I0
M F I1
M F I2
P A
P A C
P A P U
P A W U
P R M
T M P C
W D T C
T B C
U n u s e d
U n u s e d
E E A
E E D
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 C H
3 D H
3 E H
3 F H
4 0 H
4 1 H
7 F H
B a n k 1
A D R L
A D R H
A D C R 0
A D C R 1
A C E R L
C P C
C T R L
L V R C
T M 0 C 0
T M 0 C 1
T M 0 D L
T M 0 D H
T M 0 A L
T M 0 A H
T M 0 R P
T M 1 C 0
T M 1 C 1
T M 1 D L
T M 1 D H
T M 1 A L
T M 1 A H
T M 1 R P
U n u s e d
P B
P B C
P B P U
U n u s e d
E E C
U n u s e d
: U n u s e d , re a d a s "0 0 "
HT66F017/HT68F017 Special Purpose Data Memory
Note: note: address 20H~24H are unimplemented for HT68F017
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Memory Pointers - MP0, MP1
Special Function Register Description
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in
the same way as normal registers providing a convenient way with which to address and track data. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to, is the address specified by
the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data
from Bank 0, while MP1 and IAR1 are used to access
data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks
must be addressed indirectly using MP1 and IAR1. Note
that for this series of devices, the Memory Pointers,
MP0 and MP1, are both 8-bit registers and used to access the Data Memory together with their corresponding
indirect addressing registers IAR0 and IAR1.
Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this
section.
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank
0 while the IAR1 and MP1 register pair can access data
from any bank. As the Indirect Addressing Registers are
not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ²00H²
and writing to the registers indirectly will result in no operation.
The following example shows how to clear a section of
four Data Memory locations already defined as locations adres1 to adres4.
· Indirect Addressing Program Example
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h
mov block,a
mov a,offset adres1
mov mp0,a
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; setup size of block
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Bank Pointer - BP
Program Counter Low Register - PCL
For this series of devices, the Data Memory is divided
into two banks. Selecting the required Data Memory
area is achieved using the Bank Pointer. Bit 0 is used to
select Data Memory Banks 0~1.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Data Memory is initialised to Bank 0 after a reset,
except for a WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that the Special Function
Data Memory is not affected by the bank selection,
which means that the Special Function Registers can be
accessed from within any bank. Directly addressing the
Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be
implemented using indirect addressing.
Look-up Table Registers - TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is stored in the
Program Memory. TBLP and TBHP are the table pointer
and indicates the location where the table data is located. Their value must be setup before any table read
commands are executed. Their value can be changed,
for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is
the location where the high order byte of the table data is
stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.
Accumulator - ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
· Bank Pointer Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
¾
DMBP0
R/W
¾
¾
¾
¾
¾
¾
¾
R/W
POR
¾
¾
¾
¾
¾
¾
¾
0
Bit 7 ~ 1
Unimplemented, read as ²0²
Bit 0
DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Status Register - STATUS
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
· Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
· STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TO
PDF
OV
Z
AC
C
R/W
¾
¾
R
R
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
x
x
x
x
²x² unknown
Bit 7, 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as ²0²
TO: Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
25
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
EEPROM Data Memory
The device contains an area of internal EEPROM Data
Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature
a non-volatile form of re-programmable memory, with
data retention even when its power supply is removed.
By incorporating this kind of data memory, a whole new
host of application possibilities are made available to the
designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or
other product information to be stored directly within the
product microcontroller. The process of reading and
writing data to the EEPROM memory has been reduced
to a very trivial affair.
Device
All devices
Capacity
Address
64´8
00H ~ 3FH
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control
register, EEC. As both the EEA and EED registers are
located in Bank 0, they can be directly accessed in the
same was as any other Special Function Register. The
EEC register however, being located in Bank1, cannot
be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC
control register is located at address 40H in Bank 1, the
MP1 Memory Pointer must first be set to the value 40H
and the Bank Pointer register, BP, set to the value, 01H,
before any operations on the EEC register are executed.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is 64´8 bits for
this series of devices. Unlike the Program Memory and
RAM Data Memory, the EEPROM Data Memory is not
directly mapped into memory space and is therefore not
directly addressable in the same way as the other types
of memory. Read and Write operations to the EEPROM
are carried out in single byte operations using an address and data register in Bank 0 and a single control
register in Bank 1.
· EEPROM Register List
Name
Bit
7
6
5
4
3
2
1
0
EEA
¾
¾
D5
D4
D3
D2
D1
D0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
¾
¾
¾
¾
WREN
WR
RDEN
RD
· EEA Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
D5
D4
D3
D2
D1
D0
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
¾
x
x
x
x
x
x
²x² unknown
Bit 7 ~ 6
Unimplemented, read as ²0²
Bit 5 ~ 0
Data EEPROM address
Data EEPROM address bit 5 ~ bit 0
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· EEC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
WREN
WR
RDEN
RD
R/W
¾
¾
¾
¾
R/W
R/W
R/W
R/W
POR
¾
¾
¾
¾
0
0
0
0
Bit 7 ~ 4
Unimplemented, read as ²0²
Bit 3
WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.
Bit 2
WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application program will
activate a write cycle. This bit will be automatically reset to zero by the hardware after the write
cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.
Bit 0
RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application program will
activate a read cycle. This bit will be automatically reset to zero by the hardware after the read
cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to ²1² at the same time in one instruction. The WR and RD can
not be set to ²1² at the same time.
· EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
²x² unknown
Bit 7 ~ 0
Rev. 1.00
Data EEPROM address
Data EEPROM address bit 7 ~ bit 0
27
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Reading Data from the EEPROM
the Write Enable bit in the control register will be cleared
preventing any write operations. Also at power-on the
Bank Pointer, BP, will be reset to zero, which means that
Data Memory Bank 0 will be selected. As the EEPROM
control register is located in Bank 1, this adds a further
measure of protection against spurious write operations. During normal program operation, ensuring that
the Write Enable bit in the control register is cleared will
safeguard against incorrect write operations.
To read data from the EEPROM, the read enable bit,
RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the
data to be read must then be placed in the EEA register.
If the RD bit in the EEC register is now set high, a read
cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set.
When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be
read from the EED register. The data will remain in the
EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading.
EEPROM Interrupt
The EEPROM write interrupt is generated when an
EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the
relevant interrupt register. However as the EEPROM is
contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set.
When an EEPROM write cycle ends, the DEF request
flag and its associated multi-function interrupt request
flag will both be set. If the global, EEPROM and
Multi-function interrupts are enabled and the stack is not
full, a jump to the associated Multi-function Interrupt
vector will take place. When the interrupt is serviced
only the Multi-function interrupt flag will be automatically
reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section.
Writing Data to the EEPROM
The EEPROM address of the data to be written must
first be placed in the EEA register and the data placed in
the EED register. To write data to the EEPROM, the
write enable bit, WREN, in the EEC register must first be
set high to enable the write function. After this, the WR
bit in the EEC register must be immediately set high to
initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI
should also first be cleared before implementing any
write operations, and then set again after the write cycle
has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As
the EEPROM write cycle is controlled using an internal
t im e r w h o s e o p e r at i o n i s a s y n c hr o n o u s t o
microcontroller system clock, a certain time will elapse
before the data will have been written into the EEPROM.
Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write
cycle terminates, the WR bit will be automatically
cleared to zero by the microcontroller, informing the user
that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended.
Programming Considerations
Care must be taken that data is not inadvertently written
to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero
when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to
Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be
given in the application program to the checking of the
validity of new write data by a simple read back process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure
the write cycle executes correctly. The global interrupt
bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is powered-on
Rev. 1.00
28
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· Programming Examples
¨
Reading data from the EEPROM - polling method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
SET IAR1.1
SET IAR1.0
BACK:
SZ
IAR1.0
JMP BACK
CLR IAR1
CLR BP
MOV A, EED
MOV READ_DATA, A
¨
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM read/write
; move read data to register
Writing Data to the EEPROM - polling method
CLR EMI
MOV A, EEPROM_ADRES
; user defined address
MOV EEA, A
MOV A, EEPROM_DATA
; user defined data
MOV EED, A
MOV A, 040H
; setup memory pointer MP1
MOV MP1, A
; MP1 points to EEC register
MOV A, 01H
; setup Bank Pointer
MOV BP, A
SET IAR1.3
; set WREN bit, enable write operations
SET IAR1.2
; Start Write Cycle - set WR bit - executed immediately
; after set WREN bit
SET EMI
BACK:
SZ
IAR1.2
; check for write cycle end
JMP BACK
CLR IAR1
; disable EEPROM read/write
CLR BP
Rev. 1.00
29
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. The flexible features of the oscillator functions
ensure that the best optimisation can be achieved in
terms of speed and power saving. Oscillator selections
and operation are selected through a combination of
configuration options and registers.
Type
Name
Freq.
Pins
External Crystal
HXT
400kHz~
20MHz
OSC1/
OSC2
Internal High
Speed RC
HIRC
8MHz
¾
Oscillator Overview
Internal Low
Speed RC
LIRC
32kHz
¾
In addition to being the source of the main system clock
the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully
integrated internal oscillators, requiring no external
components, are provided to form a wide range of both
fast and slow system oscillators. All oscillator options
are selected through the configuration options. The
higher frequency oscillators provide higher performance
but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the
lower frequency oscillators. With the capability of dynamically switching between fast and slow system
clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in
power sensitive portable applications.
Oscillator Types
System Clock Configurations
There are methods of generating the system clock, two
high speed oscillators and one low speed oscillators.
The high speed oscillators are the external crystal/ceramic oscillator - HXT and the internal 8MHz RC oscillator - HIRC. The low speed oscillator is the internal
32kHz oscillator - LIRC. Selecting whether the low or
high speed oscillator is used as the system oscillator is
implemented using the HLCLK bit and CKS2~CKS0 bits
in the SMOD register and as the system clock can be
dynamically selected.
H ig h S p e e d
O s c illa tio n
H X T
fH
6 - s ta g e P r e s c a le r
H IR C
fH /2
fH /4
fH /8
H ig h S p e e d O s c illa tio n
C o n fig u r a tio n O p tio n
fH /1 6
fH /3 2
fH /6 4
L IR C
fS
fL
Y S
H L C L K ,
C K S 2 ~ C K S 0 b its
L o w S p e e d
O s c illa tio n
fS
U B
F a s t W a k e -u p fro m S L E E P M o d e o r
ID L E M o d e C o n tr o l ( fo r H X T o n ly )
System Clock Configurations
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Internal RC Oscillator - HIRC
The actual source clock used for each of the high speed
oscillator is chosen via configuration options. The frequency of the slow speed or high speed system clock is
also determined using the HLCLK bit and CKS2~CKS0
bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low
speed system oscillators. It is not possible to choose a
no-oscillator selection for either the high or low speed
oscillator. The OSC1 and OSC2 pins are used to connect the external components for the external crystal.
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal
RC oscillator has a fixed frequency of 8MHz. Device
trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply
voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power
supply of 5V and at a temperature of -40°C ~85°C degrees, the fixed oscillation frequency of the high speed
internal 8MHz RC oscillator will have a tolerance within
2%. Note that if this internal system clock option is selected as the high speed oscillator, as it requires no external pins for its operation, I/O pins PA6 and PA5 can
only be used as normal I/O pins.
External Crystal/Ceramic Oscillator - HXT
The External Crystal/ Ceramic System Oscillator is one
of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal
across OSC1 and OSC2 will create the necessary
phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types
and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2.
Using a ceramic resonator will usually require two small
value capacitors, C1 and C2, to be connected as shown
for oscillation to occur. The values of C1 and C2 should
be selected in consultation with the crystal or resonator
manufacturer¢s specification.
C 1
O S C 1
R p
R f
Internal 32kHz Oscillator - LIRC
The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator
with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the
inclusion of internal frequency compensation circuits
are used to ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. As a result, at a
power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 32kHz will have
a tolerance within 10%.
In te r n a l
O s c illa to r
C ir c u it
Supplementary Oscillators
C 2
T o in te r n a l
c ir c u its
O S C 2
The low speed oscillators, in addition to providing a system clock source are also used to provide a clock
source to two other device functions. These are the
Watchdog Timer and the Time Base Interrupts.
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
12MHz
0pF
0pF
8MHz
0pF
0pF
4MHz
0pF
0pF
1MHz
100pF
100pF
Note:
C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
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HT66F016/HT66F017/HT68F016/HT68F017
Operating Modes and System Clocks
P re s e n t d a y appl i c a t i ons r equi r e t ha t t h e i r
microcontrollers have high performance but often still
demand that they consume as little power as possible,
conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase
current consumption and of course vice-versa, lower
speed clocks reduce current consumption. As Holtek
has provided these devices with both high and low
speed clock sources and the means to switch between
them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected
using the HLCLK bit and CKS2~CKS0 bits in the SMOD
register. The high speed system clock can be sourced
from either an HXT or HIRC oscillator, selected via a
configuration option. The low speed system clock
source can be sourced from internal clock fL. The other
choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64.
There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time
Base clock, fTBC. Each of these internal clocks are
sourced by the LIRC oscillators. The fSUB clock is used
to provide a substitute clock for the microcontroller just
after a wake-up has occurred to enable faster wake-up
times.
System Clocks
The device has many different clock sources for both
the CPU and peripheral function operation. By providing
the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application
performance.
H ig h S p e e d
O s c illa tio n
H X T
fH
6 - s ta g e P r e s c a le r
H IR C
fH /2
fH /4
fH /8
H ig h S p e e d O s c illa tio n
C o n fig u r a tio n O p tio n
fH /1 6
fH /3 2
fH /6 4
L IR C
fS
fL
Y S
H L C L K ,
C K S 2 ~ C K S 0 b its
L o w S p e e d
O s c illa tio n
fS
U B
F a s t W a k e -u p fro m S L E E P M o d e o r
ID L E M o d e C o n tr o l ( fo r H X T o n ly )
fS
U B
fS
fS
Y S
W D T
/4
fS C o n fig u r a tio n O p tio n
fT
B C
fT
fS
Y S
/4
B
T im e B a s e
T B C K
System Clock Configurations
Note:
When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the
power. Thus there is no fH~fH/64 for peripheral circuit to use.
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HT66F016/HT66F017/HT68F016/HT68F017
Together with fSYS/4 it is also used as one of the clock
sources for the Watchdog timer. The fTBC clock is used
as a source for the Time Base interrupt functions and for
the TMs.
istics and which can be chosen according to the specific
performance and power requirements of the application. There are two modes allowing normal operation of
the microcontroller, the NORMAL Mode and SLOW
Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 Mode are used when the
microcontroller CPU is switched off to conserve power.
System Operation Modes
There are six different modes of operation for the
microcontroller, each one with its own special character-
Description
Operation Mode
CPU
fSYS
fSUB
fS
fTBC
NORMAL Mode
On
fH~ fH/64
On
On
On
SLOW Mode
On
fL
On
On
On
IDLE0 Mode
Off
Off
On
On
On
IDLE1 Mode
Off
On
On
On
On
SLEEP0 Mode
Off
Off
Off
Off
Off
SLEEP1 Mode
Off
Off
On
On
Off
· NORMAL Mode
· SLEEP1 Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of its
functions operational and where the system clock is
provided by one of the high speed oscillators. This
mode operates allowing the microcontroller to operate
normally with a clock source will come from one of the
high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio
being selected by the CKS2~LCKS0 and HLCLK bits
in the SMOD register. Although a high speed oscillator
is used, running the microcontroller at a divided clock
ratio reduces the operating current.
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD
register is low. In the SLEEP1 mode the CPU will be
stopped. However the fSUB and fS clocks will continue
to operate if the LVDEN is ²1² or the Watchdog Timer
function is enabled and if its clock source is chosen
via configuration option to come from the fSUB.
· IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction
is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register
is low. In the IDLE0 Mode the system oscillator will be
inhibited from driving the CPU but some peripheral
functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system
oscillator will be stopped.
· SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed clock
source. The clock source used will be from the low
speed oscillators LIRC. Running the microcontroller in
this mode allows it to run with much lower operating
currents. In the SLOW Mode, the fH is off.
· IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction
is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register
is high. In the IDLE1 Mode the system oscillator will be
inhibited from driving the CPU but may continue to
provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and
TMs. In the IDLE1 Mode, the system oscillator will
continue to run, and this system oscillator may be high
speed or low speed system oscillator.
· SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD
register is low. In the SLEEP0 mode the CPU will be
stopped, and the fSUB and fS clocks will be stopped too,
and the Watchdog Timer function is disabled. In this
mode, the LVDEN is must set to ²0². If the LVDEN is
set to ²1², it won¢t enter the SLEEP0 Mode.
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HT66F016/HT66F017/HT68F016/HT68F017
Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
· SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
FSTEN
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
0
0
0
0
0
1
1
Bit 7~5
CKS2~CKS0: The system clock selection when HLCLK is ²0²
000: fL (fLIRC)
001: fL (fLIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In addition
to the system clock source, which can be the LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
Bit 4
FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used
after the device wakes up. When the bit is high, the fSUB clock source can be used as a
temporary system clock to provide a faster wake up time as the fSUB clock is available.
Bit 3
LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed system
oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in
the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after
1~2 clock cycles for the LIRC oscillator.
Bit 2
HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed system
oscillator is stable. This flag is cleared to ²0² by hardware when the device is powered on and
then changes to a high level after the high speed system oscillator is stable. Therefore this flag
will always be read as ²1² by the application program after device power-on. The flag will be
low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to
a high level after 128 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if
the HIRC oscillator is used.
Bit 1
IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT instruction is
executed. If this bit is high, when a HALT instruction is executed the device will enter the
IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to
keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU
and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the
SLEEP Mode when a HALT instruction is executed.
Bit 0
HLCLK: system clock selection
0: fH/2 ~ fH/64 or fL
1: fH
This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system
clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will
be selected. When system clock switches from the fH clock to the fL clock and the fH clock will
be automatically switched off to conserve power.
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HT66F016/HT66F017/HT68F016/HT68F017
Fast Wake-up
is stopped. The Fast Wake-up enable/disable function is
controlled using the FSTEN bit in the SMOD register.
To minimise power consumption the device can enter
the SLEEP or IDLE0 Mode, where the system clock
source to the device will be stopped. However when the
device is woken up again, it can take a considerable
time for the original system oscillator to restart, stabilise
and allow normal operation to resume. To ensure the
device is up and running as fast as possible a Fast
Wake-up function is provided, which allows fSUB,
namely the LIRC oscillator, to act as a temporary clock
to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast
Wake-up function is fSUB, the Fast Wake-up function is
only available in the SLEEP1 and IDLE0 modes. When
the device is woken up from the SLEEP0 mode, the Fast
Wake-up function has no effect because the fSUB clock
System
Oscillator
HXT
FSTEN
Bit
Wake-up Time
(SLEEP0 Mode)
0
128 HXT cycles
If the HXT oscillator is selected as the NORMAL Mode
system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the
LIRC oscillator for the system to wake-up. The system
will then initially run under the fSUB clock source until 128
HXT clock cycles have elapsed, at which point the HTO
flag will switch high and the system will switch over to
operating from the HXT oscillator.
If the HIRC oscillators or LIRC oscillator is used as the
system oscillator then it will take 15~16 clock cycles of
the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up
bit, FSTEN will have no effect in these cases.
Wake-up Time
(SLEEP1 Mode)
Wake-up Time
(IDLE0 Mode)
128 HXT cycles
Wake-up Time
(IDLE1 Mode)
1~2 HXT cycles
1~2 fSUB cycles
(System runs with fSUB first for 128 HXT cycles and 1~2 HXT cycles
then switches over to run with the HXT clock)
1
128 HXT cycles
HIRC
X
15~16 HIRC cycles
15~16 HIRC cycles
1~2 HIRC cycles
LIRC
X
1~2 LIRC cycles
1~2 LIRC cycles
1~2 LIRC cycles
Wake-Up Times
Note that if the Watchdog Timer is disabled, which means that the LIRC is off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.
²X²: don¢t care
Operating Mode Switching and Wake-up
fS
ID L E 1
H A L T in s tr u c tio n is e x e c u te d
C P U s to p
ID L E N = 1
F S Y S O N = 1
fS Y S o n
fT B C o n
fS U B o n
N O R M A L
Y S = f H ~ f H / 6 4
fH o n
C P U ru n
fS Y S o n
fT B C o n
fS U B o n
ID L E 0
H A L T in s tr u c tio n is e x e c u te d
C P U s to p
ID L E N = 1
F S Y S O N = 0
fS Y S o ff
fT B C o n
fS U B o n
S L E E P 0
H A L T in s tr u c tio n is e x e c u te d
fS Y S o ff
C P U s to p
ID L E N = 0
fT B C o ff
fS U B o ff
W D T & L V D o ff
S L E E P 1
H A L T in s tr u c tio n is e x e c u te d
fS Y S o ff
C P U s to p
ID L E N = 0
fT B C o ff
fS U B o n
W D T o r L V D o n
Rev. 1.00
S L O W
fS Y S = fL
fL o n
C P U ru n
fS Y S o n
fT B C o n
fS U B o n
fH o ff
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HT66F016/HT66F017/HT68F016/HT68F017
The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this
way microcontroller operations that do not require high
performance can be executed using slower clocks thus
requiring less operating current and prolonging battery
life in portable applications.
sources will also stop running, which may affect the operation of other internal functions such as the TMs. The
accompanying flowchart shows what happens when the
device moves between the various operating modes.
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the
high speed system oscillator, and therefore consumes
more power, the system clock can switch to run in the
SLOW Mode by setting the HLCLK bit to ²0² and setting
the CKS2~CKS0 bits to ²000² or ²001² in the SMOD
register. This will then use the low speed system oscillator which will consume less power. Users may decide to
do this for certain operations which do not require high
performance and can subsequently reduce power consumption.
In simple terms, Mode Switching between the NORMAL
Mode and SLOW Mode is executed using the HLCLK bit
and CKS2~CKS0 bits in the SMOD register while Mode
Switching from the NORMAL/SLOW Modes to the
SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the
device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD
register and FSYSON in the CTRL register.
The SLOW Mode is sourced from the the LIRC oscillators and therefore requires these oscillators to be stable
before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed
clock source, fH, to the clock source, fH/2~fH/64 or fL. If
the clock is from the fL, the high speed clock source will
stop running to conserve power. When this happens it
must be noted that the fH/16 and fH/64 internal clock
N O R M A L M o d e
C K S 2 ~ C K S 0 = 0 0 x B &
H L C L K = 0
S L O W
M o d e
W D T a n d L V D a r e a ll o ff
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 0 M o d e
W D T o r L V D is o n
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 1 M o d e
ID L E N = 1 , F S Y S O N = 0
H A L T in s tr u c tio n is e x e c u te d
ID E L 0 M o d e
ID L E N = 1 , F S Y S O N = 1
H A L T in s tr u c tio n is e x e c u te d
ID L E 1 M o d e
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
S L O W
M o d e
C K S 2 ~ C K S 0 ¹ 0 0 0 B , 0 0 1 B a s H L C L K = 0
o r H L C L K = 1
N O R M A L M o d e
W D T a n d L V D a r e a ll o ff
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 0 M o d e
W D T o r L V D is o n
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 1 M o d e
ID L E N = 1 , F S Y S O N = 0
H A L T in s tr u c tio n is e x e c u te d
ID L E 0 M o d e
ID L E N = 1 , F S Y S O N = 1
H A L T in s tr u c tio n is e x e c u te d
ID L E 1 M o d e
SLOW Mode to NORMAL Mode Switching
Entering the SLEEP0 Mode
In SLOW Mode the system uses the LIRC low speed
system oscillator. To switch back to the NORMAL Mode,
where the high speed system oscillator is used, the
HLCLK bit should be set to ²1² or HLCLK bit is ²0², but
CKS2~CKS0 is set to ²010², ²011², ²100², ²101², ²110²
or ²111². As a certain amount of time will be required for
the high frequency clock to stabilise, the status of the
HTO bit is checked. The amount of time required for
high speed system oscillator stabilization depends upon
which high speed system oscillator type is used.
There is only one way for the device to enter the
SLEEP0 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in
SMOD register equal to ²0² and the WDT and LVD both
off. When this instruction is executed under the conditions described above, the following will occur:
· The system clock, WDT clock and Time Base clock
will be stopped and the application program will stop
at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and stopped no matter if the
WDT clock source originates from the fSUB clock or
from the system clock.
· The I/O ports will maintain their present conditions.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
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HT66F016/HT66F017/HT68F016/HT68F017
Entering the SLEEP1 Mode
Entering the IDLE1 Mode
There is only one way for the device to enter the
SLEEP1 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit
in SMOD register equal to ²0² and the WDT or LVD on.
When this instruction is executed under the conditions
described above, the following will occur:
There is only one way for the device to enter the IDLE1
Mode and that is to execute the ²HALT² instruction in the
application program with the IDLEN bit in SMOD register
equal to ²1² and the FSYSON bit in CTRL register equal
to ²1². When this instruction is executed under the with
conditions described above, the following will occur:
· The system clock and Time Base clock will be
· The system clock and Time Base clock and fSUB clock
stopped and the application program will stop at the
²HALT² instruction, but the WDT or LVD will remain
with the clock source coming from the fSUB clock.
will be on and the application program will stop at the
²HALT² instruction.
· The Data Memory contents and registers will maintain
· The Data Memory contents and registers will maintain
their present condition.
their present condition.
· The WDT will be cleared and resume counting if the
· The WDT will be cleared and resume counting if the
WDT is enabled.
WDT is enabled.
· The I/O ports will maintain their present conditions.
· The I/O ports will maintain their present conditions.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
Entering the IDLE0 Mode
As the main reason for entering the SLEEP or IDLE
Mode is to keep the current consumption of the device
to as low a value as possible, perhaps only in the order
of several micro-amps except in the IDLE1 Mode, there
are other considerations which must also be taken into
account by the circuit designer if the power consumption
is to be minimised. Special attention must be made to
the I/O pins on the device. All high-impedance input pins
must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations
and result in increased current consumption. This also
applies to devices which have different package types,
as there may be unbonbed pins. These must either be
setup as outputs or if setup as inputs must have
pull-high resistors connected.
There is only one way for the device to enter the IDLE0
Mode and that is to execute the ²HALT² instruction in the
application program with the IDLEN bit in SMOD register
equal to ²1² and the FSYSON bit in CTRL register equal
to ²0². When this instruction is executed under the conditions described above, the following will occur:
· The system clock will be stopped and the application
program will stop at the ²HALT² instruction, but the
Time Base clock and fSUB clock will be on.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT is enabled.
· The I/O ports will maintain their present conditions.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These
should be placed in a condition in which minimum current
is drawn or connected only to external circuits that do not
draw current, such as other CMOS inputs. Also note that
additional standby current will also be required if the configuration options have enabled the LIRC oscillator.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator,
the additional standby current will also be perhaps in the
order of several hundred micro-amps.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Wake-up
Programming Considerations
After the system enters the SLEEP or IDLE Mode, it can
be woken up from one of various sources listed as follows:
The high speed and low speed oscillators both use the
same SST counter. For example, if the system is woken
up from the SLEEP0 Mode and both the HIRC and LIRC
oscillators need to start-up from an off state. The LIRC
oscillator uses the SST counter after HIRC oscillator has
finished its SST period.
· An external reset
· An external falling edge on Port A
· A system interrupt
· If the device is woken up from the SLEEP0 Mode to
· A WDT overflow
the NORMAL Mode, the high speed system oscillator
needs an SST period. The device will execute first instruction after HTO is ²1². At this time, the LIRC oscillator may not be stability. The same situation occurs in
the power-on state. The LIRC oscillator is not ready yet
when the first instruction is executed.
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in their
original status.
· If the device is woken up from the SLEEP1 Mode to
NORMAL Mode, and the system clock source is from
HXT oscillator and FSTEN is ²1², the system clock can
be switched to the LIRC oscillator after wake up.
· There are peripheral functions, such as WDT and
TMs, for which the fSYS is used. If the system clock
source is switched from fH to fL, the clock source to the
peripheral functions mentioned above will change accordingly.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up
the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following
the ²HALT² instruction. If the system is woken up by an
interrupt, then two possible situations may occur. The first
is where the related interrupt is disabled or the interrupt is
enabled but the stack is full, in which case the program
will resume execution at the instruction following the
²HALT² instruction. In this situation, the interrupt which
woke-up the device will not be immediately serviced, but
will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The
other situation is where the related interrupt is enabled
and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is
set high before entering the SLEEP or IDLE Mode, the
wake-up function of the related interrupt will be disabled.
Rev. 1.00
· The on/off condition of fSUB and fS depends upon
whether the WDT is enabled or disabled.
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HT66F016/HT66F017/HT68F016/HT68F017
Watchdog Timer
the WDT function. When the WE4~WE0 bits value is
equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits are changed to
any other values except 01010B and 10101B, which is
caused by the environmental noise or software setting,
it will reset the microcontroller after 2~3 LIRC clock cycles. If the WDT configuration option is determined that
the WDT function is controlled by the WDT control register, the WE4~WE0 values can determine which mode
the WDT operates in. The WDT function will be disabled
when the WE4~WE0 bits are set to a value of 10101B.
The WDT function will be enabled if the WE4~WE0 bits
value is equal to 01010B. If the WE4~WE0 bits are set
to any other values by the environmental noise or software setting, except 01010B and 10101B, it will reset
the device after 2~3 LIRC clock cycles. After power on
these bits will have the value of 01010B.
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by the LIRC oscillator. The LIRC internal oscillator has an approximate
period of 32 kHz at a supply voltage of 5V. However, it
should be noted that this specified internal clock period
can vary with VDD, temperature and process variations.
The Watchdog Timer source clock is then subdivided by
a ratio of 28 to 218 to give longer timeouts, the actual
value being chosen using the WS2~WS0 bits in the
WDTC register.
Watchdog Timer Control Register
Watchdog Timer Enable/Disable Control
A single register, WDTC, controls the required timeout
period as well as the enable/disable operation. This register together with several configuration options control
the overall operation of the Watchdog Timer.
WDT Configuration Option
Always Enable
01010B or 10101B
Enable
Any other value
Reset MCU
10101B
Disable
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user
has to strategically clear the Watchdog Timer before it
overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever
reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in
the correct manner, in which case the Watchdog Timer
will overflow and reset the device. Some of the Watchdog Timer options, such as always on select and clear
instruction type are selected using configuration options. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the
WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. If the WDT configuration option is determined that the WDT function is
always enabled, the WE4~WE0 bits still have effects on
W D T C
R e g is te r
IR C
01010B
Enable
Any other value
Reset MCU
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status
bit TO. However, if the system is in the SLEEP or IDLE
Mode, when a Watchdog Timer time-out occurs, the TO
bit in the status register will be set and only the Program
Counter and Stack Pointer will be reset. Three methods
can be adopted to clear the contents of the Watchdog
Timer. The first is a WDT reset, which means a certain
value except 01010B and 10101B written into the
WE4~WE0 bit filed, the second is using the Watchdog
Timer software clear instructions and the third is via a
HALT instruction.
There is only one method of using software instruction
to clear the Watchdog Timer. That is to use the single
²CLR WDT² instruction to clear the WDT.
C L R
C L R W D T
fL
Controlled by WDT
Control Register
R e s e t M C U
W E 4 ~ W E 0 b its
L IR C
WDT
Function
WE4~WE0 Bits
fS
8 - s ta g e D iv id e r
fS /2
W S 2 ~ W S 0
(fS /2 8 ~ fS /2 18)
8
W D T P r e s c a le r
W D T T im e - o u t
(2 8 /fS ~ 2 18/fS )
8 -to -1 M U X
Watchdog Timer
Rev. 1.00
40
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum
watchdog period of around 8 second for the 218 division
ratio, and a minimum timeout of 7.8ms for the 28 division
ration.
· WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3
WE4~WE0: WDT function software control
If the WDT configuration option is ²always enable²:
10101 or 01010: Enabled
Other: Reset MCU
If the WDT configuration option is ²controlled by the WDT control register²:
10101: Disabled
01010: Enabled
Other: Reset MCU
When these bits are changed by the environmental noise or software setting to reset the
microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit
in the CTRL register will be set to 1.
Bit 2~0
WS2, WS1, WS0: WDT time-out period selection
000: 28/fS
001: 210/fS
010: 212/fS
011: 214/fS
100: 215/fS
101: 216/fS
110: 217/fS
111: 218/fS
· CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
¾
¾
¾
¾
LVRF
LRF
WRF
R/W
R/W
¾
¾
¾
¾
R/W
R/W
R/W
POR
0
¾
¾
¾
¾
x
0
0
²x² unknown
Bit 7
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as ²0²
Bit 2
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can
only be cleared to 0 by the application program.
Bit 1
LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values.
This in effect acts like a software reset function. This bit can only be cleared to 0 by the
application program.
Bit 0
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the application
program. Note that this bit can only be cleared to 0 by the application program.
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Reset and Initialisation
range between 0.9V~VLVR must exist for a time
greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply
voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the
LVRC register. If the LVS7~LVS0 bits are changed to
some certain values by the environmental noise or
software setting, the LVR will reset the device after
2~3 LIRC clock cycles. When this happens, the LRF
bit in the CTRL register will be set to 1. After power on
the register will have the value of 01010101B.
Note that the LVR function will be automatically disabled when the device enters the power down mode.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
L V R
tR
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset
operations result in different register conditions being
setup. Another reset exists in the form of a Low Voltage
Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold.
tS
S T
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as LVR reset except that the Watchdog time-out flag TO will be set to ²1².
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
W D T T im e - o u t
tR
S T D
+
tS
S T
In te rn a l R e s e t
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
tR
S D T +
tS
Note: tRSTD is power-on delay, typical time=50ms
WDT Time-out Reset during Normal Operation
Timing Chart
· Watchdog Time-out Reset during SLEEP or IDLE
Mode
The Watchdog time-out Reset during SLEEP or IDLE
Mode is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the
Program Counter and the Stack Pointer will be
cleared to ²0² and the TO flag will be set to ²1². Refer
to the A.C. Characteristics for tSST details.
S T
In te rn a l R e s e t
W D T T im e - o u t
Note: tRSTD is power-on delay, typical time=50ms
tS
Power-On Reset Timing Chart
S T
In te rn a l R e s e t
WDT Time-out Reset during SLEEP or IDLE
Timing Chart
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a
specific LVR voltage VLVR. If the supply voltage of the
device drops to within a range of 0.9V~VLVR such as
might occur when changing the battery, the LVR will
automatically reset the device internally and the LVRF
bit in the CTRL register will also be set to 1. For a valid
LVR signal, a low supply voltage, i.e., a voltage in the
Rev. 1.00
+
Note: tRSTD is power-on delay, typical time=16.7ms
Reset Functions
V D D
S T D
In te rn a l R e s e t
Note:
42
The tSST is 15~16 clock cycles if the system clock
source is provided by HIRC. The tSST is 128 clock
for HXT. The tSST is 1~2 clock for LIRC.
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~0
LVS7~LVS0: LVR Voltage Select control
01010101: 2.1V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
Any other value: Generates MCU reset -- LVRC register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage
values above, an MCU reset will be generated. The reset operation will be activated after 2~3
LIRC clock cycles. In this situation the register contents will remain the same after such a reset
occurs.
Any register value, other than the four defined LVR values above, will also result in the
generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock cycles.
However in this situation the register contents will be reset to the POR value.
Reset Initial Conditions
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
SLEEP or IDLE Mode function or Watchdog Timer. The
reset flags are shown in the table:
Item
RESET Conditions
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
TO
PDF
0
0
Power-on reset
Timer Modules
Timer Counter will be turned off
u
u
LVR reset during NORMAL or
SLOW Mode operation
Input/Output Ports
I/O ports will be setup as inputs,
and AN0~AN3 as A/D input pins
1
u
WDT time-out reset during NORMAL or
SLOW Mode operation
Stack Pointer
Stack Pointer will point to the top
of the stack
1
1
WDT time-out reset during IDLE or
SLEEP Mode operation
Note: ²u² stands for unchanged.
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation
for the larger package type.
HT66F016
HT66F017
HT68F016
HT68F017
Reset
(Power-on)
MP0
l
l
l
l
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
l
l
l
l
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
l
l
l
l
---- ---0
---- ---0
---- ---0
---- ---u
ACC
l
l
l
l
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
l
l
l
l
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
l
l
l
l
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
l
l
l
l
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
l
---- -xxx
---- -uuu
---- -uuu
---- -uuu
---- --xx
---- --uu
---- --uu
---- --uu
Register
TBHP
l
l
l
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(IDLE)
STATUS
l
l
l
l
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
SMOD
l
l
l
l
0000 0011
0000 0011
0000 0011
uuuu uuuu
LVDC
l
l
l
l
--00 -000
--00 -000
--00 -000
--uu -uuu
INTEG
l
l
l
l
---- 0000
---- 0000
---- 0000
---- uuuu
l
-000 0000
-000 0000
-000 0000
-uuu uuuu
--00 -000
--00 -000
--00 -000
--uu -uuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC0
INTC1
INTC2
l
l
l
l
l
l
l
l
l
0-00 0-00
0-00 0-00
0-00 0-00
u-uu u-uu
l
l
--00 --00
--00 --00
--00 --00
--uu --uu
l
--00 --00
--00 --00
--00 --00
--uu --uu
l
MFI0
MFI1
l
l
l
l
--00 --00
--00 --00
--00 --00
--uu --uu
MFI2
l
l
l
l
--00 --00
--00 --00
--00 --00
--uu --uu
PA
l
l
l
l
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
l
l
l
l
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
l
l
l
l
--11 1111
--11 1111
--11 1111
--uu uuuu
PBC
l
l
l
l
--11 1111
--11 1111
--11 1111
--uu uuuu
PBPU
l
l
l
l
--00 0000
--00 0000
--00 0000
--uu uuuu
PRM
l
l
l
l
0101 0000
0101 0000
0101 0000
uuuu uuuu
l
---- --00
---- --00
---- --00
---- --uu
---- --0-
---- --0-
---- --0-
---- --u-
TMPC
l
l
l
WDTC
l
l
l
l
0101 0011
0101 0011
0101 0011
uuuu uuuu
TBC
l
l
l
l
0011 -111
0011 -111
0011 -111
uuuu -uuu
Rev. 1.00
44
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
HT66F016
HT66F017
HT68F016
HT68F017
Reset
(Power-on)
EEA
l
l
l
l
--00 0000
--00 0000
--00 0000
--uu uuuu
EED
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
EEC
l
l
l
l
---- 0000
---- 0000
---- 0000
---- uuuu
ADRL (ADRFS=0)
l
l
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRL (ADRFS=1)
l
l
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH (ADRFS=0) l
l
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH (ADRFS=1) l
l
---- xxxx
---- xxxx
---- xxxx
---- uuuu
ADCR0
l
l
0110 --00
0110 --00
0110 --00
uuuu --uu
ADCR1
l
l
00-0 -000
00-0 -000
00-0 -000
uu-u -uuu
ACERL
l
l
---- 1111
---- 1111
---- 1111
---- uuuu
CPC
l
l
l
l
1000 0--1
1000 0--1
1000 0--1
uuuu u--u
CTRL
l
l
l
l
0--- -x00
u--- -uuu
u--- -uuu
u--- -uuu
LVRC
l
l
l
l
0101 0101
0101 0101
0101 0101
uuuu uuuu
Register
LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(IDLE)
TM0C0
l
l
0000 0---
0000 0---
0000 0---
uuuu u---
TM0C1
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DL
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DH
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AL
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AH
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
l
TM0RP
TM1C0
l
l
l
l
0000 0---
0000 0---
0000 0---
uuuu u---
TM1C1
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DL
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DH
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AL
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AH
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1RP
l
l
l
l
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.00
45
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin
fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is
provided with an I/O structure to meet the needs of a wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA and PB. These I/O ports are mapped to
the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O
ports can be used for input and output operations. For input operation, these ports are non-latching, which means the
inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output
operation, all the data is latched and remains unchanged until the output latch is rewritten.
· I/O Register List
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
D7
D6
D5
D4
D3
D2
D1
D0
PAC
D7
D6
D5
D4
D3
D2
D1
D0
PAPU
D7
D6
D5
D4
D3
D2
D1
D0
PAWU
D7
D6
D5
D4
D3
D2
D1
D0
PB
¾
¾
D5
D4
D3
D2
D1
D0
PBC
¾
¾
D5
D4
D3
D2
D1
D0
PBPU
¾
¾
D5
D4
D3
D2
D1
D0
PRM
PRML3
PRML2
PRML1
PRML0
PRMS3
PRMS2
PRMS1
PRMS0
Pull-High Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of
being connected to an internal pull-high resistor. These pull-high resistors are selected using the register PAPU and
PBPU, and are implemented using weak PMOS transistors.
· PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
I/O Port A bit 7 ~ bit 0 Pull-high control
0: disable
1: enable
· PBPU Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
D5
D4
D3
D2
D1
D0
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
0
0
0
0
Bit 7~6
²¾² Unimplemented, read as 0
Bit 5~0
I/O Port B bit 5 ~ bit 0 Pull-high control
0: disable
1: enable
Rev. 1.00
46
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is
important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of
which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for
applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this
wake-up feature using the PAWU register.
· PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
PAWU: Port A bit 7 ~ bit 0 wake-up control
0: disable
1: enable
I/O Port Control Register
The I/O port has its own control register known as PAC and PBC, to control the input/output configuration. With this
control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the
I/O port is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup
as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register.
However, it should be noted that the program will in fact only read the status of the output data latch and not the actual
logic status of the output pin.
· PAC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
3
2
1
0
Bit 7~0
I/O Port A bit 7 ~ bit 0 input/output control
0: Output
1: Input
· PBC Register
Bit
7
6
5
4
Name
¾
¾
D5
D4
D3
D2
D1
D0
R/W
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
¾
1
1
1
1
1
1
Bit 7~6
²¾² Unimplemented, read as 0
Bit 5~0
I/O Port B bit 5 ~ bit 0 input/output control
0: Output
1: Input
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Pin-remapping Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited
numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of
these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function
and a priority order is established where more than one pin function is selected simultaneously. Additionally there is a
PRM register to establish certain pin functions. Generally speaking, the analog function has higher priority than the digital
function. However, if more than two analog functions are enabled and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules.
Pin-remapping Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device
can contain. However by allowing the same pins to share several different functions and providing a means of function
selection, a wide range of different functions can be incorporated into even relatively small package sizes.
· PRM Register
Bit
7
6
5
4
3
2
1
0
Name
PRML3
PRML2
PRML1
PRML0
PRMS3
PRMS2
PRMS1
PRMS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
0
0
Bit 7~4
PRML3~PRML0: pin-remapping function lock bits (default: 0101)
1010: PRM register write operation is enabled
Others: PRM register write operation is disabled
Bit 3
PRMS3: INT1 pin-remapping function selection bit
0: INT1 on PA5
1: INT1 on PA4
Bit 2
PRMS2: INT0/TCK1 pin-remapping function selection bit
0: INT0 on PA3, TCK1 on PA3
1: INT0 on PA2, TCK1 on PA2
Bit 1~0
PRMS1~PRMS0: pin-remapping function selection bits
For HT66F017, HT68F017
0: TP0 on PA3, TP1/TCK0 on PA4
1: TP0 on PB0, TP1/TCK0 on PB1
2: TP0 on PA5, TP1/TCK0 on PA6
3: TP0 on PA2, TP1/TCK0 on PA7
For HT66F016, HT68F016
0: TP1 on PA4
1: TP1 on PB1
2: TP1 on PA6
3: TP1 on PA7
I/O Pin Structures
whether pull-high selections have been chosen. If the
port control registers, PAC and PBC, are then programmed to setup some pins as outputs, these output
pins will have an initial high output value unless the associated port data registers, PA and PB, are first programmed. Selecting which pins are inputs and which
are outputs can be achieved byte-wide by loading the
correct values into the appropriate port control register
or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
The accompanying diagrams illustrate the internal
structures of some generic I/O pin types. As the exact
logical construction of the I/O pin will differ from these
drawings, they are supplied as a guide only to assist
with the functional understanding of the I/O pins. The
wide range of pin-shared structures does not permit all
types to be shown.
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
The power-on reset condition of the A/D converter control registers ensures that any A/D input pins - which are
always shared with other I/O functions - will be setup as
analog inputs after a reset. Although these pins will be
configured as A/D inputs after a reset, the A/D converter
will not be switched on. It is therefore important to note
that if it is required to use these pins as I/O digital input
pins or as other functions, the A/D converter control registers must be correctly programmed to remove the A/D
function. Note also that as the A/D channel is enabled,
any internal pull-high resistor connections will be removed.
Port A has the additional capability of providing wake-up
functions. When the device is in the SLEEP or IDLE
Mode, various methods are available to wake the device
up. One of these is a high to low transition of any of the
Port A pins. Single or multiple pins on Port A can be
setup to have this function.
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
D D
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
I/O
R e a d C o n tr o l R e g is te r
p in
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
R e a d D a ta R e g is te r
S y s te m
V
P u ll- H ig h
R e g is te r
S e le c t
C o n tr o l B it
M
U
X
W a k e -u p
W a k e - u p S e le c t
P A o n ly
Generic Input/Output Structure
V
D a ta B u s
W r ite C o n tr o l R e g is te r
P u ll- H ig h
R e g is te r
S e le c t
C o n tr o l B it
Q
D
D D
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
A /D
C K
S
Q
M
R e a d D a ta R e g is te r
In p u t P in s
D a ta B it
Q
D
U
X
A n a lo g
In p u t
S e le c to r
T o A /D
C o n v e rte r
A C S 1 ~ A C S 0
A/D Input/Output Structure
Rev. 1.00
49
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Timer Modules - TM
One of the most fundamental functions in any
microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the
name TM. The TMs are multi-purpose timing units and
serve to provide operations such as Timer/Counter, Input
Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation
of PWM signals. Each of the TMs has either two individual interrupts. The addition of input and output pins for
each TM ensures that users are provided with timing
units with a wide and flexible range of features.
TM Operation
The two different types of TM offer a diverse range of
functions, from simple timing operations to PWM signal
generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose
va l u e i s t h e n co m p a r e d w i t h t h e va l u e o f
pre-programmed internal comparators. When the free
r u n n i n g co u n t e r h a s t h e sa m e va l u e a s t h e
pre-programmed comparator, known as a compare
match situation, a TM interrupt signal will be generated
which can clear the counter and perhaps also change
the condition of the TM output pin. The internal TM
counter is driven by a user selectable clock source,
which can be an internal clock or an external pin.
The common features of the different TM types are described here with more detailed information provided in
the individual Compact, Standard and Enhanced TM
sections.
TM Clock Source
The clock source which drives the main counter in each
TM can originate from various sources. The selection of
the required clock source is implemented using the
TnCK2~TnCK0 bits in the TM control registers. The
clock source can be a ratio of either the system clock
fSYS or the internal high clock fH, the fTBC clock source or
the external TCKn pin. Note that setting these bits to the
value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock
source is used to allow an external signal to drive the TM
as an external clock source or for event counting.
Introduction
The devices contain two TMs with each TM having a reference name of TM0 and TM1. Each individual TM can
be categorised as a certain type, namely Compact Type
TM (CTM) or Standard Type TM (STM). Although similar
in nature, the different TM types vary in their feature
complexity. The common features to all of the Compact
and Standard TMs will be described in this section and
the detailed operation regarding each of the TM types
will be described in separate sections. The main features and differences between the two types of TMs are
summarised in the accompanying table.
Function
CTM
STM
Timer/Counter
Ö
Ö
I/P Capture
¾
Ö
Compare Match Output
Ö
Ö
PWM Channels
1
1
Single Pulse Output
PWM Alignment
PWM Adjustment Period & Duty
¾
1
Edge
Edge
Duty or Period
Duty or Period
TM Function Summary
Each device in the series contains a Compact Type and/or Standard Type TM units which are shown in the table together with their individual reference name, TM0 and TM1.
Device
TM0
TM1
HT66F016, HT68F016
¾
16-bit STM
HT66F017, HT68F017
16-bit CTM
16-bit STM
TM Name/Type Reference
Rev. 1.00
50
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
TM Interrupts
enabled or disabled according to the internal TM on/off
control, operation mode and output control settings.
When the corresponding TM configuration selects the
TPn pin to be used as an output pin, the associated pin
will be setup as an external TM output pin. If the TM configuration selects the TPn pin to be setup as an input pin,
the input signal supplied on the associated pin can be
derived from an external signal and other pin-shared
output function. If the TM configuration determines that
the TPn pin function is not used, the associated pin will
be controlled by other pin-shared functions. The details
of the TPn pin for each TM type and device are provided
in the accompanying table.
The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator
A or comparator P, which generate a TM interrupt when
a compare match condition occurs. When a TM interrupt
is generated it can be used to clear the counter and also
to change the state of the TM output pin.
TM External Pins
Each of the TMs, irrespective of what type, has one TM
input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using
the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to
drive the internal TM. This external TM input pin is
shared with other functions but will be connected to the
internal TM if selected using the TnCK2~TnCK0 bits.
The TM input pin can be chosen to have either a rising or
falling active edge.
Device
CTM
STM
Registers
HT66F016
HT68F016
¾
TP1
TMPC
HT66F017
HT68F017
TP0
TP1
TMPC
TM Output Pins
The TMs each have one output pin with the label TPn.
When the TM is in the Compare Match Output Mode,
these pins can be controlled by the TM to switch to a
high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the
pin where the TM generates the PWM output waveform.
The TPn pin acts as an input when the TM is setup to operate in the Capture Input Mode. As the TPn pins are
pin-shared with other functions, the TPn pin function is
TM Input/Output Pin Control Registers
Selecting to have a TM input/output or whether to retain
its other shared functions is implemented using one register with a single bit in each register corresponding to a
TM input/output pin. Setting the bit high will setup the
corresponding pin as a TM input/output if reset to zero
the pin will retain its original other functions.
TMPC Register List
Device
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HT66F016
HT68F016
¾
¾
¾
¾
¾
¾
T1CP
¾
HT66F017
HT68F017
¾
¾
¾
¾
¾
¾
T1CP
T0CP
TM0
(CTM)
TP0
TP0
T0CP
TM1
(STM)
TP1
TP1
T1CP
TP1
TM Function Pin Control Block Diagram
Rev. 1.00
51
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· TMPC Register
¨
HT66F016/HT68F016
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
T1CP
¾
R/W
¾
¾
¾
¾
¾
¾
R/W
¾
POR
¾
¾
¾
¾
¾
¾
0
¾
Bit 7~2
Unimplemented, read as ²0²
Bit 1
T1CP: TP1 pin control
0: disable TP1 pin function
1: enable TP1 pin function
Bit 0
Unimplemented, read as ²0²
¨
HT66F017/HT68F017
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
¾
T1CP
T0CP
R/W
¾
¾
¾
¾
¾
¾
R/W
R/W
POR
¾
¾
¾
¾
¾
¾
0
0
Bit 7~2
Unimplemented, read as ²0²
Bit 1
T1CP: TP1 pin control
0: disable TP1 pin function
1: enable TP1 pin function
Bit 0
T0CP: TP0 Pin Control
0: Disable TP0 pin function
1: Enable TP0 pin function
Programming Considerations
TMxAL, using the following access procedures. Accessing the CCRA low byte registers without following
these access procedures will result in unpredictable values.
The TM Counter Registers and the Capture/Compare
CCRA registers, being 16-bit, all have a low and high
byte structure. The high bytes can be directly accessed,
but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs
must be carried out in a specific way. The important
point to note is that data transfer to and from the 8-bit
buffer and its related low byte only takes place when a
write or read operation to its corresponding high byte is
executed. As the CCRA registers are implemented in
the way shown in the following diagram and accessing
these register pairs is carried out in a specific way described above, it is recommended to use the ²MOV² instruction to access the CCRA low byte registers, named
The following steps show the read and write procedures:
· Writing data to CCRA
Step 2. Write data to High Byte TMxAH - here data
is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to
the Low Byte registers.
¨
Step 1. Read data from the High Byte TMxDH,
TMxAH - here data is read directly from the High
Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
¨
Step 2. Read data from the Low Byte TMxDL,
TMxAL - this step reads data from the 8-bit buffer.
TMxAH
TM CCRA Register (Read/Write)
Rev. 1.00
¨
TMxDH
8-bit
Buffer
TMxAL
Step 1. Write data to Low Byte TMxAL - note that
here data is only written to the 8-bit buffer.
· Reading Data from the Counter Registers and CCRA
TM Counter Register (Read only)
TMxDL
¨
Data
Bus
52
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Compact Type TM - CTM
Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are
Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with
an external input pin and can drive one external output pin.
CTM
Name
TM No.
TM Input Pin
TM Output Pin
HT66F017
HT68F017
16-bit CTM
0
TCK0
TP0
Compact TM Operation
At its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are
also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the
value in the counter with CCRP and CCRA registers. The CCRP is 8-bit wide whose value is compared with the highest
eight bits in the counter while the CCRA is 16-bit wide and therefore compares with all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare
match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be
generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different
clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.
C C R P
C o m p a ra to r P M a tc h
8 - b it C o m p a r a to r P
fS
Y S
/4
fS
Y S
fH /1 6
fH /6 4
fT B C
fH /8
T C K n
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
T n P F In te rru p t
b 8 ~ b 1 5
T n O C
C o u n te r C le a r
1 6 - b it C o u n t- u p C o u n te r
0
1
1 1 1
T n O N
T n M 1 , T n M 0
T n IO 1 , T n IO 0
T n C C L R
b 0 ~ b 1 5
O u tp u t
C o n tro l
P o la r ity
C o n tro l
T P n
T n P O L
T n P A U
1 6 - b it C o m p a r a to r A
C o m p a ra to r A
M a tc h
T n A F In te rru p t
T n C K 2 ~ T n C K 0
C C R A
Compact Type TM Block Diagram
Rev. 1.00
53
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Compact Type TM Register Description
Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the
internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. There is also
a read/write register used to store the internal 8-bit CCRP value. The remaining two registers are control registers
which setup the different operating and control modes.
CTM Register List
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TM0C0
T0PAU
T0CK2
T0CK1
T0CK0
T0ON
¾
¾
¾
TM0C1
T0M1
T0M0
T0IO1
T0IO0
T0OC
T0POL
T0DPX
T0CCLR
TM0DL
D7
D6
D5
D4
D3
D2
D1
D0
TM0DH
D15
D14
D13
D12
D11
D10
D9
D8
TM0AL
D7
D6
D5
D4
D3
D2
D1
D0
TM0AH
D15
D14
D13
D12
D11
D10
D9
D8
TM0RP
T0RP7
T0RP6
T0RP5
T0RP4
T0RP3
T0RP2
T0RP1
T0RP0
16-bit Compact TM Register List
· TM0DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM0DL: TM0 counter low byte register bit 7 ~ bit 0
TM0 16-bit Counter bit 7 ~ bit 0
· TM0DH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
TM0DH: TM0 counter high byte register bit 7 ~ bit 0
TM0 16-bit counter bit 15 ~ bit 8
· TM0AL Register
Bit
7
6
5
4
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM0AL: TM0 CCRA low byte register bit 7 ~ bit 0
TM0 16-bit CCRA bit 7 ~ bit 0
· TM0AH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
TM0AH: TM0 CCRA high byte register bit 7 ~ bit 0
TM0 16-bit CCRA bit 15 ~ bit 8
54
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· TM0C0 Register
Bit
7
6
5
4
3
2
1
0
Name
T0PAU
T0CK2
T0CK1
T0CK0
T0ON
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
0
¾
¾
¾
Bit 7
T0PAU: TM0 counter pause control
0: run
1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
Bit 6~4
T0CK2~T0CK0: Select TM0 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH/8
110: TCK0 rising edge clock
111: TCK0 falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock source can
be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock,
while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section.
Bit 3
T0ON: TM0 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T0OC bit, when the T0ON bit changes from low to high.
Bit 2~0
²¾² Unimplemented, read as 0
Rev. 1.00
55
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· TM0C1 Register
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
T0IO1
T0IO0
T0OC
T0POL
T0DPX
T0CCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
T0M1~T0M0: select TM0 operating mode
00: compare match output mode
01: undefined
10: PWM mode
11: Timer/Counter mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T0M1 and T0M0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T0IO1~T0IO0: Select TP0 output function
compare match output mode
00: no change
01: output low
10: output high
11: toggle output
PWM Mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Undefined
Timer/Counter mode
unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin can
be setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When the bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the T0OC bit in the TM0C1
register. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from
the initial value setup using the T0OC bit otherwise no change will occur on the TM output pin
when a compare match occurs. After the TM output pin changes state it can be reset to its initial
level by changing the level of the T0ON bit from low to high.
In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T0IO1 and T0IO0 bits only
after the TMn has been switched off. Unpredictable PWM outputs will occur if the T0IO1 and
T0IO0 bits are changed when the TM is running
Bit 3
T0OC: TP0 output control bit
compare match output mode
0: initial low
1: initial high
PWM mode
0: active low
1: active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is
in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of
the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM
signal is active high or active low.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Bit 2
T0POL: TP0 output polarity control
0: non-invert
1: invert
This bit controls the polarity of the TP0 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1
T0DPX: TM0 PWM period/duty control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
Bit 0
T0CCLR: select TM0 counter clear condition
0: TM0 Comparatror P match
1: TM0 Comparatror A match
This bit is used to select the method which clears the counter. Remember that the Compact TM
contains two comparators, Comparator A and Comparator P, either of which can be selected to
clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.
The T0CCLR bit is not used in the PWM Mode.
· TM0RP Register
Bit
7
6
5
4
3
2
1
0
Name
T0RP7
T0RP6
T0RP5
T0RP4
T0RP3
T0RP2
T0RP1
T0RP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
T0RP7~T0RP0: TM0 CCRP register bit 7~bit 0, compared with the TM0 counter bit 15~bit 8
Comparator P match period =
0: 65536 TM0 clocks
1~255: (1~255) ´ 256 TM0 clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then
compared with the internal counter's highest eight bits. The result of this comparison can be
selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter.
As the CCRP bits are only compared with the highest eight counter bits, the compare values
exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to
overflow at its maximum value.
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Compact Type TM Operating Modes
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all
zero, the counter will overflow when its reaches its maximum 16-bit, FFFF Hex, value, however here the TnAF
interrupt request flag will not be generated.
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM
Mode or Timer/Counter Mode. The operating mode is
selected using the TnM1 and TnM0 bits in the TMnC1
register.
As the name of the mode suggests, after a comparison
is made, the TM output pin will change state. The TM
output pin condition however only changes state when a
TnAF interrupt request flag is generated after a compare
match occurs from Comparator A. The TnPF interrupt
request flag, generated from a compare match occurs
from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state
are determined by the condition of the TnIO1 and TnIO0
bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go
low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON
bit changes from low to high, is setup using the TnOC
bit. Note that if the TnIO1 and TnIO0 bits are zero then
no pin change will take place.
Compare Match Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register, should be set to 00B respectively. In this mode
once the counter is enabled and running it can be
cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is
low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from
Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both
TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of
Counter Value
Counter overflow
CCRP=0
0xFFFF
TnCCLR = 0; TnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
Stop
CCRA
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 0
Note:
1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Counter Value
TnCCLR = 1; TnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 1
Note:
1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Timer/Counter Mode
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
extremely flexible. In the PWM mode, the TnCCLR bit
has no effect on the PWM operation. Both of the CCRA
and CCRP registers are used to generate the PWM
waveform, one register is used to clear the internal
counter and thus control the PWM waveform frequency,
while the other one is used to control the duty cycle.
Which register is used to control either frequency or duty
cycle is determined using the TnDPX bit in the TMnC1
register. The PWM waveform frequency and duty cycle
can therefore be controlled by the values in the CCRA
and CCRP registers.
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 11 respectively. The
Timer/Counter Mode operates in an identical way to the
Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter
Mode the TM output pin is not used. Therefore the
above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its
function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other
pin-shared function.
PWM Output Mode
An interrupt flag, one for each of the CCRA and CCRP,
will be generated when a compare match occurs from
either Comparator A or Comparator P. The TnOC bit in
the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and
TnIO0 bits are used to enable the PWM output or to
force the TM output pin to a fixed high or low level. The
TnPOL bit is used to reverse the polarity of the PWM
output waveform.
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively. The PWM function within the TM is useful for applications which require
functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a
square wave AC waveform can be generated with varying equivalent DC RMS values.
Counter Value
TnDPX = 0; TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Pause Resume
Counter Stop if
TnON bit low
CCRA
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode -- TnDPX = 0
Note:
1. Here TnDPX=0 -- Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.00
60
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
1~255
Period
CCRP ´ 256
Duty
0
65536
CCRA
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128
The CTM PWM output frequency = (fSYS/4) / (2´256) = fSYS/2048 = 7.8125 kHz, duty = 128 / (2´256) = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty
is 100%.
· 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
1~255
Period
Duty
0
CCRA
CCRP ´ 256
65536
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP´256) except when the CCRP value is equal to 0.
Counter Value
TnDPX = 1; TnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
TnON returns high
CCRA
Pause Resume
Counter Stop if
TnON bit low
CCRP
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode -- TnDPX = 1
Note:
1. Here TnDPX = 1 -- Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Standard Type TM - STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins.
STM
Name
TM No.
TM Input Pin
TM Output Pin
All devices
16-bit STM
1
TCK1
TP1
Standard TM Operation
also usually be generated. The Standard Type TM can
operate in a number of different operational modes, can
be driven by different clock sources including an input
pin and can also control an output pin. All operating
setup conditions are selected using relevant internal
registers.
At its core is a 16-bit count-up counter which is driven by
a user selectable internal or external clock source.
There are also two internal comparators with the names,
Comparator A and Comparator P. These comparators
will compare the value in the counter with CCRP and
CCRA registers. The CCRP comparator is 8-bit wide
whose value is compared with the highest eight bits in
the counter while the CCRA is 16-bit wide and therefore
compares with all counter bits.
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using
a series of registers. A read only register pair exists to
store the internal counter 16-bit value, while a read/write
register pair exists to store the internal 16-bit CCRA
value. There is also a read/write register used to store
the internal 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes.
The only way of changing the value of the 16-bit counter
using the application program, is to clear the counter by
changing the TnON bit from low to high. The counter will
also be cleared automatically by a counter overflow or a
compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will
C C R P
C o m p a ra to r P M a tc h
8 - b it C o m p a r a to r P
fS
Y S
/4
fS
Y S
fH /1 6
fH /6 4
fT B C
fH /8
T C K n
b 8 ~ b 1 5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
T n P F In te rru p t
T n O C
T n O N
T n P A U
1
T n C C L R
b 0 ~ b 1 5
1 6 - b it
C o m p a ra to r A
0
C o u n te r C le a r
1 6 - b it C o u n t- u p C o u n te r
C o m p a ra to r A
M a tc h
O u tp u t
C o n tro l
P o la r ity
C o n tro l
T n M 1 , T n M 0
T n IO 1 , T n IO 0
T n P O L
T P n
T n A F In te rru p t
T n IO 1 , T n IO 0
T n C K 2 ~ T n C K 0
C C R A
E d g e
D e te c to r
Standard Type TM Block Diagram
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
STM Register List
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TM1C0
T1PAU
T1CK2
T1CK1
T1CK0
T1ON
¾
¾
¾
TM1C1
T1M1
T1M0
T1IO1
T1IO0
T1OC
T1POL
T1DPX
T1CCLR
TM1DL
D7
D6
D5
D4
D3
D2
D1
D0
TM1DH
D15
D14
D13
D12
D11
D10
D9
D8
TM1AL
D7
D6
D5
D4
D3
D2
D1
D0
TM1AH
D15
D14
D13
D12
D11
D10
D9
D8
TM1RP
T1RP7
T1RP6
T1RP5
T1RP4
T1RP3
T1RP2
T1RP1
T1RP0
16-bit Standard TM Register List
· TM1C0 Register
Bit
7
6
5
4
3
2
1
0
Name
T1PAU
T1CK2
T1CK1
T1CK0
T1ON
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
0
¾
¾
¾
Bit 7
T1PAU: TM1 counter pause control
0: run
1: pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores normal
counter operation. When in a Pause condition the TM will remain powered up and continue to
consume power. The counter will retain its residual value when this bit changes from low to high
and resume counting from this value when the bit changes to a low value again.
Bit 6~4
T1CK2~T1CK0: select TM1 counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH/8
110: TCK1 rising edge clock
111: TCK1 falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock source can
be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock,
while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section.
Bit 3
T1ON: TM1 counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to
run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting
and turn off the TM which will reduce its power consumption. When the bit changes state from
low to high the internal counter value will be reset to zero, however when the bit changes from
high to low, the internal counter will retain its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
Bit 2~0
Rev. 1.00
unimplemented, read as 0
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· TM1C1 Register
Bit
7
6
5
4
3
2
1
0
Name
T1M1
T1M0
T1IO1
T1IO0
T1OC
T1POL
T1DPX
T1CCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
T1M1~T1M0: select TM1 operating mode
00: Compare match output mode
01: Capture input mode
10: PWM mode or single pulse output mode
11: Timer/Counter mode
These bits setup the required operating mode for the TM. To ensure reliable operation the TM
should be switched off before any changes are made to the T1M1 and T1M0 bits. In the
Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T1IO1~T1IO0: select TP1 output function
Compare match output mode
00: no change
01: output low
10: output high
11: toggle output
PWM mode/single pulse output mode
00: PWM output inactive state
01: PWM output active state
10: PWM output
11: Single pulse output
Capture input mode
00: input capture at rising edge of TP1
01: input capture at falling edge of TP1
10: input capture at falling/rising edge of TP1
11: input capture disabled
Timer/counter mode
Unused
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin can
be setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When the bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1
register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from
the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin
when a compare match occurs. After the TM output pin changes state it can be reset to its initial
level by changing the level of the T1ON bit from low to high.
In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the T1IO1 and T1IO0 bits only
after the TM has been switched off. Unpredictable PWM outputs will occur if the T1IO1 and
T1IO0 bits are changed when the TM is running
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Bit 3
T1OC: TP1 output control bit
Compare match output mode
0: initial low
1: initial high
PWM mode/single pulse output mode
0: active low
1: active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2
T1POL: TP1 output polarity control
0: non-invert
1: invert
This bit controls the polarity of the TP1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter mode.
Bit 1
T1DPX: TM1 PWM period/duty control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
Bit 0
T1CCLR: select TM1 counter clear condition
0: TM1 Comparatror P match
1: TM1 Comparatror A match
This bit is used to select the method which clears the counter. Remember that the Standard
TM contains two comparators, Comparator A and Comparator P, either of which can be selected
to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
· TM1DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
TM1DL: TM1 counter low byte register bit 7~bit 0
TM1 16-bit counter bit 7~bit 0
· TM1DH Register
Bit
7
6
5
4
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
TM1DH: TM1 counter high byte register bit 7~bit 0
TM1 16-bit Counter bit 15~bit 8
65
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· TM1AL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7~0
TM1AL: TM1 CCRA low byte register bit 7~bit 0
TM1 16-bit CCRA bit 7~bit 0
· TM1AH Register
Bit
7
6
5
4
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM1AH: TM1 CCRA high byte register bit 7~bit 0
TM1 16-bit CCRA bit 15~bit 8
· TM1RP Register
Bit
7
6
5
4
3
2
1
0
Name
T1RP7
T1RP6
T1RP5
T1RP4
T1RP3
T1RP2
T1RP1
T1RP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
T1RP7~T1RP0: TM1 CCRP register bit 7~bit 0, compared with the TM1 counter bit 15~bit 8
Comparator P Match Period =
0: 65536 TM1 clocks
1~255: (1~255) ´ 256 TM1 clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then
compared with the internal counter's highest eight bits. The result of this comparison can be
selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256
clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at
its maximum value.
66
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Standard Type TM Operating Modes
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to 0.
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM
Mode, Single Pulse Output Mode, Capture Input Mode
or Timer/Counter Mode. The operating mode is selected
using the TnM1 and TnM0 bits in the TMnC1 register.
As the name of the mode suggests, after a comparison
is made, the TM output pin, will change state. The TM
output pin condition however only changes state when a
TnAF interrupt request flag is generated after a compare
match occurs from Comparator A. The TnPF interrupt
request flag, generated from a compare match occurs
from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state
are determined by the condition of the TnIO1 and TnIO0
bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go
low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON
bit changes from low to high, is setup using the TnOC
bit. Note that if the TnIO1 and TnIO0 bits are zero then
no pin change will take place.
Compare Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register, should be set to 00 respectively. In this mode
once the counter is enabled and running it can be
cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is
low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which
allows the counter to overflow. Here both TnAF and
TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
from Comparator A. However, here only the TnAF inter-
Counter Value
Counter overflow
CCRP=0
0xFFFF
TnCCLR = 0; TnM [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
Stop
CCRA
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by TnAF
flag. Remains High until reset
by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 0
Note:
1. With TnCCLR=0, a Comparator P match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
Rev. 1.00
67
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Counter Value
TnCCLR = 1; TnM [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0xFFFF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
TnON
TnPAU
TnPOL
No TnAF flag
generated on
CCRA overflow
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnPF not
generated
Output does
not change
TM O/P Pin
Output pin set to
initial Level Low
if TnOC=0
Output not affected by
TnAF flag. Remains High
until reset by TnON bit
Output Toggle with
TnAF flag
Here TnIO [1:0] = 11
Toggle Output select
Note TnIO [1:0] = 10
Active High Output select
Output Inverts
when TnPOL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode -- TnCCLR = 1
Note:
1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. A TnPF flag is not generated when TnCCLR=1
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Timer/Counter Mode
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
extremely flexible. In the PWM mode, the TnCCLR bit
has no effect on the PWM operation. Both of the CCRA
and CCRP registers are used to generate the PWM
waveform, one register is used to clear the internal
counter and thus control the PWM waveform frequency,
while the other one is used to control the duty cycle.
Which register is used to control either frequency or duty
cycle is determined using the TnDPX bit in the TMnC1
register. The PWM waveform frequency and duty cycle
can therefore be controlled by the values in the CCRA
and CCRP registers.
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 11 respectively. The
Timer/Counter Mode operates in an identical way to the
Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter
Mode the TM output pin is not used. Therefore the
above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its
function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other
pin-shared function.
PWM Output Mode
An interrupt flag, one for each of the CCRA and CCRP,
will be generated when a compare match occurs from
either Comparator A or Comparator P. The TnOC bit in
the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and
TnIO0 bits are used to enable the PWM output or to
force the TM output pin to a fixed high or low level. The
TnPOL bit is used to reverse the polarity of the PWM
output waveform.
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively. The PWM function within the TM is useful for applications which require
functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a
square wave AC waveform can be generated with varying equivalent DC RMS values.
Counter Value
TnDPX = 0; TnM [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
TnON returns high
CCRP
Pause Resume
Counter Stop if
TnON bit low
CCRA
Time
TnON
TnPAU
TnPOL
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode -- TnDPX = 0
Note:
1. Here TnDPX=0 -- Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=0
CCRP
1~255
Period
CCRP ´ 256
Duty
0
65536
CCRA
If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128
The STM PWM output frequency = (fSYS/4) / (2´256) = fSYS/2048 = 7.8125kHz, duty = 128 / (2´256) = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty
is 100%.
· 16-bit STM, PWM Mode, Edge-aligned Mode, TnDPX=1
CCRP
1~255
Period
Duty
0
CCRA
CCRP ´ 256
65536
The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP´256) except when the CCRP value is equal to 0.
Counter Value
TnDPX = 1; TnM [1:0] = 10
Counter cleared
by CCRA
Counter Reset when
TnON returns high
CCRA
Pause Resume
Counter Stop if
TnON bit low
CCRP
Time
TnON
TnPAU
TnPOL
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
PWM Duty Cycle
set by CCRP
PWM Period
set by CCRA
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when TnPOL = 1
PWM Mode -- TnDPX = 1
Note:
1. Here TnDPX=1 -- Counter cleared by CCRA
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Single Pulse Mode
automatically change from low to high using the external
TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the
counter will start running and the pulse leading edge will
be generated. The TnON bit should remain high when
the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared
to zero, which can be implemented using the application
program or when a compare match occurs from Comparator A.
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively and also the
TnIO1 and TnIO0 bits should be set to 11 respectively.
The Single Pulse Output Mode, as the name suggests,
will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to
high transition of the TnON bit, which can be implemented using the application program. However in the
Single Pulse Mode, the TnON bit can also be made to
S /W
C o m m a n d
S E T "T n O N "
o r
T C K n P in T r a n s itio n
L e a d in g E d g e
T r a ilin g E d g e
T n O N b it
0 ® 1
T n O N b it
1 ® 0
S /W C o m m a n d
C L R "T n O N "
o r
C C R A M a tc h C o m p a re
T M n O u tp u t P in
P u ls e W id th = C C R A V a lu e
Single Pulse Generation
Counter Value
TnM [1:0] = 10 ; TnIO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
TnON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
TnON
Software
Trigger
Auto. set by
TCKn pin
Cleared by
CCRA match
Software
Trigger
TCKn pin
Software
Trigger
Software
Clear
Software
Trigger
TCKn pin
Trigger
TnPAU
TnPOL
CCRP Int.
Flag TnPF
No CCRP Interrupts
generated
CCRA Int.
Flag TnAF
TM O/P Pin
(TnOC=1)
TM O/P Pin
(TnOC=0)
Output Inverts
when TnPOL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note:
1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse triggered by the TCKn pin or by setting the TnON bit high
4. A TCKn pin active edge will automatically set the TnON bit high.
5. In the Single Pulse Mode, TnIO [1:0] must be set to ²11² and can not be changed.
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
However a compare match from Comparator A will also
automatically clear the TnON bit and thus generate the
Single Pulse output trailing edge. In this way the CCRA
value can be used to control the pulse width. A compare
match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when
the TnON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used.
The TnCCLR and TnDPX bits are not used in this Mode.
the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn pin the counter will continue to free run until the TnON bit changes
from high to low. When a CCRP compare match occurs,
the counter will reset back to zero; in this way the CCRP
value can be used to control the maximum counter
value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated.
Counting the number of overflow interrupt signals from
the CCRP can be a useful method in measuring long
pulse widths. The TnIO1 and TnIO0 bits can select the
active trigger edge on the TPn pin to be a rising edge,
falling edge or both edge types. If the TnIO1 and TnIO0
bits are both set high, then no capture operation will take
place irrespective of what happens on the TPn pin, however it must be noted that the counter will continue to
run.
Capture Input Mode
To select this mode bits TnM1 and TnM0 in the TMnC1
register should be set to 01 respectively. This mode enables external signals to capture and store the present
value of the internal counter and can therefore be used
for applications such as pulse width measurements.
The external signal is supplied on the TPn pin, whose
active edge can be either a rising edge, a falling edge or
both rising and falling edges; the active edge transition
type is selected using the TnIO1 and TnIO0 bits in the
TMnC1 register. The counter is started when the TnON
bit changes from low to high which is initiated using the
application program.
As the TPn pin is pin shared with other functions, care
must be taken if the TM is in the Input Capture Mode.
This is because if the pin is setup as an output, then any
transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are
not used in this Mode.
When the required edge transition appears on the TPn
pin, the present value in the counter will be latched into
Counter Value
TnM [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
Resume
YY
Pause
XX
Time
TnON
TnPAU
Active
edge
Active
edge
TM capture
pin TPn_x
Active edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value
TnIO [1:0]
Value
XX
00
Rising edge
01
YY
Falling edge
XX
10
Both edges
YY
11
Disable Capture
Capture Input Mode
Note:
1. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. The TnCCLR bit is not used
4. No output function -- TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal
to zero.
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Analog to Digital Converter
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
Part No.
Input
Channels
A/D Channel
Select Bits
Input
Pins
HT66F016
HT66F017
4
ACS4,
ACS1~ACS0
AN0~AN3
HT68F016
HT68F017
¾
¾
¾
The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers.
A/D Overview
The device contains a multi-channel analog to digital
converter which can directly interface to external analog
signals, such as that from sensors or other control signals and convert these signals directly into either a
12-bit digital value.
A/D Converter Register Description
Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store
the ADC data 12-bit value. The remaining three registers are control registers which setup the operating and
control function of the A/D converter.
Bit
Register
Name
7
6
5
4
3
2
1
0
ADRL(ADRFS=0)
D3
D2
D1
D0
¾
¾
¾
¾
ADRL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
ADRH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
¾
¾
¾
¾
D11
D10
D9
D8
ADCR0
START
EOCB
ADOFF
ADRFS
¾
¾
ACS1
ACS0
ADCR1
ACS4
V125EN
¾
VREFS
¾
ADCK2
ADCK1
ADCK0
ACERL
¾
¾
¾
¾
ACE3
ACE2
ACE1
ACE0
ADRH(ADRFS=1)
A/D Converter Register List
A/D Converter Data Registers - ADRL, ADRH
As the devices contain an internal 12-bit A/D converter, they require two data registers to store the converted value.
These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process
takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only
12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the
ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits
will be read as zero.
ADRFS
ADRH
7
6
5
4
0
D11
D10
D9
D8
1
0
0
0
0
3
ADRL
2
1
0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Data Registers
Rev. 1.00
73
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
A/D Converter Control Registers ADCR0, ADCR1, ACERL
T h e A C E R L co n t r o l r e g i st e r co n t a i n s t h e
ACER3~ACER0 bits which determine which pins on
PA0~PA3 are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D
converter input. Setting the corresponding bit high will
select the A/D input function, clearing the bit to zero will
select either the I/O or other pin-shared function. When
the pin is selected to be an A/D input, its original function
whether it is an I/O or other pin-shared function will be
removed. In addition, any internal pull-high resistors
connected to these pins will be automatically removed if
the pin is selected to be an A/D input.
To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1
and ACERL are provided. These 8-bit registers define
functions such as the selection of which analog channel
is connected to the internal A/D converter, the digitised
data format, the A/D clock source as well as controlling
the start function and monitoring the A/D converter end
of conversion status. The ACS1~ACS0 bits in the
ADCR0 register and ACS4 bit is the ADCR1 register define the ADC input channel number. As the device contains only one actual analog to digital converter
hardware circuit, each of the individual 4 analog inputs
must be routed to the converter. It is the function of the
ACS4 and ACS1~ACS0 bits to determine which analog
channel input pins or internal 1.25V is actually connected to the internal A/D converter.
A D C K 2 ~ A D C K 0
A C E 3 ~ A C E 0
P A 0
P A 1
P A 2
P A 3
/A N
/A N
/A N
/A N
A /D
fS
Y S
¸ 2
N
V
D D
P A 1 /V R E F
(N = 0 ~ 6 )
C lo c k
A D O F F
B it
V R E F S
B it
A /D
0
1
A /D
2
A D R L
C o n v e rte r
A D R H
3
V
1 .2 5 V
V 1 2 5 E N
A C S 4 ,
A C S 1 ~ A C S 0
S T A R T
E O C B
R e fe r e n c e V o lta g e
S S
A /D D a ta
R e g is te r s
A D R F S
b it
A D O F F
A/D Converter Structure
Rev. 1.00
74
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· ADCR0 Register
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
ADOFF
ADRFS
¾
¾
ACS1
ACS0
R/W
R/W
R
R/W
R/W
¾
¾
R/W
R/W
POR
0
1
1
0
¾
¾
0
0
Bit 7
START: start the A/D conversion
0®1®0 : start
0®1
: reset the A/D converter and set EOCB to ²1²
This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and
then cleared low again, the A/D converter will initiate a conversion process. When the bit is set
high the A/D converter will be reset.
Bit 6
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed. When
the conversion process is running the bit will be high.
Bit 5
ADOFF : A/D module power on/off control bit
0: ADC module power on
1: ADC module power off
This bit controls the power to the A/D internal function. This bit should be cleared to zero to
enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing
the device power consumption. As the A/D converter will consume a limited amount of power,
even when not executing a conversion, this may be an important consideration in power sensitive
battery powered applications.
Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving
power.
2. ADOFF=1 will power down the ADC module.
Bit 4
ADRFS: A/D data format control bit
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data registers.
Details are provided in the A/D data register section.
Bit 3~2
unimplemented, read as ²0²
Bit 1~0
ACS1, ACS0: Select A/D channel (when ACS4 is ²0²)
00: AN0
01: AN1
10: AN2
11: AN3
Rev. 1.00
75
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· ADCR1 Register
Bit
7
6
5
4
3
2
1
0
Name
ACS4
V125EN
¾
VREFS
¾
ADCK2
ADCK1
ADCK0
R/W
R/W
R/W
¾
R/W
¾
R/W
R/W
R/W
POR
0
0
¾
0
¾
0
0
0
Bit 7
ACS4: select internal 1.25V as ADC input control
0: disable
1: enable
This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have
been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the
ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other
A/D input channels disconnected.
Bit 6
V125EN: internal 1.25V control
0: disable
1: enable
This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit
is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by
the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be
automatically switched off to conserve power. When 1.25V is switched on for use by the A/D
converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing
an A/D conversion.
Bit 5
unimplemented, read as ²0²
Bit 4
VREFS: selecte ADC reference voltage
0: internal ADC power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the
A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the
internal reference is used which is taken from the power supply pin VDD. When the A/D
converter reference voltage is supplied on the external VREF pin which is pin-shared with other
functions, all of the pin-shared functions except VREF on this pin are disabled.
Bit 3
unimplemented, read as ²0²
Bit 2~0
ADCK2, ADCK1, ADCK0: select ADC clock source
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: undefined
These three bits are used to select the clock source for the A/D converter.
Rev. 1.00
76
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· ACERL Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
ACE3
ACE2
ACE1
ACE0
R/W
¾
¾
¾
¾
R/W
R/W
R/W
R/W
POR
¾
¾
¾
¾
1
1
1
1
Bit 7~4
unimplemented, read as ²0²
Bit 3
ACE3: Define PA3 is A/D input or not
0: not A/D input
1: A/D input, AN3
Bit 2
ACE2: Define PA2 is A/D input or not
0: not A/D input
1: A/D input, AN2
Bit 1
ACE1: Define PA1 is A/D input or not
0: not A/D input
1: A/D input, AN1
Bit 0
ACE0: Define PA0 is A/D input or not
0: not A/D input
1: A/D input, AN0
A/D Operation
The clock source for the A/D converter, which originates
from the system clock fSYS, can be chosen to be either
fSYS or a subdivided version of fSYS. The division ratio
value is determined by the ADCK2~ADCK0 bits in the
ADCR1 register.
The START bit in the ADCR0 register is used to start
and reset the A/D converter. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR0 register will be set high and
the analog to digital converter will be reset. It is the
START bit that is used to control the overall start operation of the internal analog to digital converter.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are
some limitations on the A/D clock source speed range
that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5ms to 10ms,
care must be taken for selected system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be
set to 000B or 110B. Doing so will give A/D clock periods
that are less than the minimum A/D clock period or
greater than the maximum A/D clock period which may
result in inaccurate A/D conversion values. Refer to the
following table for examples, where values marked with
an asterisk * show where, depending upon the device,
special care must be taken, as the values may be less
than the specified minimum A/D Clock Period.
The EOCB bit in the ADCR0 register is used to indicate
when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR0 register to check
whether it has been cleared as an alternative method of
detecting the end of an A/D conversion cycle.
Rev. 1.00
77
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
A/D Clock Period (tADCK)
fSYS
1MHz
ADCK2,
ADCK1,
ADCK0
= 000
(fSYS)
ADCK2,
ADCK1,
ADCK0
= 001
(fSYS/2)
ADCK2,
ADCK1,
ADCK0
= 010
(fSYS/4)
ADCK2,
ADCK1,
ADCK0
= 011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
= 100
(fSYS/16)
ADCK2,
ADCK1,
ADCK0
= 101
(fSYS/32)
ADCK2,
ADCK1,
ADCK0
= 110
(fSYS/64)
ADCK2,
ADCK1,
ADCK0
= 111
1ms
2ms
4ms
8ms
16ms*
32ms*
64ms*
Undefined
2MHz
500ns
1ms
2ms
4ms
8ms
16ms*
32ms*
Undefined
4MHz
250ns*
500ns
1ms
2ms
4ms
8ms
16ms*
Undefined
8MHz
125ns*
250ns*
500ns
1ms
2ms
4ms
8ms
Undefined
12MHz
83ns*
167ns*
333ns*
667ns
1.33ms
2.67ms
5.33ms
Undefined
A/D Clock Period Examples
The A/D converter has its own reference voltage pin
VREF however the reference voltage can also be supplied from the power supply pin, a choice which is made
through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value
of VREF.
Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in
the ADCR0 register. This bit must be zero to power on
the A/D converter. When the ADOFF bit is cleared to
zero to power on the A/D converter internal circuitry a
certain delay, as indicated in the timing diagram, must
be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs by clearing
the ACE3~ACE0 bits in the ACERL register, if the
ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore
recommended that the ADOFF is set high to reduce
power consumption when the A/D converter function is
not being used.
P A 0 /A N 0
1 .2 5 V
A C S 4 , A C S 1 ~ A C S 0
In p u t V o lta g e
1 2 - b it A D C
B u ffe r
V R E F S
V D D
The reference voltage supply to the A/D Converter can
be supplied from either the positive power supply pin,
VDD, or from an external reference sources supplied on
pin VREF. The desired selection is made using the
VREFS bit. As the VREF pin is pin-shared with other
functions, when the VREFS bit is set high, the VREF pin
function will be selected and the other pin functions will
be disabled automatically.
V
R E F
V 1 2 5 E N
B a n d g a p
R e fe re n c e
V o lta g e
P A 1 /V R E F
A/D Input Structure
Summary of A/D Conversion Steps
The following summarises the individual steps that
should be executed in order to implement an A/D conversion process.
A/D Input Pins
· Step 1
All of the A/D analog input pins are pin-shared with the
I/O pins on PA3~PA0 as well as other functions. The
ACE3~ ACE0 bits in the ACERL register determines
whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the
ACE3~ ACE0 bits for its corresponding pin is set high
then the pin will be setup to be an A/D converter input
and the original pin functions disabled. In this way, pins
can be changed under program control to change their
function between A/D inputs and other functions. All
pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins
are setup as A/D inputs. Note that it is not necessary to
first setup the A/D pin as an input in the PAC port control
register to enable the A/D input as when the ACE3~
ACE0 bits enable an A/D input, the status of the port
control register will be overridden.
Rev. 1.00
P A 3 /A N 3
Select the required A/D conversion clock by correctly
programming bits ADCK2~ADCK0 in the ADCR1 register.
· Step 2
Enable the A/D by clearing the ADOFF bit in the
ADCR0 register to zero.
· Step 3
Select which channel is to be connected to the internal
A/D converter by correctly programming the ACS4
and ACS1~ACS0 bits which are also contained in the
ADCR1 and ADCR0 registers.
· Step 4
Select which pins are to be used as A/D inputs and
configure them by correctly programming the
ACE3~ACE0 bits in the ACERL register.
78
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· Step 5
The power-on reset condition of the A/D converter control registers will ensure that the shared function pins
are setup as A/D converter inputs. If any of the A/D converter input pins are to be used for functions, then the
A/D converter control register bits must be properly
setup to disable the A/D input configuration.
If the interrupts are to be used, the interrupt control
registers must be correctly configured to ensure the
A/D converter interrupt function is active. The master
interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set to high to do this.
· Step 6
A/D Transfer Function
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR0 register from low to high and then to low again. Note that
this bit should have been originally cleared to 0.
As the devices contain a 12-bit A/D converter, its
full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the
VDD or VREF voltage, this gives a single bit analog input
value of VDD or VREF divided by 4096.
· Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register
can be polled. The conversion process is complete
when this bit goes low. When this occurs, the A/D data
registers ADRL and ADRH can be read to obtain the
conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur.
Note: When checking for the end of the conversion
process, if the method of polling the EOCB bit in the
ADCR0 register is used, the interrupt enable step
above can be omitted.
1 LSB= (VDD or VREF) ¸ 4096
The A/D Converter input voltage value can be
calculated using the following equation:
A/D input voltage =
A/D output digital value ´ (VDD or VREF) ¸ 4096
The diagram shows the ideal transfer function between
the analog input value and the digitised output value for
the A/D converter. Except for the digitised zero value,
the subsequent digitised values will change at a point
0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a
point 1.5 LSB below the VDD or VREF level.
The accompanying diagram shows graphically the various stages involved in an analog to digital conversion
process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to
carry out the conversion, during which time the program
can continue with other functions. The time taken for the
A/D conversion is 16tADCK where tADCK is equal to the A/D
clock period.
A/D Programming Example
The following two programming examples illustrate how
to setup and implement an A/D conversion. In the first
example, the method of polling the EOCB bit in the
ADCR0 register is used to detect when the conversion
cycle is complete, whereas in the second example, the
A/D interrupt is used to determine when the conversion
is complete.
Programming Considerations
During microcontroller operates where the A/D converter is not being used, the A/D internal circuitry can be
switched off to reduce power consumption, by setting bit
ADOFF high in the ADCR0 register. When this happens,
the internal A/D converter circuits will not consume
power irrespective of what analog voltage is applied to
their input lines. If the A/D converter input lines are used
as normal I/Os, then care must be taken as if the input
voltage is not at a valid logic level, then this may lead to
some increase in power consumption.
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
A D O F F
tO
A D C
M o d u le
O N
o ff
N 2 S T
o n
A /D
tA
D S
s a m p lin g tim e
A /D
tA
D S
o ff
s a m p lin g tim e
o n
S T A R T
E O C B
A C S 4 , A C S 1 ,
A C S 0
0 1 1 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e p o r t c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
E n d o f A /D
c o n v e r s io n
tA D C
c o n v e r s io n tim e
A /D
tA D C
c o n v e r s io n tim e
A/D Conversion Timing
1 .5 L S B
F F F H
F F E H
F F D H
A /D C o n v e r s io n
R e s u lt
0 .5 L S B
0 3 H
0 2 H
0 1 H
0
1
2
3
4 0 9 3 4 0 9 4
4 0 9 5 4 0 9 6
(
V
D D
o r V
4 0 9 6
R E F
)
A n a lo g In p u t V o lta g e
Ideal A/D Transfer Function
Rev. 1.00
80
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Example: using an EOCB polling method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,03H
mov ADCR1,a
; select fSYS/8 as A/D clock and switch off 1.25V
clr ADOFF
mov a,0Fh
; setup ACERL to configure pins AN0~AN3
mov ACERL,a
mov a,00h
mov ADCR0,a
; enable and connect AN0 channel to A/D converter
:
start_conversion:
clr START
; high pulse on start bit to initiate conversion
set START
; reset A/D
clr START
; start A/D
polling_EOC:
sz
EOCB
; poll the ADCR0 register EOCB bit to detect end
; of A/D conversion
jmp polling_EOC
; continue polling
mov a,ADRL
; read low byte conversion result value
mov ADRL_buffer,a
; save result to user defined register
mov a,ADRH
; read high byte conversion result value
mov ADRH_buffer,a
; save result to user defined register
:
:
jmp start_conversion ; start next a/d conversion
Example: using the interrupt method to detect the end of conversion
clr ADE
; disable ADC interrupt
mov a,03H
mov ADCR1,a
; select fSYS/8 as A/D clock and switch off 1.25V
Clr ADOFF
mov a,0Fh
; setup ACERL to configure pins AN0~AN3
mov ACERL,a
mov a,00h
mov ADCR0,a
; enable and connect AN0 channel to A/D converter
Start_conversion:
clr START
; high pulse on START bit to initiate conversion
set START
; reset A/D
clr START
; start A/D
clr ADF
; clear ADC interrupt request flag
set ADE
; enable ADC interrupt
set EMI
; enable global interrupt
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a
; save ACC to user defined memory
mov a,STATUS
mov status_stack,a
; save STATUS to user defined memory
:
:
mov a,ADRL
; read low byte conversion result value
mov adrl_buffer,a
; save result to user defined register
mov a,ADRH
; read high byte conversion result value
mov adrh_buffer,a
; save result to user defined register
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a
; restore STATUS from user defined memory
mov a,acc_stack
; restore ACC from user defined memory
reti
Rev. 1.00
81
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HT66F016/HT66F017/HT68F016/HT68F017
Comparators
Comparator Interrupt
An analog comparator is contained within these devices. These functions offer flexibility via their register
controlled features such as power-down, polarity select,
hysteresis etc. In sharing their pins with normal I/O pins
the comparators do not waste precious I/O pins if there
functions are otherwise unused.
C P O L
The comparator possesses its own interrupt function.
When the comparator output changes state, its relevant
interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt
vector will be executed. Note that it is the changing state
of the COUT bit and not the output pin which generates
an interrupt. If the microcontroller is in the SLEEP or
IDLE Mode and the Comparator is enabled, then if the
external input lines cause the Comparator output to
change state, the resulting generated interrupt flag will
also generate a wake-up. If it is required to disable a
wake-up from occurring, then the interrupt flag should
be first set high before entering the SLEEP or IDLE
Mode.
C O U T
C +
C X
C -
C S E L
Comparator
Comparator Operation
The device contains a comparator function which is
used to compare two analog voltages and provide an
output based on their difference. Full control over the internal comparators is provided via the control register
CPC assigned to the comparator. The comparator output is recorded via a bit in the control register, but can
also be transferred out onto a shared I/O pin. Additional
comparator functions include, output polarity, hysteresis
functions and power down control.
Programming Considerations
If the comparator is enabled, it will remain active when
the microcontroller enters the SLEEP or IDLE Mode,
however as it will consume a certain amount of power,
the user may wish to consider disabling it before the
SLEEP or IDLE Mode is entered.
As comparator pins are shared with normal I/O pins the
I/O registers for these pins will be read as zero (port control register is ²1²) or read as port data register value
(port control register is ²0²) if the comparator function is
enabled.
Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected
when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output
due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis
function will apply a small amount of positive feedback
to the comparator. Ideally the comparator should switch
at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here.
The hysteresis function, if enabled, also increases the
switching offset value.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
· CPC Register
Bit
7
6
5
4
3
2
1
0
Name
CSEL
CEN
CPOL
COUT
COS
¾
¾
CHYEN
R/W
R/W
R/W
R/W
R
R/W
¾
¾
R/W
POR
1
0
0
0
0
¾
¾
1
Bit 7
CSEL: Select Comparator pins or I/O pins
0: I/O pin select
1: Comparator pin select
This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected
and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O
pin functions. Any pull-high configuration options associated with the comparator shared pins will
also be automatically disconnected.
Bit 6
CEN: Comparator On/Off control
0: Off
1: On
This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off
and no power consumed even if analog voltages are applied to its inputs. For power sensitive
applications this bit should be cleared to zero if the comparator is not used or before the device
enters the SLEEP or IDLE mode.
Bit 5
CPOL: Comparator output polarity
0: output not inverted
1: output inverted
This is the comparator polarity bit. If the bit is zero then the COUT bit will reflect the
non-inverted output condition of the comparator. If the bit is high the comparator COUT bit will
be inverted.
Bit 4
COUT: Comparator output bit
CPOL=0
0: C+ < C1: C+ > CCPOL=1
0: C+ > C1: C+ < CThis bit stores the comparator output bit. The polarity of the bit is determined by the voltages
on the comparator inputs and by the condition of the CPOL bit.
Bit 3
CS: Output path select
0: CX pin
1: Internal use
This is the comparator output path select control bit. If the bit is set to ²0² and the CSEL bit is
²1² the comparator output is connected to an external CX pin. If the bit is set to ²1² or the
CSEL bit is ²0² the comparator output signal is only used internally by the device allowing the
shared comparator output pin to retain its normal I/O operation.
Bit 2~1
unimplemented, read as ²0²
Bit 0
CHYEN: Hysteresis Control
0: Off
1: On
This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the
comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback
induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer Module or an A/D converter requires
microcontroller attention, their corresponding interrupt
will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to
their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external
INT pin, while the internal interrupts are generated by
various internal functions such as the TMs, Comparator,
Time Base, LVD, EEPROM, SIM and the A/D converter.
Each register contains a number of enable bits to enable
or disable individual interrupts as well as interrupt flags
to indicate the presence of an interrupt request. The
naming convention of these follows a specific pattern.
First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an ²E²
for enable/ disable bit or ²F² for request flag.
Function
Global
INTn Pin
Enable Request
Bit
Flag
Notes
EMI
¾
¾
INTnE
INTnF
n=0~1
CPE
CPF
¾
Interrupt Registers
Comparator
Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the
application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as
shown in the accompanying table. The number of registers depends upon the device chosen but fall into three
categories. The first is the INTC0~INTC2 registers
which setup the primary interrupts, the second is the
MFI0~MFI2 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the
external interrupt trigger edge type.
Multi-function
MFnE
MFnF
n=0~2
A/D Converter
ADE
ADF
HT66F016,
HT66F017 only
Time Base
TBnE
TBnF
n=0~1
LVD
LVE
LVF
¾
EEPROM
DEE
DEF
¾
TnPE
TnPF
TnAE
TnAF
TM
n=0~1
Interrupt Register Bit Naming Conventions
· HT66F016, HT68F016 Interrupt Register Contents
Name
Bit
7
6
5
4
3
2
1
0
INTEG
¾
¾
¾
¾
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
¾
¾
CPF
INT0F
¾
CPE
INT0E
EMI
INTC1
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
INTC2
¾
¾
INT1F
TB1F
¾
¾
INT1E
TB1E
MFI0
¾
¾
¾
¾
¾
¾
¾
¾
MFI1
¾
¾
T1AF
T1PF
¾
¾
T1AE
T1PE
MFI2
¾
¾
DEF
LVF
¾
¾
DEE
LVE
Note: HT68F016 doesn¢t have ADE & ADF bits
· HT66F017, HT68F017 Interrupt Register Contents
Name
Bit
7
6
5
4
3
2
1
0
¾
¾
¾
¾
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
¾
MF0F
CPF
INT0F
MF0E
CPE
INT0E
EMI
INTC1
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
INTC2
¾
¾
INT1F
TB1F
¾
¾
INT1E
TB1E
MF0I
¾
¾
T0AF
T0PF
¾
¾
T0AE
T0PE
MFI1
¾
¾
T1AF
T1PF
¾
¾
T1AE
T1PE
MFI2
¾
¾
DEF
LVF
¾
¾
DEE
LVE
INTEG
Note: HT68F017 doesn¢t have ADE & ADF bits
Rev. 1.00
84
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
INT1S1
INT1S0
INT0S1
INT0S0
R/W
¾
¾
¾
¾
R/W
R/W
R/W
R/W
POR
¾
¾
¾
¾
0
0
0
0
Bit 7~2
Bit 3~2
Bit 1~0
unimplemented, read as ²0²
INT1S1~INT1S0: interrupt edge control for INT1 pin
00: disable
01: rising edge
10: falling edge
01: both rising and falling edges
INT0S1~INT0S0: interrupt edge control for INT0 pin
00: disable
01: rising edge
10: falling edge
01: both rising and falling edges
· INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
MF0F
CPF
INT0F
MF0E
CPE
INT0E
EMI
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
Note: HT66F016 , HT68F016 & HT68F017 don¢t have MF0E, MF0F
Bit 7
unimplemented, read as ²0²
Bit 6
MF0F: Multi-function 0 Interrupt Request Flag
0: no request
1: interrupt request
Bit 5
CPF: Comparator interrupt request flag
0: no request
1: interrupt request
Bit 4
INT0F: INT0 pin interrupt request flag
0: no request
1: interrupt request
Bit 3
MF0E: Multi-function 0 Interrupt Control
0: disable
1: enable
Bit 2
CPE: Comparator interrupt control
0: disable
1: enable
Bit 1
INT0E: INT0 interrupt control
0: disable
1: enable
Bit 0
EMI: Global interrupt control
0: disable
1: enable
Rev. 1.00
85
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HT66F016/HT66F017/HT68F016/HT68F017
· INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
TB0F
ADF
MF2F
MF1F
TB0E
ADE
MF2E
MF1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Note: HT68F016, HT68F017 don¢t have ADE, ADF
Bit 7
TB0F: Time Base 0 Interrupt Request Flag
0: no request
1: interrupt request
Bit 6
ADF: A/D Converter Interrupt Request Flag
0: no request
1: interrupt request
Bit 5
MF2F: Multi-function Interrupt 2 Request Flag
0: no request
1: interrupt request
MF1F: Multi-function Interrupt 1 Request Flag
0: no request
1: interrupt request
TB0E: Time Base 0 Interrupt Control
0: disable
1: enable
ADE: A/D converter interrupt control
0: disable
1: enable
MF2E: Multi-function Interrupt 2 Control
0: disable
1: enable
MF1E: Multi-function Interrupt 1 Control
0: disable
1: enable
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
· INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
INT1F
TB1F
¾
¾
INT1E
TB1E
R/W
¾
¾
R/W
R/W
¾
¾
R/W
R/W
POR
¾
¾
0
0
¾
¾
0
0
Bit 7~6
unimplemented, read as ²0²
Bit 5
INT1F: INT1 pin interrupt request flag
0: no request
1: interrupt request
Bit 4
TB1F: Time Base 1 Interrupt Request Flag
0: no request
1: interrupt request
Bit 3~2
unimplemented, read as ²0²
Bit 1
INT1E: INT1 pin interrupt control
0: disable
1: enable
Bit 0
TB1E: Time Base 1 Interrupt Control
0: disable
1: enable
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· MFI0 Register -- HT66F017
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
T0AF
T0PF
¾
¾
T0AE
T0PE
R/W
¾
¾
R/W
R/W
¾
¾
R/W
R/W
POR
¾
¾
0
0
¾
¾
0
0
Bit 7~6
unimplemented, read as ²0²
Bit 5
T0AF: TM0 Comparator A match interrupt request flag
0: no request
1: interrupt request
Bit 4
T0PF: TM0 Comparator P match interrupt request flag
0: no request
1: interrupt request
Bit 3~2
unimplemented, read as ²0²
Bit 1
T0AE: TM0 Comparator A match interrupt control
0: disable
1: enable
Bit 0
T0PE: TM0 Comparator P match interrupt control
0: disable
1: enable
· MFI1 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
T1AF
T1PF
¾
¾
T1AE
T1PE
R/W
¾
¾
R/W
R/W
¾
¾
R/W
R/W
POR
¾
¾
0
0
¾
¾
0
0
Bit 7~6
Bit 5
Bit 4
Bit 3~2
Bit 1
Bit 0
Rev. 1.00
unimplemented, read as ²0²
T1AF: TM1 Comparator A match interrupt request flag
0: no request
1: interrupt request
T1PF: TM1 Comparator P match interrupt request flag
0: no request
1: interrupt request
unimplemented, read as ²0²
T1AE: TM1 Comparator A match interrupt control
0: disable
1: enable
T1PE: TM1 Comparator P match interrupt control
0: disable
1: enable
87
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· MFI2 Register
Bit
7
6
5
4
3
Name
¾
¾
DEF
LVF
¾
2
1
0
DEE
LVE
R/W
¾
¾
R/W
R/W
¾
¾
R/W
R/W
POR
¾
¾
0
0
¾
¾
0
0
Bit 7~6
Bit 5
unimplemented, read as ²0²
DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
Bit 4
LVF: LVD interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Bit 1
unimplemented, read as ²0²
DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
Bit 0
LVE: LVD Interrupt Control
0: Disable
1: Enable
Interrupt Operation
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagrams with their order of priority. Some interrupt
sources have their own individual vector while others
share the same multi-function interrupt vector. Once an
interrupt subroutine is serviced, all the other interrupts
will be blocked, as the global interrupt enable bit, EMI bit
will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other
interrupt requests occur during this interval, although
the interrupt will not be immediately serviced, the request flag will still be recorded.
When the conditions for an interrupt event occur, such
as a TM Comparator P or Comparator A match or A/D
conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually
generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable
bit. If the enable bit is set high then the program will jump
to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump
to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts.
If an interrupt requires immediate servicing while the
program is already in another interrupt service routine,
the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related
interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must
be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the
priority that is applied. All of the interrupt request flags
when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.
When an interrupt is generated, the Program Counter,
which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program
Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector.
The microcontroller will then fetch its next instruction
from this interrupt vector. The instruction at this vector
will usually be a ²JMP² which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a ²RETI², which retrieves the original
Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Legend
xxF
Request Flag, no auto reset in ISR
xxF
Request Flag, auto reset in ISR
xxE
Enable Bits
TM0 P
T0PF
T0PE
TM0 A
T0AF
T0AE
TM1 P
T1PF
T1PE
TM1 A
T1AF
T1AE
LVD
LVF
LVE
EEPROM
DEF
DEE
Interrupts contained within
Multi-Function Interrupts
EMI auto disabled
in ISR
Interrupt
Name
INT0 Pin
Request
Flags
INT0F
Enable
Bits
INT0E
Master
Enable
EMI
Comparator
CPF
CPE
EMI
08H
M. Funct. 0
MF0F
MF0E
EMI
0CH
M. Funct. 1
MF1F
MF1E
EMI
10H
M. Funct. 2
MF2F
MF2E
EMI
14H
A/D
ADF
ADE
EMI
18H
Time Base 0
TB0F
TB0E
EMI
1CH
Time Base 1
TB1F
TB1E
EMI
20H
INT1 Pin
INT1F
INT1E
EMI
24H
Vector
04H
Priority
High
Low
Note: HT68F017 don¢t have ADE, ADF
Interrupt Structure - HT66F017/HT68F017
EMI auto disabled
in ISR
Legend
xxF
Request Flag, no auto reset in ISR
xxF
Request Flag, auto reset in ISR
xxE
Enable Bits
TM1 P
T1PF
T1PE
TM1 A
T1AF
T1AE
LVD
LVF
LVE
EEPROM
DEF
DEE
Interrupts contained within
Multi-Function Interrupts
Interrupt
Name
INT0 Pin
Request
Flags
INT0F
Enable
Bits
INT0E
Master
Enable
EMI
Vector
Comparator
CPF
CPE
EMI
08H
M. Funct. 1
MF1F
MF1E
EMI
10H
M. Funct. 2
MF2F
MF2E
EMI
14H
A/D
ADF
ADE
EMI
18H
Time Base 0
TB0F
TB0E
EMI
1CH
Time Base 1
TB1F
TB1E
EMI
20H
INT1 Pin
INT1F
INT1E
EMI
24H
04H
Priority
High
Low
Note: HT68F016 don¢t have ADE, ADF
Interrupt Structure - HT66F016/HT68F016
Rev. 1.00
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May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
External Interrupt
A Multi-function interrupt request will take place when
any of the Multi-function interrupt request flags, MFnF
are set. The Multi-function interrupt flags will be set
when any of their included functions generate an interrupt request flag. To allow the program to branch to its
respective interrupt vector address, when the
Multi-function interrupt is enabled and the stack is not
full, and either one of the interrupts contained within
each of Multi-function interrupt occurs, a subroutine call
to one of the Multi-function interrupt vectors will take
place. When the interrupt is serviced, the related
Multi-Function request flag, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
The external interrupts are controlled by signal transitions on the INT0~INT1 pins. An external interrupt request will take place when the external interrupt request
flags, INT0F~INT1F, are set, which will occur when a
transition, whose type is chosen by the edge select bits,
appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and
respective external interrupt enable bit, INT0E~INT1E,
must first be set. Additionally the correct interrupt edge
type must be selected using the INTEG register to enable the external interrupt function and to choose the
trigger edge type. As the external interrupt pins are
pin-shared with I/O pins, they can only be configured as
external interrupt pins if their external interrupt enable
bit in the corresponding interrupt register has been set.
The pin must also be setup as an input by setting the
corresponding bit in the port control register. When the
interrupt is enabled, the stack is not full and the correct
transition type appears on the external interrupt pin, a
subroutine call to the external interrupt vector, will take
place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid
even if the pin is used as an external interrupt input.
However, it must be noted that, although the
Multi-function Interrupt flags will be automatically reset
when the interrupt is serviced, the request flags from the
original source of the Multi-function interrupts, namely
the TM Interrupts, LVD interrupt and EEPROM interrupt,
will not be automatically reset and must be manually reset by the application program.
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter
Interrupt request flag, ADF, is set, which occurs when
the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D
Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D
Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag,
ADF, will be automatically cleared. The EMI bit will also
be automatically cleared to disable other interrupts.
The INTEG register is used to select the type of active
edge that will trigger the external interrupt. A choice of
either rising or falling or both edge types can be chosen
to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt
function.
Comparator Interrupt
The comparator interrupt is controlled by the internal
comparator. A comparator interrupt request will take
place when the comparator interrupt request flag, CPF,
is set, a situation that will occur when the comparator
output changes state. To allow the program to branch to
its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable
bit, CPE, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs
generate a comparator output transition, a subroutine
call to the comparator interrupt vector, will take place.
When the interrupt is serviced, the comparator interrupt
request flag, will be automatically reset and the EMI bit
will be automatically cleared to disable other interrupts.
Time Base Interrupts
The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They
are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To
allow the program to branch to their respective interrupt
vector addresses, the global interrupt enable bit, EMI and
Time Base enable bits, TB0E or TB1E, must first be set.
When the interrupt is enabled, the stack is not full and the
Time Base overflows, a subroutine call to their respective
vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or
TB1F, will be automatically reset and the EMI bit will be
cleared to disable other interrupts.
Multi-function Interrupt
Within these devices there are up to three Multi-function
interrupts. Unlike the other independent interrupts,
these interrupts have no independent source, but rather
are formed from other existing interrupt sources, namely
the TM Interrupts, LVD interrupt and EEPROM interrupt.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges.
The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several
different sources, as shown in the System Operating Mode section.
· TBC Register
Bit
7
6
5
4
3
2
1
0
Name
TBON
TBCK
TB11
TB10
¾
TB02
TB01
TB00
R/W
R/W
R/W
R/W
R/W
¾
R/W
R/W
R/W
POR
0
0
1
1
¾
1
1
1
Bit 7
TBON: Time Base control
0: disable
1: enable
Bit 6
TBCK: Time Base clock fTB selection
0: fTBC
1: fSYS/4
Bit 5~4
TB11~TB10: select Time Base 1 Time-out period
00: 4096/fTB
01: 8192/fTB
10: 16384/fTB
11: 32768/fTB
Bit 3
Unimplemented, read as 0
Bit 2~0
TB02~TB00: select Time Base 0 Time-out period
000: 256/fTB
001: 512/fTB
010: 1024/fTB
011: 2048/fTB
100: 4096/fTB
101: 8192/fTB
110: 16384/fTB
111: 32768/fTB
T B 0 2 ~ T B 0 0
fS
fT
B C
Y S
= fL
/4
M
IR C
X
fT
U
T B C K B it
¸
2
8
~ 2
1 5
T im e B a s e 0 In te r r u p t
1 2
~ 2
1 5
T im e B a s e 1 In te r r u p t
B
¸
2
T B 1 1 ~ T B 1 0
Time Base Interrupt
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
EEPROM Interrupt
To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant
Multi-function Interrupt enable bit, MFnE, must first be
set. When the interrupt is enabled, the stack is not full
and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is
serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF
flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have
to be cleared by the application program.
The EEPROM Interrupt, is contained within the
Multi-function Interrupt. An EEPROM Interrupt request
will take place when the EEPROM Interrupt request
flag, DEF, is set, which occurs when an EEPROM Write
cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be
set. When the interrupt is enabled, the stack is not full
and an EEPROM Write cycle ends, a subroutine call to
the respective Multi-function Interrupt vector, will take
place. When the EEPROM Interrupt is serviced, the EMI
bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request
flag will be also automatically cleared. As the DEF flag
will not be automatically cleared, it has to be cleared by
the application program.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE
Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent
of whether the interrupt is enabled or not. Therefore,
even though the device is in the SLEEP or IDLE Mode
and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a
low power supply voltage or comparator input change
may cause their respective interrupt flag to be set high
and consequently generate an interrupt. Care must
therefore be taken if spurious wake-up situations are to
be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag
should be set high before the device enters the SLEEP
or IDLE Mode. The interrupt enable bits have no effect
on the interrupt wake-up function.
LVD Interrupt
The Low Voltage Detector Interrupt is contained within
the Multi-function Interrupt. An LVD Interrupt request will
take place when the LVD Interrupt request flag, LVF, is
set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the
program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage
Interrupt enable bit, LVE, and associated Multi-function
interrupt enable bit, must first be set. When the interrupt
is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage
Interrupt is serviced, the EMI bit will be automatically
cleared to disable other interrupts, however only the
Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically
cleared, it has to be cleared by the application program.
TM Interrupts
The Compact and Standard Type TMs have two interrupts each. All of the TM interrupts are contained within
the Multi-function Interrupts. For each of the Compact
and Standard Type TMs there are two interrupt request
flags TnPF and TnAF and two enable bits TnPE and
TnAE. A TM interrupt request will take place when any
of the TM request flags are set, a situation which occurs
when a TM comparator P or A match situation happens.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the
corresponding interrupt is serviced or until the request
flag is cleared by the application program.
Every interrupt has the capability of waking up the
microcontroller when it is in SLEEP or IDLE Mode, the
wake up being generated when the interrupt request
flag changes from low to high. If it is required to prevent
a certain interrupt from waking up the microcontroller
then its respective request flag should be first set high
before enter SLEEP or IDLE Mode.
Where a certain interrupt is contained within a
Multi-function interrupt, then when the interrupt service
routine is executed, as only the Multi-function interrupt
request flags, MFnF, will be automatically cleared, the
individual request flag for the function needs to be
cleared by the application program.
As only the Program Counter is pushed onto the stack,
then when the interrupt is serviced, if the contents of the
accumulator, status register or other registers are altered by the interrupt service program, their contents
should be saved to the memory at the beginning of the
interrupt service routine.
It is recommended that programs do not use the ²CALL²
instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately. If only one stack is left and the
interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine.
To return from an interrupt subroutine, either a RET or
RETI instruction may be executed. The RETI instruction
in addition to executing a return to the main program
also automatically sets the EMI bit high to allow further
interrupts. The RET instruction however only executes a
return to the main program leaving the EMI bit in its
present zero state and therefore disabling the execution
of further interrupts.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Low Voltage Detector - LVD
Each device has a Low Voltage Detector function, also
known as LVD. This enabled the device to monitor the
power supply voltage, VDD, and provide a warning signal
should it fall below a certain level. This function may be
especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as
it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability
of generating an interrupt signal.
fixed voltages below which a low voltage condition will
be detemined. A low voltage condition is indicated when
the LVDO bit is set. If the LVDO bit is low, this indicates
that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall
on/off function of the low voltage detector. Setting the bit
high will enable the low voltage detector. Clearing the bit
to zero will switch off the internal low voltage detector
circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off
the circuit when not in use, an important consideration in
power sensitive battery powered applications.
LVD Register
The Low Voltage Detector function is controlled using a
single register with the name LVDC. Three bits in this
register, VLVD2~VLVD0, are used to select one of eight
· LVDC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
LVDO
LVDEN
¾
VLVD2
VLVD1
VLVD0
R/W
¾
¾
R
R/W
¾
R/W
R/W
R/W
POR
¾
¾
0
0
¾
0
0
0
Bit 7~6
unimplemented, read as ²0²
Bit 5
LVDO: LVD output flag
0: no low voltage detect
1: low voltage detect
Bit
LVDEN: low voltage detector control
0: disable
1: enable
Bit 3
unimplemented, read as ²0²
Bit 2~0
VLVD2 ~ VLVD0: select LVD voltage
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.2V
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
LVD Operation
The Low Voltage Detector also has its own interrupt
which is contained within one of the Multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt
will only be generated after a delay of tLVD after the LVDO
bit has been set high by a low voltage condition. When
the device is powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case,
the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD
voltage. This will cause the device to wake-up from the
SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag
should be first set high before the device enters the
SLEEP or IDLE Mode.
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified
voltage level stored in the LVDC register. This has a
range of between 2.0V and 4.2V. When the power supply voltage, VDD, falls below this pre-determined value,
the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be
automatically enabled. When the device is powered
down the low voltage detector will remain active if the
LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also
that as the VDD voltage may rise and fall rather slowly, at
the voltage nears that of VLVD, there may be multiple bit
LVDO transitions.
V D D
V
L V D
L V D E N
L V D O
tL
V D S
LVD Operation
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later using the application program. All options must be defined for proper system function, the
details of which are shown in the table.
No.
Options
Oscillator Options
1
High Speed System Oscillator Selection - fOSC: HIRC or HXT
Watchdog Options
2
WDT function: Always enable or "By S/W control
Application Circuits
A N 0 ~ A N 3
O S C
C ir c u it
P A 0 ~ P A 4
P A 6 /O S C 1
P A 5 /O S C 2
P B 0 ~ P B 5
S e e O s c illa to r
S e c tio n
Note:
²*² Recommended component for added ESD protection.
²**² Recommended component in environments where power line noise is significant.
Rev. 1.00
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HT66F016/HT66F017/HT68F016/HT68F017
Instruction Set
Introduction
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontroller, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller a p p l i c at i o n s . W i t h i n t h e H o l t e k
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRD [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
107
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HT66F016/HT66F017/HT68F016/HT68F017
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRD [m]
Read table to TBLH and Data Memory
Description
The program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
108
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
109
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for
the latest version of the package information.
16-pin DIP (300mil) Outline Dimensions
A
B
A
1 6
9
1
8
B
1 6
9
1
8
H
H
C
C
D
D
G
E
G
E
I
F
I
F
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
· MS-001d (see fig1)
Symbol
A
Min.
Nom.
Max.
0.780
¾
0.880
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.070
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
19.81
¾
22.35
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
110
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
· MS-001d (see fig2)
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.735
¾
0.775
B
0.240
¾
0.280
C
0.115
¾
0.195
D
0.115
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.070
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
A
Dimensions in mm
Min.
Nom.
Max.
18.67
¾
19.69
B
6.10
¾
7.11
C
2.92
¾
4.95
D
2.92
¾
3.81
E
0.36
¾
0.56
F
1.14
¾
1.78
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
· MO-095a (see fig2)
Symbol
Nom.
Max.
A
0.745
¾
0.785
B
0.275
¾
0.295
C
0.120
¾
0.150
D
0.110
¾
0.150
E
0.014
¾
0.022
F
0.045
¾
0.060
G
¾
0.100
¾
H
0.300
¾
0.325
I
¾
0.430
¾
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
18.92
¾
19.94
B
6.99
¾
7.49
C
3.05
¾
3.81
D
2.79
¾
3.81
E
0.36
¾
0.56
1.52
F
1.14
¾
G
¾
2.54
¾
H
7.62
¾
8.26
I
¾
10.92
¾
111
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
16-pin NSOP (150mil) Outline Dimensions
A
1 6
9
1
B
8
C
C '
G
H
D
E
a
F
· MS-012
Symbol
A
Min.
Nom.
Max.
0.228
¾
0.244
B
0.150
¾
0.157
C
0.012
¾
0.020
C¢
0.386
¾
0.402
D
¾
¾
0.069
E
¾
0.050
¾
F
0.004
¾
0.010
G
0.016
¾
0.050
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
3.99
C
0.30
¾
0.51
C¢
9.80
¾
10.21
D
¾
¾
1.75
E
¾
1.27
¾
F
0.10
¾
0.25
G
0.41
¾
1.27
H
0.18
¾
0.25
a
0°
¾
8°
112
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
16-pin SSOP (150mil) Outline Dimensions
9
1 6
A
B
1
8
C
C '
G
H
D
E
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.189
¾
0.197
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.00
a
F
Dimensions in mm
Min.
Nom.
Max.
A
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
4.80
¾
5.00
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
113
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
16-pin SSOP (150mil)
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.00
Dimensions in mm
330.0±1.0
100.0±1.5
13.0
+0.5/-0.2
2.0±0.5
12.8
+0.3/-0.2
18.2±0.2
114
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 16N (150mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
16.0±0.3
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
7.5±0.1
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
16-pin SSOP (150mil)
Symbol
Description
Dimensions in mm
12.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.4±0.1
B0
Cavity Width
5.2±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.00
8.0±0.1
1.75±0.10
5.5±0.1
1.55±0.10
1.50
+0.25/-0.00
0.30±0.05
9.3±0.1
115
May 14, 2012
HT66F016/HT66F017/HT68F016/HT68F017
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
116
May 14, 2012