HY5DV651622 4 Banks x 1M x 16Bit DOUBLE DATA RATE SDRAM DESCRIPTION The Hyundai HY5DV651622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point to point applications which require high bandwidth. HY5DV651622 is organized as 4 banks of 1,048,576x16. HY5DV651622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK ), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. Mode Register Set options include the length of pipeline ( CAS latency of 2 / 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 2 / 4 / 8), and the burst count sequence(sequential or interleave). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. FEATURES • 3.3V for VDD and 2.5V for V DDQ power supplies • Data inputs on LDQS/UDQS centers when write (centered DQ) • All inputs and outputs are compatible with SSTL_2 interface • Data strobes synchronized with output data for read and input data for write JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch • Delay Locked Loop(DLL) installed with DLL reset mode • Write mask byte controls by LDM and UDM • Programmable CAS Latency 2.0 / 3.0 • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Internal 4 bank operations with single pulsed RAS • Auto refresh and self refresh supported • 4096 refresh cycles / 64ms • • Fully differential clock operations(CLK & CLK) • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • • Data(DQ), Data strobes(LDQS/UDQS) and Write masks(LDM/UDM) latched on both rising and falling edges of the clock Data outputs on LDQS/UDQS edges when read (edged DQ) ORDERING INFORMATION Part No. Power Supply HY5DV651622T-G55 HY5DV651622T-G6 HY5DV651622T-G7 Clock Frequency Organization Interface Package 4Banks x 1Mbit x 16 SSTL_2 400mil 66pin TSOP II 183MHz VDD=3.3V VDDQ=2.5V 166MHz 143MHz This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9/Jan.00 HY5DV651622 PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 TOP VIEW 2 3 4 5 6 7 8 9 10 11 12 13 14 15 400mil X 875mil 16 66 Pin TSOP-II 17 0.65mm Pin Pitch 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN PIN NAME DESCRIPTION CLK, CLK Differential Clock Input The system clock input. All of the inputs are latched on the rising edges of the clock except DQi, LDQS/UDQS and LDM/UDM that are sampled on the both. CKE Clock Enable Controls internal clock signal. When deactivated, the DDR SDRAM will be one of the states among power down or self refresh. CS Chip Select Enables or disables all inputs except CLK/ CLK, CKE, LDQS/UDQS and LDM/UDM. BA0, BA1 Bank Select Address Selects bank to be activated during either RAS or CAS activity. Selects bank to be read/written during either RAS or CAS activity. A0 ~ A11 Address Row Address : A0 ~ A11, Column Address : A0 ~ A7 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the command being issued. Refer function truth table for details. LDM, UDM Write Mask Masks input data in write mode. LDQS, UDQS Data Input/Output Strobe Active on the both edges for Data Input and Output. DQ0 ~ DQ15 Data Input/Output Bidirectional data input / output pin. VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers for Noise immunity. VREF Reference Voltage Reference voltage for inputs for SSTL interface. NC No Connection No connection. Rev. 0.9/ Jan.00 2 HY5DV651622 FUNCTIONAL BLOCK DIAGRAM 4banks x 1Mbit x 16 I/O Double data rate Synchronous DRAM Input Buffer 16 Write Data Register 2-bit Prefetch Unit 32 1Mx16/Bank0 1Mx16/Bank2 32 1Mx16/Bank3 Mode Register 16 Output Buffer 1Mx16/Bank1 Command Decoder 2-bit Prefetch Unit Bank Control Sense AMP CLK /CLK CKE /CS /RAS /CAS /WE DM LDQS, UDQS DQ[0:15] Row Decoder Column Decoder LDQS, UDQS ADD Address Buffer Column Address Counter CLK_DLL LDQS, UDQS CLK, /CLK Data Strobe Transmitter Data Strobe Receiver DLL Block Mode Register Rev. 0.9/ Jan.00 3 HY5DV651622 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 ×C Storage Temperature TSTG -55 ~ 125 ×C VIN, VOUT -0.5 ~ 3.6 V VDD -1.0 ~ 4.6 V VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 1 W TSOLDER 260 Þ 10 ×C Þ Sec Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to V SS Soldering Temperature Þ Time Note : Operation at above absolute maximum rating can adversely affect device reliability. DC OPERATING CONDITIONS (TA=0 to 70×C, Voltage referenced to VSS = 0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage VDD 3.15 3.3 3.6 V Power Supply Voltage VDDQ 2.3 2.5 2.7 V Input High Voltage VIH VREF + 0.18 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.18 V Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V VREF 1.15 1.25 1.35 V Reference Voltage Note 1 2 3 Note : 1. VDDQ must not exceed the level of V DD. 2. VIL (min) is acceptable -1.5V AC pulse width with £5ns of duration. 3. The value of VREF is approximately equal to 0.5V DDQ. AC OPERATING TEST CONDITIONS (TA=0 to 70×C, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.35 V AC Input Low Level Voltage (V IL, max) VREF - 0.35 V VREF V VTT V Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Rev. 0.9/ Jan.00 4 HY5DV651622 AC OPERATING TEST CONDITIONS (TA=0 to 70×C, Voltage referenced to VSS = 0V) Parameter - continued Value Unit 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT) 50 W Series Resistor (RS) 25 W Output Load Capacitance for Access Time Measurement (C L) 30 pF Input Signal maximum peak swing - CAPACITANCE (TA=25×C, f=1MHz) Parameter Pin Input Capacitance A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS, CAS, WE Clock Capacitance CLK, CLK Data Input / Output Capacitance DQ0 ~ DQ15, LDQS, UDQS, LDM, UDM Symbol Min Max Unit C IN 2.5 3.5 pF CCLK 2.5 3.5 pF CIO 4.0 5.5 pF OUTPUT LOAD CIRCUIT VTT VTT RT=50Ω RT=50Ω Output RS=25Ω Zo=50Ω VREF CL=30pF Rev. 0.9/ Jan.00 5 HY5DV651622 DC CHARACTERISTICS I (TA=0 to 70×C, Voltage referenced to VSS = 0V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -5 5 mA 1 Output Leakage Current ILO -5 5 mA 2 Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA Output Low Voltage VOL - VTT - 0.76 V IOL = +15.2mA Note : 1.VIN = 0 to 3.6V, All other pins are not tested under V IN =0V 2.DOUT is disabled, VOUT=0 to 2.7V DC CHARACTERISTICS II (TA=0 to 70×C, Voltage referenced to VSS = 0V) Speed Parameter Symbol Test Condition G55 G6 G7 160 150 140 Unit Note mA 1 Operating Current IDD1 Burst length=2, One bank active tRC Š tRC(min), I OL=0mA Precharge Standby Current in Power Down Mode IDD2P CKE £ VIL(max), tCK = min 20 mA Precharge Standby Current in Non Power Down Mode IDD2N CKE Š VIH(min), CS Š VIH(min), tCK = min Input signals are changed one time during 2clks 40 mA Active Standby Current in Power Down Mode IDD3P CKE £ VIL(max), tCK = min 25 mA Active Standby Current in Non Power Down Mode IDD3N CKE Š VIH(min), CS Š VIH(min), tCK = min Input signals are changed one time during 2clks 50 mA tCK Š tCK(min), IOL=0mA All banks active Burst Mode Operating Current IDD4 Auto Refresh Current IDD5 tRC Š tRFC(min), All banks active Self Refresh Current IDD6 CKE £ 0.2V CL=3.0 280 260 240 CL=2.0 220 210 200 210 200 190 2 mA 1 mA 1,2 mA Note : 1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of t RFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS. Rev. 0.9/ Jan.00 6 HY5DV651622 AC CHARACTERISTICS -G55 Parameter -G6 -G7 Symbol Unit Min Row Cycle Time Auto Refresh Row Cycle Time Max Min Max Min tRC 55 - 60 - 62 - ns tRFC 66 - 72 - 77 - ns Row Active Time tRAS 38.5 120K 42 120K 42 120K ns Row Address to Column Address Delay tRCD 16.5 - 18 - 20 - ns Row Prechage Time tRP 16.5 - 18 - 20 - ns Row Active to Row Active Delay tRRD 2 - 2 - 2 - CLK Column Address to Column Address Delay tCCD 1 - 1 - 1 - CLK Write Recovery Time tWR 2 - 2 - 2 - CLK Last Data-In to Read Command delay tDRL 1 - 1 - 1 - CLK Auto Precharge Write Recovery + Precharge Time tDAL 27.5 - 30 - 34 - ns 5.5 12 6 15 7 15 ns - - - - - - ns CL = 3.0 System Clock Cycle Time Note Max tCK CL = 2.0 Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CLK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CLK DQS-Out edge to Clock edge skew tDQSCK -0.4 0.1 -0.4 0.1 -0.4 0.1 CLK Data-Out edge to Clock edge skew tAC -0.4 0.1 -0.4 0.1 -0.4 0.1 CLK tDQSQ -0.4 0.4 -0.4 0.4 -0.5 0.5 ns tDV 0.35 - 0.35 - 0.35 - CLK DQS-Out Preamble Time tRPRE 0.8 1.1 0.8 1.1 0.8 1.1 CLK DQS-Out Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK DQS-Out edge to Data-Out edge skew Data/DQS-Out Valid Window CLK to first rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CLK DQS-In Preamble Setup Time tWPRES 0 - 0 - 0 - CLK DQS-In Preamble Hold Time tWPREH 0.25 - 0.25 - 0.25 - CLK tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK DQS-In High Level Width tDSH 0.4 0.6 0.4 0.6 0.4 0.6 CLK DQS-In Low Level Width tDSL 0.4 0.6 0.4 0.6 0.4 0.6 CLK Input Setup Time to CLK (ADDR & Control) tIS 1.1 - 1.1 - 1.1 - ns 1 Input Hold Time to CLK (ADDR & Control) tIH 1.1 - 1.1 - 1.1 - ns 1 Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 - 0.5 - 0.5 - ns 2 Data-In Hold Time to DQS-In (DQ & DM) tDH 0.5 - 0.5 - 0.5 - ns 2 DQS-In Pulse Width tDIPW 1.6 - 1.6 - 1.7 - ns Mode register Set Cycle Time tMRD 2 - 2 - 2 - CLK DQS-In Last falling edge to Hi-Z Delay Power Down Exit Time tPDEX 10 - 10 - 10 - ns Exit Self Refresh to Non-Read Command tXSNR 66 - 72 - 75 - ns Exit Self Refresh to Read command tXSRD 200 - 200 - 200 - CLK Average Periodic Refresh Interval tREFI - 15.6 - 15.6 - 15.6 us 3 Note : 1. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. 2. Data letched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 3. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Rev. 0.9/ Jan.00 7 HY5DV651622 SIMPLIFIED COMMAND TRUTH TABLE A10/ AP Command CKEn-1 CKEn CS RAS CAS WE Extended Mode Register Set H X L L L L OP code 1,2 Mode Register Set H X L L L L OP code 1,2 H X X X H X X 1 L H H H Device Deselect No Operation Bank Active H X L L H H H X L H L H ADDR RA Read BA V L CA Read with Autoprecharge 1 1,3,6 L H X L H L L CA Write with Autoprecharge 1 V H Precharge All Banks H X L L H L Precharge selected Bank 1 V H Write Note 1,4,6 H X 1,5 L V 1 X Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Entry H L L L L H H X X X Exit L H L H H H H X X X L H H H Self Refresh Entry H X 1 1 L Precharge Power Down Mode 1 X Exit Active Power Down Mode (Clock Suspend) 1 Entry Exit L H L H X X X 1 L H H H 1 H X X X 1 L V V V H L H X X 1 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are “Don’t Care”. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA 0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CLK(n), then there will be no command presented to activated bank until CLK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory compoment in CLK(n), then there will be no command presented to activated bank until CLK(n+BL/2+1+t DPL+tRP). Last Data-In to Prechage delay(t DPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is “High” when Row Precharge command being issued, BA 0/BA1 are ignored and all banks are selected to be precharged. 6. The speed grade with G code will not be guaranteed the Read and Write with Autoprecharge function. Rev. 0.9/ Jan.00 8 HY5DV651622 WRITE MASK TRUTH TABLE Function A10/ AP CKEn-1 CKEn CS, RAS, CAS, WE LDM UDM Data Write H X X L L X 1,2 Data-In Mask H X X H H X 1,2 Lower Byte Write / Upper Byte-In Mask H X X L H X 1,2 Upper Byte Write / Lower Byte-In Mask H X X H L X 1,2 ADDR BA Note ( H=Logic High Level, L=Logic Low Level, X=Don’t Care ) Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. PACKAGE INFORMATION 400mil 66pin Thin Small Outline Package Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396) BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.65 (0.0256) BSC 1.194 (0.0470) 0.991 (0.0390) Rev. 0.9/ Jan.00 0.35 (0.0138) 0.25 (0.0098) 0 ~ 5 Deg. SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 9