HY628400 Series 512Kx8bit CMOS SRAM DESCRIPTION FEATURES The HY628400 is a high-speed, low power and 4M bits CMOS SRAM organized as 524,288 words by 8 bits. The HY628400 uses Hyundai's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particulary well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0V. • • • • Product Voltage Speed Operation No. (V) (ns) Current(mA) HY628400 5.0 55/70/85 10 Note 1. Normal : Normal Temperature 2. Current value are max. Standby Current(uA) L LL 100 30 Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) - 2.0V(min) data retention • Standard pin configuration - 32pin 525mil SOP - 32pin 400mil TSOP-II (Standard and Reversed) Temperature (°C) 0~70(Normal) PIN CONNECTION TSOP-II(Standard) PIN DESCRIPTION Pin Name /CS /WE /OE A0 ~ A18 I/O1 ~ I/O8 Vcc Vss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin Function Chip Select Write Enable Output Enable Address Input Data Input/Output Power(5.0V) Ground Vcc A15 A17 /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 Vcc A15 A17 /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss TSOP-II(Reversed) BLOCK DIAGRAM ROW DECODER A0 A18 /CS /OE /WE MEMORY ARRAY 1024x4096 I/O1 OUTPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SENSE AMP SOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss WRITE DRIVER Vcc A15 A17 /WE A13 A8 A9 A11 /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 COLUMN DECODER 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ADD INPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O8 CONTROL LOGIC A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 /Jan.99 Hyundai Semiconductor HY628400 Series ORDERING INFORMATION Part No. HY628400LG HY628400LLG HY628400LT2 HY628400LLT2 HY628400LR2 HY628400LLR2 Speed 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 55/70/85 Power L-part LL-part L-part LL-part L-part LL-part Temp Package SOP SOP TSOP-II(Standard) TSOP-II(Standard) TSOP-II(Reversed) TSOP-II(Reversed) ABSOLUTE MAXIMUM RATING (1) Symbol Vcc, VIN, VOUT TA TSTG PD TSOLDER Parameter Power Supply, Input/Output Voltage Operating Temperature Storage Temperature Power Dissipation Lead Soldering Temperature & Time Rating -0.5 to 7.0 0 to 70 -65 to 125 1.0 260 • 10 Unit V °C °C W °C•sec Remark HY628400 Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliablity. RECOMMENDED DC OPERATING CONDITION TA=0°C to 70°C (Normal) Symbol Parameter Vcc Supply Voltage Vss Ground VIH Input High Voltage VIL Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 - Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V Note : 1. VIL = -3.0V for pulse width less than 30ns TRUTH TABLE /CS1 H L L L /WE X H H L /OE X H L X MODE Standby Output Disabled Read Write I/O OPERATION High-Z High-Z Data Out Data In Note : 1. H=VIH, L=VIL, X=don't care Rev.04/Jan99 2 HY628400 Series DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V ±10%, TA = 0°C to 70°C (Normal) unless otherwise specified Symbol Parameter Test Condition ILI ILO Input Leakage Current Output Leakage Current Icc Operating Power Supply Current Average Operating Current ICC1 ISB ISB1 VOL VOH TTL Standby Current (TTL Input) Standby Current HY628400 (CMOS Input) Output Low Voltage Output High Voltage Vss < VIN < Vcc Vss < VOUT < Vcc, /CS = VIH or or /OE = VIH or /WE = VIL /CS = VIL, VIN = VIH or VIL, II/O = 0mA /CS = VIL Min Duty Cycle = 100%, II/O = 0mA /CS = VIH /CS > Vcc - 0.2V IOL = 2.1mA IOH = -1mA L LL Min . -1 -1 Typ . - Max . 1 1 Unit - 5 10 mA - 50 80 mA - 0.4 2 mA 2.4 - 100 30 0.4 - uA uA V V uA uA Note : Typical values are at Vcc = 5.0V, TA = 25°C ERISTICS Vcc = 5.0V ± 10%, TA = 0°C to 70°C (Normal) unless otherwise specified -55 -70 # Symbol Parameter Min. Max. Min. Max. READ CYCLE 1 Trc Read Cycle Time 55 70 2 TAA Address Access Time 55 70 3 TACS Chip Select Access Time 55 70 4 TOE Output Enable to Output Valid 25 35 5 TCLZ Chip Select to Output in Low Z 10 10 6 TOLZ Output Enable to Output in Low Z 5 5 7 TCHZ Chip Deselection to Output in High Z 0 20 0 25 8 TOHZ Out Disable to Output in High Z 0 20 0 25 9 tOH Output Hold from Address Change 10 10 WRITE CYCLE 10 tWC Write Cycle Time 55 70 11 tCW Chip Selection to End of Write 45 60 12 tAW Address Valid to End of Write 45 60 13 tAS Address Set-up Time 0 0 14 tWP Write Pulse Width 40 50 15 tWR Write Recovery Time 0 0 16 tWHZ Write to Output in High Z 0 20 0 25 17 tDW Data to Write Time Overlap 25 30 18 tDH Data Hold from Write Time 0 0 19 tOW Output Active from End of Write 5 5 - Rev.04/Jan99 -85 Min Max. Unit 85 10 5 0 0 10 85 85 45 30 30 - ns ns ns ns ns ns ns ns ns 85 70 70 0 55 0 0 35 0 5 30 - ns ns ns ns ns ns ns ns ns ns 3 HY628400 Series AC TEST CONDITIONS TA = 0°C to 70°C (Normal) unless otherwise specified PARAMETER Value Input Pulse Level 0.8V to 2.4V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load CL = 100pF + 1TTL Load AC TEST LOADS TTL CL(1) Note : Including jig and scope capacitance CAPACITANCE Temp = 25°C, f= 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Condition VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Note : This parameter is sampled and not 100% tested Rev.04/Jan99 4 HY628400 Series TIMING DIAGRAM READ CYCLE 1 tRC ADDR tAA OE tOE tOH tOLZ CS tACS tOHZ tCHZ tCLZ Data Out High-Z Data Valid Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device and from device to device. 3. /WE is high for the read cycle. READ CYCLE 2 tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid Note(READ CYCLE): 1. /WE is high for the read cycle. 2. Device is continuously selected /CS = VIL 3. /OE =VIL. Rev.04/Jan99 5 HY628400 Series WRITE CYCLE 1(/OE Clocked) tWC ADDR OE tAW tCW CS tAS tWR tWP WE tDW Data In tDH Data Valid tOHZ Data Out WRITE CYCLE 2 (/OE Low Fixed) tWC ADDR tAW tCW tWR CS tAS tWP WE tDW Data In tDH Data Valid tWHZ tOW (7) (8) Data Out Notes(WRITE CYCLE): 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low /WE going low: A write end at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. . 2. tCW is measured from the later of /CS going low to the end of write . 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. 5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If /CS goes low simultaneously with /WE going low, the outputs remain in high impedance state. 7. Dout is the read data of the new address. 8. When /CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the outputs should not be applied. Rev.04/Jan99 6 HY628400 Series DATA RETENTION ELECTRIC CHARATERISTIC TA=0°C to 70°C (Normal) Symbol Parameter VDR Vcc for Data Retention ICCDR Data Retention Current HY628400 tCDR tR Chip Deselect to Data Retention Time Operating Recovery Time Test Condition /CS > Vcc - 0.2V Vss<VIN<Vcc Vcc = 3.0V, L /CS >Vcc - 0.2V LL Vss<VIN <Vcc Min 2.0 Typ - Max - Unit V - - 50 15 uA uA 0 tRC(2) - - ns ns Notes: 1. Typical values are at the comdition of TA = 25°C. 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 4.5V tR tCDR 2.2V VDR CS>VCC-0.2V CS VSS RELIABILITY SPEC. TEST MODE ESD HBM MM LATCH - UP Rev.04/Jan99 TEST SPEC. > 2000V > 250V < -100mA > 100mA 7 HY628400 Series PACKAGE INFORMATION 32pin 400mil Thin Small Outline Package Standard(T2) 0.404(10.2620) 0.396(10.0580() UNIT : INCH(mm) MAX. MIN. 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) GAGE PLANE BASE PLANE 0-5 0.0235(0.5970) 0.050BSC (1.2700) 0.017(0.4500) 0.012(0.3050) 0.047(1.1940) SEATING PLANE 0.0160(0.4060) 0.0059(0.1500) 0.0083(0.2100) 0.0020(0.0500) 0.0047(0.1200) 0.039(0.9910) 32pin 400mil Thin Small Outline Package Reversed(R2) 0.404(10.2620) 0.396(10.0580) UNIT : INCH(mm) MAX. MIN. 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) GAGE PLANE BASE PLANE 0-5 0.0235(0.5970) 0.050 BSC (1.2700) 0.047(1.1940) 0.039(0.9910) Rev.04/Jan99 0.017(0.4500) 0.012(0.3050) SEATING PLANE 0.0059(0.1500) 0.0020(0.0500) 0.0160(0.4060) 0.0083(0.2100) 0.0047(0.1200) 8 HY628400 Series 32pin 525mil Small Outline Package(G) UNIT : INCH(mm) 0.810(20.574) 0.804(20.422) 0.444(11.278) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.102) 0.050(1.27)BSC Rev.04/Jan99 0.0125(0.318) 0.0061(0.155) 0.020(0.508) 0 deg 0.0425(1.080) 0.014(0.356) 8 deg 0.0235(0.597) 9