HY57V161610D 2 Banks x 512K x 16 Bit Synchronous DRAM D E S C R IP T IO N THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.) FEATURES • Single 3.0V to 3.6V power supply • • Note1) • Auto refresh and self refresh All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms JEDEC standard 400mil 50pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type of pin pitch - 1, 2, 4, 8 and Full Page for Sequence Burst • All inputs and outputs referenced to positive edge of - 1, 2, 4 and 8 for Interleave Burst system clock • Data mask function by UDQM/LDQM • Internal two banks operation • Programmable C A S Latency ; 1, 2, 3 Clocks O R D E R IN G IN F O R M A T IO N Part No. C lo c k F r e q u e n c y HY57V161610DTC-5 200MHz HY57V161610DTC-55 183MHz HY57V161610DTC-6 166MHz HY57V161610DTC-7 143MHz HY57V161610DTC-8 125MHz HY57V161610DTC-10 100MHz O rganization Interface 2Banks x 512Kbits x 16 LVTTL Package 400mil 50pin TSOP II Note : 1. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied Rev. 3.6/Apr.01 HY57V161610D P IN C O N F IG U R A T IO N VDD 1 50 VSS DQ0 2 49 DQ15 DQ1 3 48 DQ14 VSSQ 4 47 VSSQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSSQ 10 41 VSSQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC A11 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 VSS 50pin TSOP-II 400mil x 825mil 0.8mm pin pitch P IN D E S C R IP T IO N PIN P I N N A M E D E S C R IPTIO N The system clock input. All other inputs are referenced to the SDRAM on the CLK Clock CKE Clock Enable CS Chip Select Command input enable or mask except CLK, CKE and DQM BA Bank Address Select either one of banks during both R A S a n d C A S activity. A0 ~ A10 Address Row Address Strobe, RAS, CAS, W E Column Address Strobe, Write Enable rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 R A S , C A S and W E define the operation. Refer function truth table for details LDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write mode DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin V D D /V S S Power Supply/Ground Power supply for internal circuit and input buffer V D D Q /V S S Q Data Output Power/Ground Power supply for DQ NC No Connection No connection Rev. 3.6/Apr.01 2 HY57V161610D F U N C T IO N A L B L O C K D IA G R A M 1Mx16 Synchronous DRAM R e f . A d d r.[0:11] Address[0:10] Row Decoder Refresh Counter Auto/Self Refresh Refresh Interval Timer Row Addr. Latch/ Predecoder Self Refresh Counter 512Kx16 Bank 0 Sense AMP & I/O gates Column Decoder CLK DQ0 Register Row Active CS RAS CAS State Machine BA(A11) C o l u m n A d d r. Column Active Latch & Counter Overflow Burst Length Counter W E Data Input/Output Buffers Precharge CKE DQ1 Address DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 UDQM DQ14 Column Decoder LDQM Row Addr. Latch/Predecoder Mode Register Rev. 3.6/Apr.01 DQ15 Sense AMP & I/O gates 512Kx16 Bank 1 Test Mode I/O Control 3 HY57V161610D A B S O L U T E M A X IM U M R A T IN G S Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TS T G -55 ~ 125 °C Voltage on Any Pin relative to V SS V IN , V O U T -1.0 ~ 4.6 V Voltage on V D D relative to V S S V DD -1.0 ~ 4.6 V Short Circuit Output Current IO S 50 mA Power Dissipation PD 1 W S o l d e r i n g T e m p e r a t u r e ·T i m e TS O L D E R 2 6 0 ·1 0 ° C ·S e c Note : Operation at above absolute maximum rating can adversely affect device reliability. D C O P E R A T IN G C O N D IT IO N Parameter ( T A = 0 °C t o 7 0 ° C ) Symbol Min Typ. Max Unit Note Power Supply Voltage V DD , V DDQ 3.0 3.3 3.6 V 1, 2, 3 Input high voltage V IH 2.0 3.0 V DD + 0.3 V 1, 4 Input low voltage V IL -0.5 0 0.8 V 1, 5 Note Note : 1.All voltages are referenced to V S S = 0V. 2.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 3.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 4 . V IH ( m a x ) i s a c c e p t a b l e 4 . 6 V A C p u l s e w i d t h w i t h ≤ 1 0 n s o f d u r a t i o n . 5 . V IL ( m i n ) i s a c c e p t a b l e - 1 . 5 V A C p u l s e w i d t h w i t h ≤ 1 0 n s o f d u r a t i o n . A C O P E R A T IN G C O N D IT IO N ( T A = 0 °C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V ) Parameter Symbol Value Unit AC input high / low level voltage V IH / V IL 2.4/0.4 V Vtrip 1.4 V tR / tF 1 ns Voutref 1.4 V CL 30 pF Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement 1 Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit. 2. V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s 3. V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V ‘ Rev. 3.6/Apr.01 4 HY57V161610D C A P A C IT A N C E ( T A = 2 5 °C , f = 1 M H z ) Parameter Pin Input capacitance Symbol Min Max Unit CLK CI1 2.5 4 pF A0 ~ A10, BA CI2 2.5 5 pF C I/O 4 6.5 pF C K E , C S, R A S , C A S, W E , U D Q M , L D Q M Data input / output capacitance DQ0 ~ DQ15 O U T P U T L O A D C IR C U IT V t t= 1 . 4 V R T=250 Ω Output Output 3 0p F 3 0p F DC Output Load Circuit D C C H A R A C T E R IS T IC S I ( T A = 0°C Parameter AC Output Load Circuit t o 7 0 °C ) Symbol Min. Max Unit Note Power Supply Voltage V DD 3.0 3.6 V 1, 2 Input leakage current IL -1 1 uA 3 Output leakage current IO -1 1 uA 4 Output high voltage VOH 2.4 - V IO H = - 4 m A Output low voltage VOL - 0.4 V IO L = + 4 m A Note : 1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s . 2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 3 . V IN = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t u n d e r t e s t = 0 V 4.D O U T is disabled, V O U T =0 to 3.6V Rev. 3.6/Apr.01 5 HY57V161610D D C C H A R A C T E R IS T IC S II ( T A = 0 ° C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V Note1,2) Speed Parameter Symbol Test Condition -5 -55 -6 -7 -8 -10 130 130 120 110 110 110 Unit Note mA 2 Burst Length=1, One bank active Operating Current ID D 1 tRAS ≥ tRAS(min),tRP ≥ tRP(min), IO=0mA Precharge Standby ID D 2 P C K E ≤ VIL(max), tCK = min. 1 ID D 2 P S C K E ≤ VIL(max), tCK = ∞ 1 Current in power down mode mA C K E ≥ VIH(min), C S ≥ VIH(min), tCK = min Precharge Standby ID D 2 N Current in non power down Input signals are changed one time during 2Clks. All other pins ≥ VDD-0.2V 20 mA or ≤ 0.2V mode ID D 2 N S C K E ≥ VIH(min), tCK = ∞ 15 Input signals are stable. ID D 3 P C K E ≤ VIL(max), tCK = min 30 ID D 3 P S C K E ≤ VIL(max), tCK = ∞ 30 Active Standby Current in power down mode mA C K E ≥ VIH(min), C S ≥ VIH(min), tCK = min Active Standby Current ID D 3 N in non power down Input signals are changed one time during 2CLKs. All other pins ≥ V D D - ID D 3 N S C K E ≥ VIH(min), tCK = ∞ IDD4 30 Input signals are stable t C K ≥ tCK(min), Current mA 0.2V or ≤ 0.2V mode Burst Mode Operating 50 CL=3 130 130 120 110 110 90 110 110 - - 110 110 110 110 tRAS ≥ tRAS(min), IO=0mA All banks active mA CL=2 Auto Refresh Current ID D 5 t R R C ≥ tRRC(min), All banks active Self Refresh Current ID D 6 C K E ≤ 0.2V 130 130 2 3 mA mA Note : 1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s . 2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 3.ID D 1 a n d I DD4 depend on output loading and cycle rates. Specified values are measured with the output open. Rev. 3.6/Apr.01 6 HY57V161610D A C C H A R A C T E R IS T IC S ( T A = 0 °C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V Note1,2 ) -5 Parameter -55 -6 -7 -8 -10 Symbol Unit Min Max M in Max M in Max M in Max M in Max M in Max Note CL=3 tCK3 5 5.5 6 - 7 - 8 - 10 - CL=2 tCK2 - - 10 - 10 - 12 - 12 - Clock high pulse width tCHW 1.75 2 2 - 2.5 - 3 - 3 - ns 4 Clock low pulse width tCLW 1.75 2 2 - 2.5 - 3 - 3 - ns 4 - 5.5 - 6 - 6 - 7 - 6 - 6 - 6 - 7 System clock cycle time Access time from clock ns CL=3 tAC3 CL=2 tAC2 4.5 5 3 ns 3 Data-out hold time tOH 1.5 2 2 - 2.5 - 2.5 - 2.5 - ns Data-Input setup time tDS 1.5 1.5 1.5 - 1.75 - 2 - 2.5 - ns 4 Data-Input hold time tDH 1 1 1 - 1 - 1 - 1 - ns 4 Address setup time tAS 1.5 1.5 1.5 - 1.75 - 2 - 2.5 - ns 4 Address hold time tAH 1 1 1 - 1 - 1 - 1 - ns 4 CKE setup time tCKS 1.5 1.5 1.5 - 1.75 - 2 - 2.5 - ns 4 CKE hold time tCKH 1 1 1 - 1 - 1 - 1 - ns 4 Command setup time tCS 1.5 1.5 1.5 - 1.75 - 2 - 2.5 - ns 4 Command hold time tCH 1 1 1 - 1 - 1 - 1 - ns 4 tOLZ 2 2 2 - 2 - 2 - 2 - ns tOHZ 2 2 6 2 7 2 8 3 10 ns CLK to data output in low Ztime CLK to data output in high Ztime 5 2 5.5 Note : 1.V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s . 2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610DTC-6 and HY57V161610DTC-7. 4.Assume tR / tF (input rise and fall time ) is 1ns. Rev. 3.6/Apr.01 7 HY57V161610D A C C H A R A C T E R IS T IC S ( T A = 0 °C t o 7 0 ° C , V D D = 3 . 0 V t o 3 . 6 V , V S S = 0 V Note1,2 )) -5 Paramter -55 -6 Symbol M in Max M in Max -7 -8 -10 M in M a x Min M a x M in M a x M in M a x U n it Operation tRC 55 55 60 - 70 - 70 - 70 - ns Auto Refresh tRRC 55 55 60 - 70 - 70 - 80 - ns R A S to C A S delay tRCD 15 16.5 18 - 20 - 20 - 20 - ns R A S active time tRAS 40 R A S precharge time tRP 3 3 3 - 3 - 3 - 2 - CLK R A S to R A S bank active delay tRRD 2 2 2 - 2 - 2 - 2 - CLK C A S to C A S bank active delay tCCD 1 1 1 - 1 - 1 - 1 - CLK Write command to data-in delay tWTL 0 0 0 - 0 - 0 - 0 - CLK Data-in to precharge command tDPL 1 1 1 - 1 - 1 - 1 - CLK Data-in to active command tDAL 4 4 4 - 4 - 4 - 3 - CLK DQM to data-in Hi-Z tDQZ 2 2 2 - 2 - 2 - 2 - CLK DQM to data mask tDQM 0 0 0 - 0 - 0 - 0 - CLK MRS to new command tMRD 2 2 2 - 2 - 2 - 2 - CLK Precharge to data output Hi-Z tPROZ 3 3 3 - 3 - 3 - 3 - CLK Power down exit time tPDE 1 1 1 - 1 - 1 - 1 - CLK Self refresh exit time tSRE 1 1 1 - 1 - 1 - 1 - CLK Refresh Time tREF 64 64 64 - 64 - 64 - 64 - ms Note R A S cycle time 100 K 38.5 100 K 40 100 K 45 100 K 45 100 K 45 100 K ns Note : 1. V DD ( m i n ) i s 3 . 1 5 V w h e n H Y 5 7 V 1 6 1 6 1 0 D T C - 7 o p e r a t e s a t C A S l a t e n c y = 2 a n d t C K 2 = 8 . 9 n s . 2.V DD ( m i n ) o f H Y 5 7 V 1 6 1 6 1 0 D T C - 5 / 5 5 i s 3 . 1 5 V 3. A new command can be given tRRC after self refresh exit. Rev. 3.6/Apr.01 8 3 HY57V161610D D E V IC E O P E R A T IN G O P T IO N T A B L E HY57V161610DTC-5 C A S Latency tRCD tRAS tRC tRP tAC tOH 2 0 0 M H z 3CLKs 3CLKs 8CLKs 11CLKs 3CLKs 4.5ns 1.5ns 1 8 3 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5ns 2ns 1 6 6 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns C A S Latency tRCD tRAS tRC tRP tAC tOH 1 8 3 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5ns 2ns 1 6 6 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 1 4 3 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2.5ns C A S Latency tRCD tRAS tRC tRP tAC tOH 1 6 6 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns 1 4 3 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2.5ns 1 2 5 M H z 3CLKs 2CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns C A S Latency tRCD tRAS tRC tRP tAC tOH 1 4 3 M H z 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2.5ns 1 2 5 M H z 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns 1 0 0 M H z 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 7ns 2.5ns C A S Latency tRCD tRAS tRC tRP tAC tOH 1 2 5 M H z 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns 1 0 0 M H z 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 7ns 2.5ns 8 3 M H z 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 7ns 2.5ns HY57V161610DTC-55 HY57V161610DTC-6 HY57V161610DTC-7 HY57V161610DTC-8 Rev. 3.6/Apr.01 9 HY57V161610D COMMAND TRUTH TABLE Command CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X Read A 0~ A 9 A10/ CKEn-1 Row Address Column Address Read with Auto precharge BA Note V L V H Write H X L H L L X Column Address Write with Auto precharge L V H Precharge All Bank H X L L H L X Precharge selected Bank Burst Stop H U/LDQM H Auto Refresh H H L L L Burst-READ-Single-WRITE H X L L Entry H L L X H Exit L H H L H H L X L V X V X H X X L L X L L H X X X X A9 Pin High (Other Pins OP code) X X L H H H H X X X L H H H H X X X L H H H H X X X L V V V L Precharge power H X X X Self Refresh1 Entry AP X X down Exit Entry L H H L Clock Suspend Exit L X H X X X X Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code, NOP=No Operation. Rev. 3.6/Apr.01 10 HY57V161610D P A C K A G E IN F O R M A T IO N 400mil 50pin Thin Small Outline Package (TC) 1Mx16 Synchronous DRAM V V V V UNIT : INCH (mm) 1 5 0 V S S D Q 0 2 4 9 D Q 1 5 D D Q 1 3 4 8 D Q 1 4 4 4 7 V S S Q S D S Q D Q 2 5 4 6 D Q 1 3 D Q 3 6 4 5 D Q 1 2 D 7 4 4 V D D Q D Q 4 8 4 3 D Q 1 1 D D Q 5 9 4 2 D Q 1 0 Q S Q S D Q Q D Q 0 4 1 V S S 1 1 4 0 D Q 9 7 3 9 D Q 8 3 8 V D D 3 7 N C 1 2 V D D Q 1 3 L D Q M 1 4 E 1 5 3 6 U D W 5 0 p i n T S O P - I I 4 0 0 m i l x 8 2 5 m i l 0 . 8 m m p i n p i t c h C A S 1 6 3 5 C L R A S 1 7 3 4 C K C S 1 8 3 3 N C A 1 1 1 9 3 2 A 9 A 1 0 2 0 3 1 A 8 A 0 2 1 3 0 A 7 A 1 2 2 2 9 A 6 A 2 2 3 2 8 A 3 2 4 2 7 A 4 2 5 2 6 V S A V Rev. 3.6/Apr.01 1 6 D D Q Q M K E 5 S 11